JP2005214980A - Macro inspection method for wafer and automatic wafer macro inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To automatically perform an appearance inspection of a pattern formed on a wafer. <P>SOLUTION: The automatic wafer macro inspection device used for the appearance inspection of the pattern formed on the surface of the wafer comprises an image detection part 16 detecting a surface image of the wafer to be inspected and a surface image of a reference wafer as an image to be inspected and a reference image, respectively; and an image processing part 18 mutually comparing the detected reference image and image to be inspected, and determining the propriety of the wafer to be inspected according to the result of comparison. The image detection part 16 comprises a coat/development failure inspection part 12 inspecting the pattern for coat failure and development failure. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wafer inspection method and a wafer inspection apparatus for inspecting a pattern formed on a wafer after completion of a photolithography process and an etching process in a semiconductor manufacturing process.

  In the semiconductor manufacturing process, after the formation of the resist pattern in the photolithography process or after the formation of the pattern in the etching process, it is necessary to inspect the state of the formed pattern. For example, with respect to the resist pattern, an inspection for defective coating such as whether the resist is uniformly coated is performed. Further, after the pattern exposure, a development state inspection for inspecting whether the development is uniformly performed, and a resolution defect inspection for checking whether the pattern exposure is performed normally are performed. Further, the formed pattern is inspected for scratches. In addition, regarding the etching pattern, it is inspected whether the etching is performed uniformly or inspected for the presence or absence of scratches. Conventionally, there are mainly the following two methods for performing these appearance inspections.

  The first method is a method called a micro inspection method in which a part of a pattern is enlarged using a metal microscope or the like, and the formation state of the pattern is actually judged visually. According to this method, a part on the wafer can be observed to inspect the details. However, recently, with the miniaturization of the pattern, it is difficult to distinguish the pattern even if it is enlarged with a metal microscope. Moreover, since the place to observe by magnifying is limited, the detection rate of defective products is lowered, and it takes time to make a wide observation place.

  The second method is a method of projecting uneven color on the wafer by irradiating the entire surface of the wafer from various angles with illumination means. If there is an abnormality in the pattern formed on the wafer, the color unevenness projected on the wafer appears to be different in color and brightness from the color unevenness due to the normal pattern, so it can be detected that there is a defective part. . In this way, a method in which the operator visually observes the color unevenness and determines the quality of the pattern is called a macro inspection method. Color unevenness is caused by irregular reflection caused by a step of about 1 μm to several μm in the pattern on the wafer.

  Since the macro inspection method is a method of observing the entire surface of the wafer, it is an effective method for detecting a defective state occurring only in a part on the wafer, such as unevenness of resist and unevenness of development. In this way, the macro inspection method, which observes the entire relatively large area, can increase the defective product detection rate and shorten the work time, compared to the micro inspection method by detailed observation at each point. Can do. Therefore, the importance of macro inspection methods has been increasing recently.

  However, conventionally, since the macro inspection has been performed visually, there has been a problem that the color unevenness and the state of scratches are changed depending on the angle of inclination of the wafer with respect to the illumination and the angle viewed by the operator. Therefore, the judgment criteria for defective products were ambiguous.

  In addition, since this inspection is always performed every time a pattern is formed, many inspections must be performed several tens of times before a wafer process is completed for one product. Therefore, the work efficiency has been significantly reduced.

  In addition, since the change in the height difference that occurs in the poorly coated portion or the poorly developed portion is relatively loose, it can be displayed as a variation in color unevenness. However, when there is a problem in the shape of the pattern, such as poor resolution, and the change in height difference is abrupt and the degree of change is subtle, it is difficult to project color unevenness.

  In addition, when the surface image of the wafer is detected by a camera, it is necessary to take an image with respect to the wafer obliquely so that the image of the camera itself reflected on the wafer is not detected. However, when the wafer is photographed obliquely as described above, a focus shift occurs between the side closer to the camera and the side farther from the camera. And a perspective difference arises and the pattern looks distorted. There is no problem if it always looks distorted in the same manner, but the degree of distortion easily changes due to disturbances such as slight positional deviation of the wafer. Accordingly, the way in which the background pattern is reflected becomes unstable, and an accurate inspection of the pattern formed on the background pattern that is the original inspection target cannot be performed.

  In addition, when the wafer is irradiated obliquely, the amount of light irradiated differs according to the distance to the illumination. Therefore, since the surface of the wafer is not uniformly irradiated with light, the appearance of color unevenness or the like appears differently depending on the position on the wafer. There is no problem as long as the irradiation is always performed in the same manner, but the irradiation state can be easily changed by the positional deviation of the wafer. Therefore, the way in which the base pattern is reflected becomes unstable, and an accurate inspection of the pattern formed on the base pattern that is the original inspection target cannot be performed.

  In addition, scratches formed on the pattern are regarded as lines. Even if such a line is detected by an image processing apparatus or the like, it is difficult to distinguish and recognize it from other patterns because the number of pixels is small. Also, if there is a disturbance element, it will be disturbed.

  Therefore, conventionally, there has been a demand for the appearance of a wafer macro inspection method and a macro inspection apparatus capable of efficiently inspecting a pattern with a constant determination criterion for quality.

  Therefore, according to the wafer macro inspection method of the present invention, the illumination unit irradiates the wafer with inspection light, the detection unit detects the surface image of the wafer under illumination of the inspection light, and the image processing unit When analyzing the detected surface image and inspecting the appearance of the pattern formed on the surface of the wafer, the surface image analysis is performed when the pattern coating is inspected for defective coating and development. Detecting a surface image of a reference wafer as a reference image by a unit, storing the reference image in an image memory unit, detecting a surface image of the wafer to be inspected as an inspection image by the detection unit, and the image Reading the reference image from the memory unit, comparing the reference image with the image to be inspected, and determining whether the inspection wafer is good or bad according to the result of the comparison. And wherein the Mukoto.

  In this way, the surface image of the wafer is detected by the detection unit, and the detected surface image is analyzed by the image processing unit. Then, by detecting the reference image and the inspection image and comparing these images, the pattern formed on the reference wafer serving as the inspection reference is compared with the pattern formed on the inspection wafer that is the inspection target. be able to. Therefore, it is possible to perform an appearance inspection for wafer coating defects and development defects. For example, if the detection unit and the image processing unit are controlled by a computer device, the appearance inspection can be automatically performed.

  In the wafer macro inspection method of the present invention, preferably, the comparison is performed by setting a reference template in the stored reference image, and using a brightness distribution of each pixel constituting the set reference template as a reference distribution. A step of recording in the first memory means; a step of setting a template to be inspected in a region of the detected image to be inspected corresponding to the reference template; and a brightness distribution of each pixel constituting the template to be inspected It is preferable to perform the steps of recording the distribution in the second memory means and reading the reference distribution and the distribution to be inspected from the first and second memory means and comparing the reference distribution and the distribution to be inspected. .

  In this way, templates are set for the reference image and the image to be inspected corresponding to the reference image, and these templates are matched. The matching is performed by calculating the brightness distribution of each template based on a conventionally known method. Then, by comparing the lightness distributions obtained for each template and obtaining the similarity (correlation rate), the matching rate of these templates can be obtained.

  In the wafer macro inspection method of the present invention, it is preferable that the reference template or the template to be inspected is set as a pattern on a surface image over the entire area of the surface of the detected reference wafer or the detected wafer to be inspected. A step of setting a formation region, a step of creating a lattice region by partitioning the pattern formation region in a lattice shape, and a step of setting the lattice region excluding the non-inspection region as the reference template or the template to be inspected. It is good to do with.

  The non-inspection area is an area unrelated to the product, unlike the inspection area where the chip is formed. Usually, this non-inspection area often contains prints or scratches. When the non-inspection area is included in the matching target, even if the formed pattern is normal, it is determined that the pattern is different from the reference wafer, and it is determined that the pattern formed on the wafer is abnormal. When the template is set as described above, a template from which the non-inspection area on the wafer is excluded can be set.

  According to the wafer macro inspection method of the present invention, the illumination unit irradiates the wafer with inspection light, the detection unit detects a surface image of the wafer under illumination of the inspection light, and the image processing unit In analyzing the detected surface image and performing the appearance inspection of the pattern formed on the surface of the wafer, when performing the inspection of the pattern scratch, the analysis of the surface image is performed by the detection unit by the reference wafer. Detecting the surface image of the wafer as a reference image, storing the reference image in an image memory unit, detecting the surface image of the wafer to be inspected by the detection unit as the image to be inspected, from the image memory unit, The method includes a step of reading a reference image, comparing the reference image with the image to be inspected, and determining whether the wafer to be inspected is good or bad according to a result of the comparison.

  In this way, the surface image of the wafer is detected by the detection unit, and the detected surface image is analyzed by the image processing unit. Then, by detecting the reference image and the inspection image and comparing these images, the pattern formed on the reference wafer serving as the inspection reference is compared with the pattern formed on the inspection wafer that is the inspection target. be able to. Therefore, it is possible to inspect the appearance of scratches on the wafer. For example, if the detection unit and the image processing unit are controlled by a computer device, the appearance inspection can be automatically performed.

  In the wafer macro inspection method of the present invention, preferably, the detection of the reference image and the detection of the image to be inspected are performed by extending an extension direction of a grid line formed on the reference wafer or the wafer to be inspected, and It is preferable that the direction perpendicular to the inspection light generating surface of the illuminating unit is set at an angle of substantially 45 °.

  Since the scratch is detected as a line, the number of pixels in the area corresponding to the detected scratch is very small. Therefore, when inspecting scratches, it is necessary to reduce the contrast by reducing the dark field as much as possible, and make it stand out from other patterns on the base pattern. Also, grid lines formed as boundaries between chips on the wafer can be a factor that confuses inspection. In order to detect as little reflected light as possible from the grid lines, the inspection light may be irradiated from an angle of 45 ° with respect to the extending direction of the grid lines.

  In the wafer macro inspection method of the present invention, it is preferable that the comparison is performed by applying an edge enhancement process to the stored reference image, and a first of each pixel constituting the reference area subjected to the edge enhancement process. Counting the number of pixels less than the brightness difference and the number of pixels greater than the second brightness difference as reference values, recording the reference values in the first memory means, and edge enhancement on the inspection image corresponding to the reference image A step of performing processing, and counting the number of pixels equal to or less than the first brightness difference and the number of pixels equal to or greater than the second brightness difference of each pixel constituting the inspected image subjected to the edge enhancement processing, The step of recording the value to be inspected in the second memory means, and the step of reading out the reference value and the value to be inspected from the first and second memory means, respectively, and comparing the reference value and the value to be inspected. Tsu is good to do with the flop.

  In this way, edge enhancement processing is performed on the reference image and the image to be inspected corresponding to the reference image, and the number of pixels in a certain brightness difference range is counted. Then, the degree of similarity between these images can be obtained by comparing the number of pixels obtained for each image.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, the wafer inspection apparatus is used for visual inspection of the pattern formed on the surface of the wafer, and each of the surface image of the wafer to be inspected and the surface image of the reference wafer is subjected to inspection. An image detection unit that detects an inspection image and a reference image, and an image processing unit that compares the detected reference image and the inspection image and determines the quality of the inspection wafer according to a result of the comparison. In the automatic wafer macro inspection apparatus, the image detection unit includes a coat / development defect inspection unit that inspects the pattern for defective coat and development failure.

  In this way, the image detection unit for detecting the surface image of the wafer and the image processing unit for analyzing the detected surface image are provided. The image detection unit includes a coat / development defect inspection unit for inspecting a coat defect and a development defect, and an image detected by the inspection unit is processed by the image processing unit described above. Therefore, it is possible to inspect the appearance of wafer defects and development defects. Further, for example, if the image detection unit and the image processing unit are controlled by a computer device, the appearance inspection can be automatically performed.

  In the automatic wafer macro inspection apparatus according to the present invention, it is preferable that the coat / development defect inspection unit performs diffuse illumination for irradiating diffused light onto the surface of the wafer and second detection for detecting the surface image of the wafer. And a support portion for supporting the wafer.

  Pattern coating defects and development defects can be examined by the uneven color projected on the wafer surface. Therefore, by irradiating the surface of the wafer with diffused light and detecting the surface image by the second detection unit, it is possible to inspect for a coat defect or a development defect of the pattern formed on the surface of the wafer. As the second detection unit, for example, an imaging unit using photoelectric conversion may be used.

  In the automatic wafer macro inspection apparatus of the present invention, it is preferable that the diffuse illumination has a function of changing the amount of light to be irradiated according to the type of the wafer and the pattern formed on the wafer. .

  In the automatic wafer macro inspection apparatus of the present invention, preferably, the diffused light is reflected toward the surface of the wafer, and the diffused light reflected from the surface of the wafer is directed toward the second detection unit. It is better to have a half mirror that allows the light to pass through.

  If such a half mirror is used, uniform diffused light can be irradiated toward the wafer, and illumination light reflected on the wafer can be detected by the second detection unit. Further, if this half mirror is provided between the imaging means of the image detection unit and the wafer, it is possible to prevent the image of the imaging means itself from being detected.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, the wafer inspection apparatus is used for visual inspection of the pattern formed on the surface of the wafer, and each of the surface image of the wafer to be inspected and the surface image of the reference wafer is subjected to inspection. An image detection unit that detects an inspection image and a reference image, and an image processing unit that compares the detected reference image and the inspection image and determines the quality of the inspection wafer according to a result of the comparison. In the automatic wafer macro inspection apparatus, the image detection unit includes a scratch inspection unit that inspects the pattern for scratches.

  In this way, the image detection unit for detecting the surface image of the wafer and the image processing unit for analyzing the detected surface image are provided. The image detection unit includes a scratch inspection unit that inspects scratches, and an image detected by the inspection unit is processed by the image processing unit described above. Therefore, it is possible to inspect the appearance of the scratch on the wafer. Further, for example, if the image detection unit and the image processing unit are controlled by a computer device, the appearance inspection can be automatically performed.

  In the automatic wafer macro inspection apparatus of the present invention, preferably, the scratch inspection unit includes spot illumination for irradiating the surface of the wafer with spot light, a third detection unit for detecting the surface image of the wafer, It is good to provide the support part which supports the said wafer.

  Scratches formed in the pattern are considered to be very thin groove-like foreign matters, so that using a spot light with directivity rather than a dim diffused light as illumination may cause strong irregular reflection at the groove portion. Easy to detect because it can. At this time, since the scratches are observed as white, it is preferable that the background color is dark.

  As described above, the surface of the wafer is irradiated with spot light, and the surface image is detected by the third detection unit, whereby it is possible to inspect the presence or absence of a pattern formed on the surface of the wafer. As the third detection unit, for example, an imaging unit using photoelectric conversion may be used.

  In the automatic wafer macro inspection apparatus of the present invention, it is preferable that the support portion has a mechanism for adjusting a relative position of the wafer with respect to the diffuse illumination.

  As described above, since the support portion has a function of adjusting the posture of the wafer, it is possible to set an irradiation angle suitable for the type and process.

  In the automatic wafer macro inspection apparatus according to the present invention, it is preferable that the spot illumination has a function of changing the amount of light to be irradiated according to the type of the wafer and the pattern formed on the wafer. .

  In the automatic wafer macro inspection apparatus of the present invention, preferably, the extending direction of the grid lines formed on the reference wafer or the wafer to be inspected, and the direction perpendicular to the inspection light generation surface of the illumination unit, The spot illumination may be provided so that the angle is substantially 45 °.

  Since the scratch is detected as a line, the number of pixels in the area corresponding to the detected scratch is very small. Therefore, when inspecting scratches, it is necessary to make the dark field as much as possible and to lower the contrast so that it stands out from other patterns on the base pattern. If the grid line formed as a boundary line between chips on the wafer is illuminated and strongly reflected, it becomes indistinguishable from the illumination reflected by the scratch, and it is difficult to detect the scratch. Therefore, in order to detect as little reflected light from the grid line as possible, the inspection light is irradiated from an angle of 45 ° with respect to the extending direction of the grid line.

  According to the wafer macro inspection method of the present invention, the surface image of the wafer is detected by the detection unit, and the detected surface image is analyzed by the image processing unit. Then, by detecting the reference image and the inspection image and comparing these images, the pattern formed on the reference wafer serving as the inspection reference is compared with the pattern formed on the inspection wafer that is the inspection target. be able to. Therefore, it is possible to perform an appearance inspection for wafer coating defects and development defects. For example, if the detection unit and the image processing unit are controlled by a computer device, the appearance inspection can be automatically performed. Therefore, the work man-hour can be significantly reduced. In addition, reliable inspection can be performed without depending on the skill level of the operator.

  According to the wafer macro inspection method of the present invention, templates are set for the reference image and the image to be inspected corresponding to the reference image, and the templates are matched. The matching is performed by calculating the brightness distribution of each template based on a conventionally known method. Then, by comparing the lightness distributions obtained for each template and obtaining the similarity (correlation rate), the matching rate of these templates can be obtained.

  According to the wafer macro inspection method of the present invention, the template in which the non-inspection area on the wafer is eliminated by setting the pattern formation area, dividing the pattern formation area, and setting the non-inspection area. Can be set. Accordingly, since an area unrelated to the product on the wafer can be excluded as a non-inspection area, accurate inspection can be performed.

  According to the wafer macro inspection method of the present invention, the surface image of the wafer is detected by the detection unit, and the detected surface image is analyzed by the image processing unit. Then, by detecting the reference image and the inspection image and comparing these images, the pattern formed on the reference wafer serving as the inspection reference is compared with the pattern formed on the inspection wafer that is the inspection target. be able to. Therefore, it is possible to inspect the appearance of scratches on the wafer. For example, if the detection unit and the image processing unit are controlled by a computer device, the appearance inspection can be automatically performed. Therefore, the work man-hour can be significantly reduced. In addition, reliable inspection can be performed without depending on the skill level of the operator.

  Further, according to the wafer macro inspection method of the present invention, since the inspection light is irradiated from an angle of 45 ° with respect to the extending direction of the grid line, the reflected light from the grid line is detected as little as possible. Can be done. Therefore, scratches are easily detected.

  Also, according to the wafer macro inspection method of the present invention, edge enhancement processing is performed on the reference image and the image to be inspected corresponding to the reference image, and the number of pixels within a certain brightness difference range is counted. Then, the degree of similarity between these images can be obtained by comparing the number of pixels obtained for each image.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, the image detecting unit for detecting the surface image of the wafer and the image processing unit for analyzing the detected surface image are provided. The image detection unit includes a coat / development defect inspection unit for inspecting a coat defect and a development defect, and an image detected by the inspection unit is processed by the image processing unit described above. Therefore, it is possible to inspect the appearance of wafer defects and development defects. Further, for example, if the image detection unit and the image processing unit are controlled by a computer device, the appearance inspection can be automatically performed. Therefore, it is possible to realize a remarkable reduction in the number of work steps and a reliable inspection that does not depend on the skill level of the worker.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, the surface of the wafer is irradiated with the diffused light and the surface image is detected by the second detection unit. Defects can be inspected.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, uniform diffused light can be irradiated toward the wafer by using the half mirror. The illumination light reflected on the wafer is detected by the second detector. Further, if this half mirror is provided between the imaging means of the image detection unit and the wafer, it is possible to prevent the image of the imaging means itself from being detected.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, the image detecting unit for detecting the surface image of the wafer and the image processing unit for analyzing the detected surface image are provided. The image detection unit includes a scratch inspection unit that inspects scratches, and an image detected by the inspection unit is processed by the image processing unit described above. Therefore, it is possible to inspect the appearance of the scratch on the wafer. Further, for example, if the image detection unit and the image processing unit are controlled by a computer device, the appearance inspection can be automatically performed. Therefore, it is possible to realize a remarkable reduction in the number of work steps and a reliable inspection that does not depend on the skill level of the worker.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, the surface of the wafer is irradiated with spot light and the surface image is detected by the third detection unit. Can be inspected.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, the support portion has a function of adjusting the posture of the wafer, so that it is possible to set the irradiation angle suitable for the type and process.

  Further, according to the automatic wafer macro inspection apparatus of the present invention, since the inspection light is irradiated from an angle of 45 ° with respect to the extending direction of the grid line, the reflected light from the grid line is detected as little as possible. Can be done. Therefore, scratches are easily detected.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Note that the drawing schematically shows the configuration, size, and arrangement relationship to the extent that the present invention can be understood, and the conditions such as the numerical values described below are merely examples, and therefore The present invention is not limited to this embodiment.

  The automatic wafer macro inspection apparatus is a wafer inspection apparatus used for appearance inspection of a pattern formed on the surface of a wafer. FIG. 1 is a block diagram showing a configuration of an automatic wafer macro inspection apparatus according to an embodiment. As shown in FIG. 1, this configuration example includes an image detection unit 16 and an image processing unit 18. The image detection unit 16 is an apparatus for detecting a surface image of a wafer to be inspected (wafer to be inspected) and a surface image of a reference wafer (wafer to be inspected) as an image to be inspected and a reference image, respectively. The image processing unit 18 is a device for comparing the detected reference image and the image to be inspected and determining the quality of the wafer to be inspected according to the comparison result.

  1 includes a resolution defect inspection unit 10, a coat / development defect inspection unit 12, and a scratch inspection unit 14. The resolution defect inspection unit 10 is an apparatus for inspecting a pattern resolution defect. The coat / development defect inspection unit 12 is an apparatus for inspecting pattern coat defects and development defects. And the crack inspection part 14 is an apparatus which test | inspects the presence or absence of the crack of a pattern. The images detected by these inspection units 10, 12 and 14 are sent to a common image processing unit 18 and analyzed. Hereinafter, the image detection unit 16 will be described first, and then the image processing unit 18 will be described.

[Image detector]
Hereinafter, the inspection units 10, 12, and 14 will be described in order.

<Configuration of defective resolution inspection section>
First, the resolution defect inspection unit 10 will be described. FIG. 2 is a diagram illustrating a configuration of the resolution failure inspection unit 10 and is referred to in conjunction with FIG. FIG. 2A shows a front view, and FIG. 2B shows a side view. The resolution defect inspection unit 10 shown in FIG. 1 is a view seen from a position corresponding to FIG.

  As described above, the resolution failure inspection unit 10 is an apparatus that inspects a resolution failure of a pattern formed on the surface of a wafer. As shown in FIGS. 1 and 2, the resolution defect inspection unit 10 supports a diffusion illumination 20 that irradiates the surface of the wafer with diffused light, a first detection unit 22 that detects the surface image of the wafer, and the wafer. And a support portion 24.

  A tilt-type wafer chuck is used as the support portion 24, and the wafer 26 is attracted to the chuck. The tilt type wafer chuck 24 can tilt the wafer 26 in an arbitrary direction, and has a function of rotating about the center of the chuck. Thus, the support 24 has a mechanism for adjusting the relative position of the wafer with respect to the diffuse illumination 20. Thereby, the posture of the wafer 26 is freely set. 2 shows a state where the wafer 26 is tilted to the left side in the drawing.

  The surface of the wafer 26 supported by the support unit 24 is irradiated with diffused light by the diffuse illumination 20 at the time of inspection. As the diffuse illumination 20, a halogen light source having a light emitting surface in a line shape (wide shape) is used. The diffuse illumination 20 is provided at a position obliquely above the wafer 26. Specifically, the diffuse illumination 20 is formed in the wafer by a distance corresponding to the length substantially the same as the diameter of the wafer 26 in the direction along the optical axis of the first detection unit 22 of the wafer 26 (dotted line b in FIG. 2). 26 is provided apart from 26. Further, the diffuse illumination 20 is provided at a position separated from the center of the wafer 26 by about 0.8 times the diameter of the wafer 26 in a direction orthogonal to the optical axis b. The illumination width of the diffuse illumination 20 is preferably about 1.8 times the diameter of the wafer 26 or more. The height and depth of the light emitting surface of the diffuse illumination 20 may be appropriate.

  A white acrylic plate (a in FIGS. 1 and 2) is provided as a diffusion plate on the entire light emitting surface of the diffuse illumination 20. The acrylic plate has a thickness of about 1 to 2 mm. As the diffusion plate, frosted glass may be used instead of the acrylic plate.

  In this embodiment, the diffuse illumination 20 is configured to allow fine adjustment of illuminance by remote control. By using this illuminance adjustment function, it is possible to perform an inspection with an optimum illuminance suitable for each case even when the pattern formed differs depending on the type of wafer or process. Further, as described above, the relative position between the diffuse illumination 20 and the wafer 26 can be adjusted to the optimum position by the support portion 24, so that the illumination can always be performed with the optimum illuminance from the optimum direction.

  As described above, the surface of the wafer 26 is irradiated with diffused light by the diffuse illumination 20 at the time of inspection for defective resolution. The surface image of the wafer 26 is detected by the first detection unit 22 under this illumination. The detected surface image is configured to be sent to the image processing unit 18.

  As the first detection unit 22, a camera having a photoelectric conversion function is used. The first detection unit 22 is provided at a position above the center of the wafer 26. The first detection unit 22 is separated from the wafer 26 by a distance that allows the entire wafer 26 to fall within the field of view captured by the detection unit 22. This distance varies depending on the diameter of the wafer and the focal length of the camera lens, but is approximately 150 to 250 mm. The output terminal of the first detection unit 22 is coupled to the input terminal of the image processing unit 18.

  Except for the first detection unit 22, the resolution failure inspection unit 10 described above is an external light blocking box 28 made of a black wall material in order to shield light other than the diffused illumination 20 from the wafer 26. Covered. The external light blocking box 28 has an opening from which the first detection unit 22 can observe the wafer 26.

<Principle of detection of resolution failure>
The principle of detection of resolution failure will be described with reference to FIG. The cross section of FIG. 3 shows the wafer 26 and the resist 30 stacked on the surface thereof. In addition, an uneven pattern is formed on the upper surface of the resist 30 as a result of exposure. In FIG. 3, a pattern normally expected (normal pattern) is a pattern formed in the resist region (normal pattern portion) on the left side of the figure from the line I. On the other hand, the pattern formed in the resist region (defective pattern portion) on the right side of the figure from the J line is a defective pattern. In the case of the defective pattern in the figure, the edge is rounded more than usual as indicated by point B.

  A point A in the figure is a planar region in the normal pattern portion of the resist 30. The light 1 incident on the point A obliquely from above is reflected at an angle similar to the incident angle to become reflected light 2 shown in FIG. In this way, the light that is normally reflected by the resist surface of the pattern portion is reflected at the same reflection angle as the incident angle. Therefore, the positional relationship between the first detection unit (camera) 22 and the wafer 26 can be adjusted so that the light reflected by the normal pattern portion is not detected by the first detection unit 22.

  Further, point B in the figure is at the surface position of the defective pattern portion of the resist 30. Unlike point A, point B is not a plane but a curved surface. Therefore, the light 3 incident on the point B at the same angle as the light 1 is reflected as the scattered light 4. A part of the scattered light 4 is reflected also in the direction of the camera 22 on the upper part of the wafer, and is thus detected by the camera 22. Therefore, the detected brightness can be different between the normal pattern portion and the defective pattern portion (at the same time, color unevenness occurs due to the influence of light interference). By recognizing this difference in brightness, it is possible to detect a resolution failure.

  In the normal pattern portion, the incident light 5 is reflected as scattered light 6 at the edge portion such as point C. However, since the edge of the point C is not rounded, the region where irregular reflection occurs is only a narrow region called the point C. On the other hand, since point B is a curved surface (in fact, it is not a beautiful curved surface and there are many discontinuous portions), there are many points that cause irregular reflection. Therefore, the ratio of reflecting light toward the camera is larger in the defective pattern portion than in the normal pattern portion. That is, the scattered light 4 generated at the point B is captured by the camera 22 more than the scattered light 6 generated at the point C. Therefore, the presence of a defective pattern is detected as a difference in brightness.

<Configuration of coat / development defect inspection section>
Next, the coating / development defect inspection unit 12 will be described. FIG. 4 is a diagram showing a configuration of the coat / development defect inspection unit 12 and is referred to in conjunction with FIG. FIG. 4A shows a front view, and FIG. 4B shows a side view. The coating / development defect inspection section 12 shown in FIG. 1 is a view seen from a position corresponding to FIG.

  As described above, the coat / development defect inspection unit 12 is an apparatus for inspecting a resist defect on a resist layered on a wafer surface or a pattern development defect. As shown in FIGS. 1 and 4, the coating / development defect inspection unit 12 supports a diffusion illumination 32 that irradiates the surface of the wafer with diffused light, a second detection unit 34 that detects the surface image of the wafer, and the wafer. And a support portion 36 for carrying out the operation.

  A fixed wafer chuck is used as the support portion 36, and the wafer 26 is attracted to the chuck. The surface of the wafer 26 supported by the fixed wafer chuck 36 is irradiated with diffused light by the diffuse illumination 32 at the time of inspection. As the diffuse illumination 32, surface illumination using an LED (light emitting diode) light source is used. Alternatively, a cathode tube light source may be used as the diffuse illumination 32.

  The diffuse illumination 32 is provided at a position obliquely above the wafer 26. The position where the diffuse illumination 32 is provided is a position separated from the wafer 26 by a distance of 10 to 50 mm in the direction along the optical axis of the second detection unit 34 of the wafer 26 (the dashed line b in FIG. 4). The diffuse illumination 32 is provided at a distance from the center of the wafer 26 by a distance corresponding to about 0.9 times the diameter of the wafer 26 in a direction orthogonal to the optical axis b. Both the illumination width and height of the diffuse illumination 32 are preferably about 1.8 times the diameter of the wafer 26 or more.

  A white acrylic plate (d in FIGS. 1 and 4) is provided as a diffusion plate on the entire light emitting surface of the diffuse illumination 32. The acrylic plate has a thickness of about 1 to 2 mm. As the diffusion plate, frosted glass may be used instead of the acrylic plate.

  In this embodiment, similarly to the diffused illumination 20, the diffused illumination 32 is configured to allow fine adjustment of illuminance by remote control. Therefore, even when the pattern formed differs depending on the kind of wafer, process, etc., the inspection can be performed with the optimum illuminance according to each case.

  As described above, at the time of inspection, the surface of the wafer 26 is irradiated with diffused light by the diffused illumination 32. Under this illumination, the surface image of the wafer 26 is detected by the second detector 34. As the second detection unit 34, a camera having a photoelectric conversion function is used. The second detection unit 34 is provided at a position above the center of the wafer 26. Further, the second detection unit 34 is provided apart from the wafer 26 by a distance that allows the entire wafer 26 to fall within the field of view captured by the detection unit 34. This distance varies depending on the diameter of the wafer and the focal length of the camera lens, but is approximately 500 to 600 mm.

  Further, a half mirror 38 is installed between the wafer 26 and the second detection unit 34. The half mirror 38 reflects the diffused light emitted from the diffuse illumination 32 toward the surface of the wafer 26 and transmits the diffused light reflected from the surface of the wafer toward the second detection unit 34. It is. The half mirror 38 is installed with its mirror surface inclined by an angle of 45 ° with respect to the surface of the wafer 26.

  The diffused light emitted from the diffuse illumination 32 is reflected toward the surface of the wafer 26 on the lower surface of the half mirror 38 (the e surface in FIG. 4B). Thereby, the diffused light is irradiated to the surface over the entire region of the wafer 26. The diffused light irradiated on the surface of the wafer 26 is reflected toward the upper side of the wafer 26. The reflected light passes through the half mirror 38 and is received by the second detection unit (camera) 34 provided above the wafer 26. Therefore, the surface image of the wafer 26 is detected.

  Further, the light emitted from the camera 34 toward the wafer 26 is reflected by the upper surface of the half mirror 38 (the f surface in FIG. 4B), and thus cannot reach the surface of the wafer 26. Therefore, the image of the camera 34 itself is not detected by the camera 34. Therefore, the image of the camera 34 itself does not obstruct the pattern image on the wafer 26 from being obstructed.

  The dimension of the half mirror 38 is such that the length in the lateral direction (the length in the direction perpendicular to the optical axis b in the plane of FIG. 4A) is 1.8 times or more the diameter of the wafer 26. The length in the vertical direction (the length along the e-plane or the f-plane in FIG. 4B) is at least 2.5 times the diameter of the wafer 26.

  The coating / development defect inspecting unit 12 described above, except for the second detecting unit 34, blocks the light other than the diffused illumination 32 from the upper surface 26 of the wafer so as to block the external light blocking box 28 made of a black wall material. Covered with. The external light blocking box 28 has an opening from which the second detection unit 34 can observe the wafer 26.

<Detection principle of defective coating and defective development>
The detection principle of defective coating and defective development will be described with reference to FIG. The cross section of FIG. 5 shows the wafer 26, a resist 40 (hereinafter referred to as a base pattern 40) laminated on the surface thereof, and a resist 42 coated on the base pattern 40. . The resist 42 is shown with hatching omitted. In addition, a pattern is formed on the actual resist 42 by exposure and development processes, which are omitted in this figure.

  Coat defects and development defects are mainly caused by gentle irregularities on the upper surface of the resist film. The light reflected from the upper surface of the base pattern 40 (secondary reflected light) and the light reflected from the upper surface of the resist 42 (primary reflected light) interfere with each other to generate color unevenness. If there are irregularities, the optical path length difference of these lights changes, so that the color or pattern changes depending on the location, and is detected as uneven color. Then, a coat defect or a development defect is detected by detecting a difference in color unevenness between the reference wafer and the wafer to be inspected.

  As described above, a defect pattern is detected by utilizing the fact that a difference occurs in the optical path length of the secondary reflected light depending on the film thickness, resulting in a difference in interference with the primary reflected light. As shown in FIG. 5, the light 1 incident on the point A is separated into primary reflected light 3 and light 2 transmitted through the resist 42. The light 2 is reflected from the upper surface of the base pattern 40 and is emitted from the resist 42 to become secondary reflected light 4. The secondary reflected light 4 propagates outside the resist 42 in a state parallel to the primary reflected light 3. At this time, since interference occurs between the two lights, the amplitude of the reflected light of the light 1 changes. This change in amplitude is affected by a change in the phase of the secondary reflected light 4 caused by the optical path length C1 (a distance corresponding to half the distance that the light 2 propagates through the resist 42).

  On the other hand, the light 5 incident on the point B is separated into the primary reflected light 7 and the light 6 propagating through the resist 42, similarly to the light 1. The light 6 is reflected outward from the resist 42 as secondary reflected light 8 and interferes with the primary reflected light 7. Since the optical path length C2 (a distance corresponding to half the distance that the light 6 propagates through the resist 42) is different from the optical path length C1, the phase change of the secondary reflected light 8 is the same as the secondary reflected light 4 described above. It is different. Accordingly, the amplitude of the reflected light of the light 5 incident on the point B is different from the amplitude of the reflected light of the light 1 incident on the point A. Therefore, a difference in brightness occurs (the degree of interference changes depending on the wavelength, and thus, a difference in color occurs precisely). By detecting this difference in lightness, it is possible to detect coating defects and development defects.

  It is preferable that the diffused illumination 32 can perform diffuse illumination as uniform as possible. The diffuse illumination 20 of the poor resolution inspection unit 10 is provided so that the diffused light is irradiated obliquely from above the wafer surface, whereas the diffused light having a certain degree of direction is generated. The diffuse illumination 32 of the coat / development defect inspection unit 12 is provided so that diffused light is irradiated as uniformly as possible on the entire surface of the wafer. By irradiating with diffused light in this way, the brightness difference (color difference) due to interference is further amplified and the detection becomes easy.

<Configuration of scratch inspection unit>
Next, the scratch inspection unit 14 will be described. FIG. 6 is a diagram illustrating a configuration of the scratch inspection unit 14, and is referred to in conjunction with FIG. 1. FIG. 6A shows a front view, and FIG. 6B shows a left side view. 1 is a view seen from a position corresponding to FIG. 6B.

  As described above, the flaw inspection unit 14 is an apparatus that inspects the presence or absence of flaws in the resist laminated on the wafer surface. As shown in FIGS. 1 and 6, the scratch inspection unit 14 includes a spot illumination 44 for irradiating the surface of the wafer with spot light, a third detection unit 46 for detecting the surface image of the wafer, and a support for supporting the wafer. Part 48.

  A vertical wafer chuck is used as the support portion 48, and the wafer 26 is adsorbed by this chuck. The vertical wafer chuck 48 is capable of moving the wafer 26 in the vertical direction in the figure, and has a function of rotating about the center of the chuck. Thus, the support 48 has a mechanism for adjusting the relative position of the wafer with respect to the spot illumination 44. Thereby, the installation height and rotation angle of the wafer 26 are freely set. 6 shows a state in which the wafer 26 is moved upward in the drawing.

  The surface of the wafer 26 supported by the support unit 48 is irradiated with spot light by the spot illumination 44 at the time of inspection. As the spot illumination 44, line illumination using a halogen light source is used. In this embodiment, two spot illuminations 44 a and 44 b are used as the spot illumination 44, which are provided on both sides of the wafer 26 so as to face each other. Therefore, the surface of the wafer 26 is irradiated with spot light by the two spot illuminations 44a and 44b.

  The illumination is provided on both sides of the wafer. The illumination on the wafer is uneven when only one side of the wafer is illuminated, and there is usually a difference in the contrast of the pattern area. The closer it is, the stronger it is.) Because only the scratches cannot be raised brightly.

  The spot illuminations 44 a and 44 b are provided obliquely above the wafer 26. The positions where the spot illuminations 44a and 44b are provided are positions separated from the wafer 26 by a distance of 0 to 30 mm in the direction along the optical axis of the third detection unit 46 of the wafer 26 (the dashed line b in FIG. 6). . The spot illumination 44 is provided at a distance from the center of the wafer 26 by a distance corresponding to a length of about 0.8 times the diameter of the wafer 26 in a direction orthogonal to the optical axis b. Each spot illumination 44a and 44b may have a light emitting surface of a size that can illuminate the entire area of the surface of the wafer 26. The illumination width of the spot illumination 44 is preferably about 1.6 times the diameter of the wafer 26 or more. The height and depth of the spot illumination 44 may be appropriate.

  In this embodiment, the spot illumination 44 is configured to allow fine adjustment of illuminance by remote control. By using this illumination together with the above-mentioned upper and lower wafer chucks, inspection can be performed with the optimum illuminance suitable for each case even when the patterns formed due to differences in wafer types and processes are different. Can do. That is, by setting the illumination angle (wafer height) and illuminance according to the pattern type (product type / process), it is always possible to maintain the normal pattern area with a small brightness difference (semi-dark field). Yes, only scratches appear brightly.

  As described above, at the time of inspection, the surface of the wafer 26 is irradiated with the spot light by the spot illumination 44. Then, the surface image of the wafer 26 is detected by the third detection unit 46 under this illumination. As the third detection unit 46, a camera having a photoelectric conversion function is used. The third detection unit 46 is provided at a position above the center of the wafer 26. Further, the third detection unit 46 is provided apart from the wafer 26 by a distance that allows the entire wafer 26 to fall within the field of view captured by the detection unit 46. This distance varies depending on the diameter of the wafer and the focal length of the camera lens, but is approximately 150 to 250 mm.

  Except for the third detection unit 46, the scratch inspection unit 14 described above is covered with an external light blocking box 28 made of a black wall material in order to shield light other than the spot illumination 44 from the wafer top 26. ing. The external light blocking box 28 has an opening from which the third detection unit 46 can observe the wafer 26.

<Scratch detection principle>
The flaw detection principle will be described with reference to FIG. The cross section of FIG. 7 shows the wafer 26 and the resist 42 laminated on the surface thereof and having a pattern already formed thereon.

  In FIG. 7, the scratch h is represented as unevenness formed in the resist 42. Then, the light is reflected by the slope portion g of the resist 42 forming the unevenness, and the presence or absence of a scratch is detected. Therefore, the detection of scratches is basically the same as the detection of poor resolution. However, the roundness of the edge of the defective pattern of poor resolution is as small as 1 micron or less, and the number per unit area is large, such as several thousand in a few millimeters square, whereas there are several tens of scratches. In most cases, it exists as a single line with large irregularities of micron to several hundred microns. If only one line is detected as defective, other disturbance elements (pattern images, etc.) must be eliminated as much as possible, which may lead to misrecognition during image processing. This is because it is extremely small in comparison.) Therefore, when detecting a flaw, it is necessary to irradiate the surface of the wafer with strong light from a horizontal direction as much as possible, and capture the reflected light of the flaw only with the camera.

  In FIG. 7, light 1 is light incident on the surface of the resist 42 in which no scratch is formed. The light 1 is reflected at the same angle as the incident angle. Light 2 is light incident on the sloped surface g of the scratch. The light 2 is reflected by the slope portion g and becomes scattered light 3. In the configuration example shown in FIG. 6, since the spot light is emitted from a substantially horizontal direction with respect to the surface of the wafer 26, the camera 46 provided above the wafer 26 detects the light reflected by other than the scratch. do not do. Therefore, the presence or absence of scratches is detected.

  In addition, the spot illumination 44 is provided so that the extending direction of the grid lines formed on the reference wafer or the wafer to be inspected and the direction perpendicular to the inspection light generation surface of the illumination unit are substantially at an angle of 45 °. Is provided. FIG. 8 is a view showing a state in which the wafer 26 and the spot illumination 44 are viewed from the viewpoint of the camera 46. On the wafer 26, boundary lines (this is referred to as grid lines) for separating chips are provided in a lattice shape. The grid line extending direction (x direction and y direction in FIG. 8) and the direction perpendicular to each light emitting surface (s plane and t plane in FIG. 8) of the spot illuminations 44a and 44b are 45. ° It is tilted. When the wafer and illumination are arranged in this way, it is possible to prevent the grid line from being illuminated and strongly reflected, making it indistinguishable from illumination reflected by scratches.

[Image processing unit]
Next, the image processing unit 18 will be described. The image processing unit 18 performs different processes on the images detected by the inspection units 10, 12, and 14 described above. Therefore, the image processing unit 18 is a device having different functions for each of the inspection units 10, 12, and 14. In this embodiment, the function of the image processing unit 18 will be described for each inspection unit. The image processing unit 18 may have a device configuration separated for each of these functions.

  As shown in FIG. 1, the image processing unit 18 includes an image processing device 50, a monitor 52, a device control personal computer (hereinafter simply referred to as a personal computer) 54, and a control monitor 56. It is provided as a component. As described above, the image processing apparatus 50 performs analysis by performing different processing on the image detected by each inspection unit. The output ports of the cameras 22, 34 and 46 of the inspection units 10, 12 and 14 are coupled to the input port of the image processing apparatus 50. The monitor 52 is used to display an image detected by each inspection unit or display a processing result of the image processing apparatus 50. The apparatus control personal computer 54 is coupled to the image processing apparatus 50 through a communication cable 80 so that data can be exchanged with the image processing apparatus 50. The apparatus control personal computer 54 controls the position of the camera, the position of the wafer, the illumination illuminance, and the like based on the data obtained by the image processing apparatus 50. If a control program is built in the personal computer 54, wafer macro inspection is automatically performed. The control monitor 56 is a display device for displaying control contents and the like. The image processing apparatus 50 and the apparatus control personal computer 54 may be configured as the same so-called computer apparatus.

  The automatic wafer macro inspection apparatus described in this embodiment is an apparatus that mainly executes the following four steps. That is, 1) a step of detecting a reference image, 2) a step of detecting an image to be inspected, 3) a step of comparing the reference image and the image to be inspected, and 4) a step of performing a determination.

  The above-described inspection for poor resolution, poor coating, poor development, and scratches starts by detecting a reference wafer surface image (reference image). The reference image is stored in the image memory unit. The pattern formed on the reference wafer (reference wafer) must be good. Only the determination of the quality of the pattern is performed by the operator visually displaying a surface image on the monitor 52, for example.

  Subsequently, the surface image of the wafer to be inspected (inspected wafer) is detected as the above-described inspected image. Then, the reference image stored in the image memory unit is called and compared with the detected image to be inspected. The comparison is performed by template matching or counting the number of pixels. The quality of the pattern formed on the wafer to be inspected is determined according to the result of this comparison.

  Note that the above-described steps 2) and 3) may be repeatedly performed (for example, when inspecting for a resolution failure). Hereinafter, the image processing unit 18 will be described in order for each of the inspection units 10, 12, and 14.

<Image processing for defective resolution inspection>
FIG. 9 is a block diagram illustrating a configuration of the image processing unit 18 that processes an image detected by the resolution failure inspection unit 10. As shown in FIG. 9, the image processing unit 18 includes an inspection area setting unit 58, a chuck control unit 60, an image memory unit 62, a comparison unit 64, and a determination unit 66.

  The inspection area setting unit 58 sets an inspection area in the surface area of the wafer to be inspected. In this resolution defect inspection, the surface image of the entire wafer surface is not detected at a time and compared with the reference image, but the area on the wafer is divided into a plurality of areas, and each divided area is compared with the reference image. Make a comparison. That is, the camera 22 of the resolution defect inspection unit 10 sequentially detects these divided areas as inspection areas. In this configuration example, since the optical axis of the camera 22 is fixed, the region on the wafer captured by the camera 22 is changed by moving the chuck 24.

  For this reason, the inspection area setting unit 58 receives information from outside such as how many regions the region on the wafer to be inspected is divided into. Further, not only the number of divided areas but also non-inspection areas on the wafer are input. These pieces of information are input by the operator via the personal computer 54 using input means such as a keyboard. Based on this information, the inspection area setting unit 58 controls other means.

  The inspection area set for the reference wafer is called a reference area, and the inspection area set for the wafer to be inspected is called an inspection area to distinguish them. In this resolution defect inspection, the reference area detected in advance and the inspection area corresponding to the reference area are compared, and the quality of the pattern formed in the inspection area is determined. The inspection will be conducted sequentially.

  The chuck control unit 60 controls the wafer chuck 24 based on a control signal sent from the inspection area setting unit 58 and a signal sent from another device constituting the image processing unit 18. Here, the chuck 24 changes the angle of the wafer 26 with respect to the optical axis of the camera 22 in order to change the region on the wafer to which the diffused light is irradiated. The chuck 24 also rotates the wafer 26 every 180 ° around an axis perpendicular to the wafer surface at the center of the wafer.

  FIG. 10 is a view showing two positional relationships between the wafer 26 and the diffuse illumination 20. FIG. 10A is a view of the side view shown in FIG. 10B viewed from the left side in the drawing. FIG. 10C is a view of the side view shown in FIG. 10D viewed from the left side in the drawing. The wafer 26 shown in FIG. 10B is inclined by an angle θ1 from the horizontal direction. Therefore, irradiation is performed in the region X near the illumination 20 and the region Z far from the illumination 20 on the wafer 26. The incident angle of the emitted light is different. That is, the irradiation angle a for the wafer 26 when detecting the surface image of the region X is different from the irradiation angle b for the wafer 26 when detecting the surface image of the region Z. As described above, when the irradiation angle is different, the way the pattern is seen is different, and it becomes impossible to accurately inspect the pattern.

  Therefore, as shown in FIG. 10D, when detecting the surface image of the region Z, the inclination angle θ2 of the wafer 26 may be made smaller than the angle θ1. Then, the incident angle c of the light applied to the region Z may be set to be the same as the angle a described above. Thus, by changing the tilt angle of the wafer, each surface image is always detected in the same irradiation state.

  When the inspection on the orientation flat (OF in the figure) side is performed, the wafer 26 may be rotated by 180 ° about an axis perpendicular to the central portion.

  Here, an image detection method (inspection area creation method) at the time of the poor resolution inspection will be described with reference to FIGS. 11, 12, and 13. Since the reference image and the inspection image are detected by the same method, the inspection image will be described as an example.

  First, an image of the entire surface of the wafer 26 is detected and displayed on the monitor 52. FIG. 11A shows a state of the surface image of the wafer when the direction orthogonal to the orientation flat of the wafer 26 (OF in FIG. 11A) is inclined by 30 ° from the horizontal direction. (That is, θ1 = 30 °). The wafer 26 is viewed from the camera 22 side. As shown in the figure, an LSI pattern is formed on the surface of the wafer. In the following, the LSI pattern is omitted for illustration.

  Then, in order to set an inspection area, an elliptical area is set on the wafer (FIG. 11B). The area of the inspection ellipse D1 is set by designating the horizontal diameter M1 and the vertical diameter L1 of the inspection ellipse D1. These numerical values are input to the inspection area setting unit 58 described above. Areas on the wafer other than the inspection area set in this way are not set as inspection areas.

  Next, an upper non-detection region and a lower non-detection region are determined (FIG. 11C). For this purpose, the upper boundary line j1 is set at a position separated from the center S of the inspection ellipse D1 by the upper vertical length N1 in the upper side in the figure. Further, a lower boundary line k1 is set at a position separated from the center S of the inspection ellipse D1 by a lower vertical length O1 in the lower side in the figure. Thereby, the surface area of the wafer 26 closer to the illumination than the upper boundary line j1 becomes the upper non-inspection area. Further, the surface area of the wafer 26 farther from the illumination than the lower boundary line k1 is a lower non-inspection area. As shown in FIG. 11D, the external area, upper non-inspection area, and lower non-inspection area of the inspection ellipse D1 are set as non-inspection areas, and other surface areas on the wafer 26 (FIG. 11D). A hatched area i1) is set as an inspection area (referred to as inspection area 1).

  Next, from the state shown in FIG. 11D, the wafer 26 is rotated by 180 ° about an axis perpendicular to the center S of the inspection ellipse D1 (FIG. 12A). Then, the inspection area i1 described above is set as the inspection area 2 this time.

  Next, from the state of FIG. 12A, the wafer 26 is further rotated by 180 ° to return to the original state (FIG. 11D). Then, the inclination angle of the wafer 26 is increased (θ1 = 45 °). In this state, the inspection ellipse D2 is set by setting the horizontal diameter M2 and the vertical diameter L2 (FIG. 12B).

  Subsequently, the upper non-inspection area and the lower non-inspection area are set by setting the upper vertical length N2 and the lower vertical length O2, that is, setting the upper boundary line j2 and the lower boundary line k2 (FIG. 12C). In this manner, the area on the wafer excluding the non-inspection area (the area i2 with a hatched line in FIG. 12D) is set as the inspection area 3 (FIG. 12D). Further, from this state, the region i2 is rotated 180 degrees around an axis perpendicular to the center S, and this time, the region i2 is set as the inspection area 4 (FIG. 13A).

  Further, the inclination angle of the wafer 26 is increased (θ1 = 60 °), and the inspection area 5 (region i3 in FIG. 13B) and the inspection area 6 (region i3 in FIG. 13C) are similarly formed. Set.

  As described above, the inspection area is set closer to the illumination as the inclination angle of the wafer is larger. Then, comparison and determination are performed for each setting of the inspection area, and the quality of the pattern is determined for each inspection area. That is, the inspection procedure proceeds such as setting of the wafer tilt angle, setting of the inspection area, detection of the inspection image, comparison between the reference image and the inspection image, and determination of the quality of the inspection image. By repeating this procedure a plurality of times while changing the inspection area, the quality of the pattern is determined over the entire surface of the wafer to be inspected.

  In performing the above-described procedure, the surface image detected for each inspection area is stored in the image memory unit 62, and comparison and determination are performed after the inspection area is detected over the entire area of the wafer surface. May be.

  Next, a detailed configuration of the comparison unit 64 will be described. In FIG. 9, the comparison unit 64 of this configuration example includes an edge processing unit 68, a pixel counting unit 70, and a pixel number comparison unit 72.

  The edge processing unit 68 is an apparatus that performs edge enhancement processing on the detected surface image of the wafer. The processing unit 68 applies edge enhancement processing to both the reference image and the image to be inspected. The edge enhancement process (differential filter) is a process normally used in image processing, and is also referred to as differentiation process. As a result of the edge enhancement processing, the boundary line in the reference image or the inspection image is enhanced. In this way, a portion having a large change in brightness in the image is extracted. Since the poor resolution portion is brighter than the other portions, the boundary is detected as a change point. In order to detect this poor resolution portion, a threshold value for density difference is set for each area.

  The pixel counting unit 70 uses, as a reference value or a value to be inspected, the number of pixels that are equal to or smaller than the first brightness difference and the number of pixels that are equal to or larger than the second brightness difference of each pixel that constitutes the reference area or the area to be inspected after edge enhancement It is a device for counting each and recording these reference values or values to be inspected in the memory means. Here, it is assumed that this memory means is provided in the pixel counting unit 70. It should be noted that once the reference value is counted, it is stored in the memory means later, and the reference value is also input to the pixel number comparing unit 72 at the timing when the value to be inspected is input to the pixel number comparing unit 72. What is necessary is just to comprise.

  The pixel number comparison unit 72 is a device that reads the reference value and the value to be inspected from the memory means, and compares the reference value and the value to be inspected. In this way, the comparison unit 64 outputs the result of comparison between the reference value and the value to be inspected. Here, the result of this comparison is output as the coincidence rate between the reference value and the value to be inspected. This matching rate is sent to the determination unit 66, and the determination unit 66 determines the quality of the pattern formed on the wafer to be inspected according to the matching rate. The determination result is sent to the apparatus control personal computer 54 and visually recognized on the control monitor 56 or the like. Then, the apparatus control personal computer 54 instructs the inspection area setting unit 58 to set the next area together with the input of the determination result.

  Here, the brightness difference distribution and the coincidence rate will be described. The distribution of the number of pixels for each brightness difference detected by the comparison unit 64 is referred to as a brightness difference distribution. This brightness difference distribution is obtained for each of the reference image and the inspected image, and is referred to as the reference brightness difference distribution and the inspected brightness difference distribution, respectively. For example, FIG. 14 shows an example of the brightness difference distribution with the brightness difference on the horizontal axis and the number of pixels on the vertical axis.

  The first graph in FIG. 14 is the reference lightness difference distribution obtained for the reference image, and the second and third graphs are the inspected lightness difference distribution obtained for the inspected image. It is. In the example of FIG. 14, the first-stage reference brightness difference distribution has a substantially target mountain shape. On the other hand, the second stage brightness difference distribution to be inspected has a shape in which the maximum point is shifted to the right side (high brightness difference side) in the figure as compared with the reference brightness difference distribution. Further, the inspected brightness difference distribution in the third stage has a shape in which the maximum point is shifted to the left side (low brightness difference side) in the figure as compared with the reference brightness difference distribution. In this manner, FIG. 14 shows two types of inspected brightness difference distributions having shapes different from the reference brightness difference distribution.

  First, the first reference value is obtained by counting the number of pixels equal to or smaller than the first lightness difference on the low lightness difference side (shaded area m1 in FIG. 14) in the first graph. Further, the second reference value is obtained by counting the number of pixels (shaded area n1 in FIG. 14) equal to or greater than the second brightness difference on the high brightness difference side in the first graph. Then, the number of pixels equal to or smaller than the first lightness difference (shaded area m2) in the second graph is counted as the first inspection value, and the number of pixels equal to or larger than the second lightness difference (hatched area n2) is counted. 2 Value to be inspected. In the third graph, the number of pixels equal to or smaller than the first brightness difference (shaded area m3) is counted as the first inspection value, and the number of pixels equal to or larger than the second brightness difference (hatched area n3) is counted. 2 Value to be inspected. In the pixel number comparison unit 72, the coincidence rate between the first inspected value and the first reference value and the coincidence rate between the second inspected value and the second reference value are obtained.

  Here, the coincidence rate is a value indicating how much the two quantities coincide. If a reference (threshold value) is set for this coincidence rate and is set to 60%, for example, if the coincidence rate of each pixel number is 60% or more, these pixel numbers are determined to be the same. It has become so.

  The coincidence rate between the first inspected value and the first reference value is sent to the determination unit 66 where it is compared with a threshold value. The number of pixels is determined to be the same for the first and second graphs in FIG. On the other hand, when the number of pixels below the first brightness difference (shaded areas m1 and m3) is compared with the first and third graphs, it is determined that they are not the same.

  Further, when the number of pixels equal to or greater than the second brightness difference (shaded areas n1 and n2) is compared with the first and second stages, it is determined that they are not the same. On the other hand, when the number of pixels greater than or equal to the second brightness difference (shaded areas n1 and n3) is compared with the first and third stages, they are determined to be the same.

  As a result, in the example described with reference to FIG. 14, it is determined that the inspected brightness difference distributions in the second and third stages are different from the reference brightness difference distribution. In the example described above, if only the first brightness difference is set, it is determined that the first graph and the second graph match. The difference between these graphs is recognized by setting the second brightness difference. In this way, since two boundary lines (upper limit value and lower limit value of the count number) for determining the area for counting the number of pixels, such as the first and second brightness differences, are set, only one is set. Compared to, accurate determination can be made. Two or more boundary lines may be set.

  As described above, the image processing is performed by setting the threshold value of the density difference and the upper limit value and lower limit value of the count number for each area. Then, the quality of the pattern is determined for each area. In this embodiment, if there is at least one area that is determined to be no, the wafer is determined to be defective.

<Image processing for coat defect inspection and development defect inspection>
The configuration of the image processing unit 18 that processes the image detected by the coat / development defect inspection unit 12 is the same as the configuration of the image processing unit 18 described with reference to FIG. Since only the configuration of the comparison unit 64 is different, this point will be described.

  FIG. 15 is a block diagram showing a configuration of the comparison unit 64 used for coating / development defect inspection. The comparison unit 64 of this configuration example includes a template setting unit 74, a lightness distribution reading unit 76, and a lightness distribution comparison unit 78.

  In the detection of poor resolution and the detection of scratches, a system is adopted in which the difference is recognized by making the pattern part a dark image (half-dark field) with as little change as possible and making only the defective part brightly raised. . On the other hand, in order to detect defective coating and defective development, a method of irradiating all parts on the wafer with uniform light and recognizing the visible state is adopted. As a recognition method (image processing method) in such a case, template matching is used. That is, first, a non-defective sample (surface image of a reference wafer) is divided into templates, and each pattern shape is stored in the apparatus. Then, at the time of inspection, templates at the same place are compared, and each correlation value (match rate) is calculated. If any one of the correlation values registered in advance is below, the wafer is determined to be defective.

  Template creation is done in a special way. The pattern on the wafer is mainly a repetition of the same pattern (chip), but the arrangement state varies depending on the type. Depending on the product type, different chips (chips for measuring and manufacturing transistors called “Teg”) may be mixed in several places. Further, some chips around the wafer are missing (see FIG. 16A). For these reasons, the entire wafer cannot be accurately inspected by storing chips as a template and repeatedly arranging them. Therefore, a special template creation method dedicated to the wafer is required. Hereinafter, the procedure will be described with reference to FIGS. 16 and 17.

  As can be seen from FIG. 16A, LSI patterns are formed as a set of chips on the wafer 26, but chips formed in a portion in contact with the outer periphery of the wafer are missing. The chip thus lacking does not become a product, so there is no need to inspect it. Therefore, an area excluding these chips is created as a template.

  First, an inspection circle E is set on the wafer surface (FIG. 16B). The inspection circle E is set by designating the diameter A of the inspection circle.

  Next, the outer frame T of the template is set (FIG. 16C). The horizontal dimension is the same as the diameter A of the inspection circle, and the vertical dimension is the remaining dimension B obtained by deleting the orientation flat side by an arbitrary length from the diameter A of the inspection circle.

  The template surrounded by the outer frame T is divided into an arbitrary number of rectangular regions (FIG. 17A). By designating the division number C, C × C rectangular regions having the same area are created as templates. In FIG. 17A, the outer frame T is divided into 4 × 4, and 16 templates a, b, c, d, e, f, g, h, i, j, k, l, m , N, o and p have been created.

  Next, a non-detection area (shaded area in FIG. 17B) is designated. In the previously created template, the part outside the inspection circle is excluded from the inspection target. As shown in FIG. 17B, templates a, b, c, d, e, h, i, l, m, n, o and p have their non-detection regions, and the shapes of these templates Is no longer rectangular.

  Finally, a template search area (search area) is designated (FIG. 17C). The search area is an area provided so that a target template can be found even when the inspection object is displaced. That is, if the positional deviation is within the search area, the inspection can be performed. By inputting a value D indicating how much larger than the length of one side of the template, the size and position of the search area are simultaneously determined. In FIG. 17C, only the search area for template a (the u area in FIG. 17C) is displayed, but the search areas are similarly set for templates b to p.

  According to the template created in this way, only a desired region can be set as a target region for template matching. Further, a template can be created according to the shape and size of the wafer.

  The template creation described above is performed by the template setting unit 74 described above. In the template setting unit 74, an inspection circle diameter A, a division number C, and the like are input in advance. The image memory unit 62 stores a reference image detected by the camera 34 and an inspection image. The reference image and the image to be inspected are surface images over the entire area of the wafer surface, unlike during the resolution defect inspection. Therefore, it is not detected for each area. Then, the template setting unit 74 reads the reference image or the image to be inspected from the image memory unit 62, and sets the template for this image by the method described above.

  Template matching is a method of comparing a plurality of images for each template. This comparison is a comparison of lightness distribution states of each pixel constituting the template. The lightness distribution reading unit 76 calls the template created by the template setting unit 74 and reads the lightness distribution of the pixels in the template. The lightness distribution reading unit 78 reads the lightness distribution of the pixels in the reference image and the lightness distribution of the pixels in the inspection image for each template, and outputs the read result to the lightness distribution comparison unit 78. The lightness distribution comparison unit 78 compares the lightness distribution of the pixels in the reference image with the lightness distribution of the pixels in the inspected image, and calculates the correlation value (match rate). This correlation value is output to the determination unit 66 as a comparison result.

  Here, as a method of comparing the brightness distribution of the pixels of the reference image and the image to be inspected, for example, a method called gray scale pattern matching, or mathematically, a method using a normalized two-dimensional correlation coefficient is used.

  In addition, the above-described lightness distribution is not a distribution representing the relationship between lightness and the number of pixels, but represents a lightness distribution for each position on the template.

  The determination unit 66 performs the same operation as described in the resolution failure inspection. If there is at least one template determined to be defective, the image to be inspected, that is, the pattern formed on the wafer to be inspected, is determined to be defective.

<Image processing for scratch inspection>
The configuration of the image processing unit 18 that processes the image detected by the scratch inspection unit 14 is the same as the configuration of the image processing unit 18 described with reference to FIG. The difference is that only one inspection area is set. That is, in the defect inspection, an area excluding the non-detection area from the surface image over the entire area of the wafer surface is set as the inspection area. Also, since the wafer is not tilted during the scratch inspection, only one inspection area is required.

  FIG. 18 is a diagram for explaining an area creation method at the time of scratch inspection. FIG. 18A shows a state in which the wafer is viewed from the viewpoint of the camera 46. In FIG. 18B, first, an inspection circle Q is set. The inspection circle Q is set by designating the diameter A. In this way, the non-detection area on the outer periphery of the inspection circle is set. Further, the remaining dimension B is set by deleting the orientation flat side by an arbitrary length from the inspection circle diameter A (FIG. 18C). In this way, the non-detection area on the orientation flat side is set. An area on the wafer excluding these non-detection areas is set as an inspection area (shaded area in FIG. 18D).

  After that, the inspection areas set for the reference image and the image to be inspected may be compared with each other. This comparison is performed by the pixel count method for each inspection area described in the resolution defect inspection. In other words, the number of pixels equal to or smaller than the first brightness difference and the number of pixels equal to or larger than the second brightness difference are counted as the reference value and the value to be inspected for the reference image and the image to be inspected, respectively. Then, the comparison unit 64 calculates the coincidence rate between the reference value and the value to be inspected, and the determination unit 66 determines whether the pattern is good or bad.

It is a figure which shows the structure of the automatic wafer macro inspection apparatus of embodiment. It is a figure which shows the structure of a resolution defect inspection part. It is a figure which shows the detection principle of a resolution failure. It is a figure which shows the structure of a coat | court and image development defect inspection part. It is a figure which shows the detection principle of a coating defect and a development defect. It is a figure which shows the structure of a damage inspection part. It is a figure which shows the detection principle of a crack. It is a figure which shows arrangement | positioning of illumination and a wafer. It is a figure which shows the structure of the image process part used for a resolution defect test | inspection. It is a figure which shows arrangement | positioning of a wafer and illumination. It is a figure which shows the preparation method of a test | inspection area. FIG. 12 is a diagram illustrating an inspection area creation method following FIG. 11. FIG. 13 is a diagram illustrating a method for creating an inspection area following FIG. 12. It is a figure which shows a brightness difference distribution graph. It is a figure which shows the structure of the comparison part used for a coating and image development defect test | inspection. It is a figure which shows the template preparation method. It is a figure which shows the template preparation method following FIG. It is a figure which shows the preparation method of a test | inspection area.

Explanation of symbols

10: Resolution failure inspection unit 12: Coat / development defect inspection unit 14: Scratch inspection unit 16: Image detection unit 18: Image processing unit 20, 32: Diffuse illumination 22: First detection unit 24: Tilt-type wafer chuck 26: Wafer 28: External light blocking box 30: Resist 34: Second detector 36: Fixed wafer chuck 38: Half mirror 40: Substrate pattern 42: Resist 44, 44a, 44b: Spot illumination 46: Third detector 48: Up and down Wafer chuck 50: image processing device 52: monitor 54: device control personal computer 56: control monitor 58: inspection area setting unit 60: chuck control unit 62: image memory unit 64: comparison unit 66: determination unit 68: edge processing Unit 70: pixel number counting unit 72: pixel number comparing unit 74: template setting unit 76: lightness distribution reading unit 78: lightness distribution comparing unit 80: communication cable

Claims (15)

The illumination unit irradiates the wafer with inspection light, the detection unit detects a surface image of the wafer under illumination of the inspection light, and the image processing unit analyzes the detected surface image to analyze the surface of the wafer In performing the appearance inspection of the pattern formed in
When inspecting the pattern for coating defects and development defects, the analysis of the surface image is as follows:
Detecting a surface image of a reference wafer as a reference image by the detection unit, and storing the reference image in an image memory unit;
Detecting a surface image of the wafer to be inspected as an inspection image by the detection unit;
Reading the reference image from the image memory unit and comparing the reference image with the image to be inspected;
And a step of determining the quality of the wafer to be inspected according to the result of the comparison. The wafer macro inspection method according to claim 1,
The comparison
Setting a reference template in the stored reference image;
Recording the brightness distribution of each pixel constituting the set reference template in the first memory means as a reference distribution;
Setting an inspected template in a region of the detected inspected image corresponding to the reference template;
Recording the brightness distribution of each pixel constituting the inspected template in the second memory means as the inspected distribution;
A wafer macro inspection method comprising: reading out the reference distribution and the inspection distribution from the first and second memory means, respectively, and comparing the reference distribution and the inspection distribution. The wafer macro inspection method according to claim 2,
The setting of the reference template or the inspected template is as follows:
Setting a pattern formation region on the surface image over the entire region of the detected reference wafer or the detected wafer surface;
Creating a lattice region by dividing the pattern formation region into a lattice shape;
And a step of using the lattice area excluding the non-inspection area as the reference template or the template to be inspected. The illumination unit irradiates the wafer with inspection light, the detection unit detects a surface image of the wafer under illumination of the inspection light, and the image processing unit analyzes the detected surface image to analyze the surface of the wafer In performing the appearance inspection of the pattern formed in
When examining the pattern scratch, the analysis of the surface image is:
Detecting a surface image of a reference wafer as a reference image by the detection unit, and storing the reference image in an image memory unit;
Detecting a surface image of the wafer to be inspected as an inspection image by the detection unit;
Reading the reference image from the image memory unit and comparing the reference image with the image to be inspected;
And a step of determining the quality of the wafer to be inspected according to the result of the comparison. The wafer macro inspection method according to claim 4,
Detection of the reference image and detection of the inspection image,
The extending direction of the grid lines formed on the reference wafer or the wafer to be inspected and the direction perpendicular to the inspection light generation surface of the illumination unit are performed at an angle of substantially 45 °. Wafer macro inspection method. The wafer macro inspection method according to claim 4,
The comparison
Applying edge enhancement processing to the stored reference image;
The number of pixels less than or equal to the first brightness difference and the number of pixels greater than or equal to the second brightness difference of each pixel constituting the edge enhancement processed reference area are counted as reference values, and the reference values are recorded in the first memory means. And steps to
Performing an edge enhancement process on the inspected image corresponding to the reference image;
The number of pixels equal to or smaller than the first brightness difference and the number of pixels equal to or greater than the second brightness difference of each pixel constituting the edge-enhanced image to be inspected are counted as the values to be inspected. 2 recording in a memory means;
A wafer macro inspection method comprising: reading out the reference value and the value to be inspected from the first and second memory means, respectively, and comparing the reference value and the value to be inspected. A wafer inspection apparatus used for appearance inspection of a pattern formed on a surface of a wafer, the image detection unit detecting a surface image of a wafer to be inspected and a surface image of a reference wafer as an image to be inspected and a reference image, respectively, In an automatic wafer macro inspection apparatus comprising an image processing unit that compares a detected reference image and an inspection image and determines the quality of the inspection wafer according to the comparison result,
The automatic wafer macro inspection apparatus, wherein the image detection unit includes a coat / development defect inspection unit that inspects the pattern for coating defects and development defects. The automatic wafer macro inspection apparatus according to claim 7,
The coat / development defect inspection section is
Diffuse illumination for irradiating diffused light on the surface of the wafer;
A second detector for detecting the surface image of the wafer;
An automatic wafer macro inspection apparatus comprising: a support portion for supporting the wafer.   9. The automatic wafer macro inspection apparatus according to claim 8, wherein the diffuse illumination has a function of changing an amount of light to be irradiated according to a type of the wafer and a pattern formed on the wafer. Automatic wafer macro inspection system. The automatic wafer macro inspection apparatus according to claim 8,
An automatic wafer comprising a half mirror that reflects the diffused light toward the surface of the wafer and transmits the diffused light reflected from the surface of the wafer toward the second detection unit. Macro inspection device. A wafer inspection apparatus used for appearance inspection of a pattern formed on a surface of a wafer, the image detection unit detecting a surface image of a wafer to be inspected and a surface image of a reference wafer as an image to be inspected and a reference image, respectively, In an automatic wafer macro inspection apparatus comprising an image processing unit that compares a detected reference image and an inspection image and determines the quality of the inspection wafer according to the comparison result,
The automatic wafer macro inspection apparatus, wherein the image detection unit includes a scratch inspection unit that inspects the pattern for scratches. The automatic wafer macro inspection apparatus according to claim 11,
The scratch inspection unit
Spot illumination for irradiating the surface of the wafer with spot light;
A third detector for detecting the surface image of the wafer;
An automatic wafer macro inspection apparatus comprising: a support portion for supporting the wafer. The automatic wafer macro inspection apparatus according to claim 12,
The automatic wafer macro inspection apparatus, wherein the support portion has a mechanism for adjusting a relative position of the wafer with respect to the diffuse illumination. The automatic wafer macro inspection apparatus according to claim 12,
2. The automatic wafer macro inspection apparatus according to claim 1, wherein the spot illumination has a function of changing an amount of light to be irradiated in accordance with a type of the wafer and a pattern formed on the wafer. The automatic wafer macro inspection apparatus according to claim 12,
The spot illumination so that the extending direction of the grid lines formed on the reference wafer or the wafer to be inspected and the direction perpendicular to the inspection light generation surface of the illumination unit are substantially at an angle of 45 °. An automatic wafer macro inspection apparatus characterized in that is provided.

Images