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JP2005167286A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2005167286A
JP2005167286A JP2005067089A JP2005067089A JP2005167286A JP 2005167286 A JP2005167286 A JP 2005167286A JP 2005067089 A JP2005067089 A JP 2005067089A JP 2005067089 A JP2005067089 A JP 2005067089A JP 2005167286 A JP2005167286 A JP 2005167286A
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JP
Japan
Prior art keywords
semiconductor chip
bonding wire
semiconductor
electrode
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005067089A
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Japanese (ja)
Inventor
Makoto Tsubonoya
誠 坪野谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2005067089A priority Critical patent/JP2005167286A/en
Publication of JP2005167286A publication Critical patent/JP2005167286A/en
Pending legal-status Critical Current

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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-chip type semiconductor device, wherein a space is provided in the chip back surface to enable the electrode pads hidden beneath a chip to be wire bonded. <P>SOLUTION: A first semiconductor chip 10 is fixed onto a film, and a second semiconductor chip 11 is fixed onto the first semiconductor chip 10. The first semiconductor chip 10 is connected to a lead terminal 41 through a first bonding wire 16a, and the second semiconductor chip 11 is connected to the lead terminal 41 through a second bonding wire 16b. The first and second semiconductor chips 10, 11 have mutually resembling sizes and shapes, and a first electrode pad is hidden by the second semiconductor chip 11 in plan view. The space is provided at a lower part of the end of the semiconductor chip 11, and the space is utilized to connect the first electrode pad to the second bonding wire. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、複数の半導体チップを重ね合わせてモールドしつつ、近似した大きさを持つ半導体チップの組み合わせでも小型化できる半導体装置に関する。   The present invention relates to a semiconductor device that can be miniaturized even by a combination of semiconductor chips having approximate sizes while superposing and molding a plurality of semiconductor chips.

半導体装置の封止技術として最も普及しているのが、図５（Ａ）に示したような、半導体チップ１の周囲を熱硬化性のエポキシ樹脂２で封止するトランスファーモールド技術である。半導体チップ１の支持素材としてリードフレームを用いており、リードフレームのアイランド３に半導体チップ１をダイボンドし、半導体チップ１のボンディングパッドとリード４をワイヤ５でワイヤボンドし、所望の外形形状を具備する金型内にリードフレームをセットし、金型内にエポキシ樹脂を注入、これを硬化させることにより製造される。   The most widespread as a sealing technique for a semiconductor device is a transfer mold technique for sealing the periphery of a semiconductor chip 1 with a thermosetting epoxy resin 2 as shown in FIG. A lead frame is used as a support material for the semiconductor chip 1, the semiconductor chip 1 is die-bonded to the island 3 of the lead frame, and the bonding pad of the semiconductor chip 1 and the lead 4 are wire-bonded with the wire 5 to have a desired outer shape. The lead frame is set in a mold to be manufactured, and an epoxy resin is injected into the mold and is cured.

一方、各種電子機器に対する小型、軽量化の波はとどまるところを知らず、これらに組み込まれる半導体装置にも、一層の大容量、高機能、高集積化が望まれることになる。   On the other hand, the wave of miniaturization and weight reduction for various electronic devices is not limited, and further higher capacity, higher functionality, and higher integration are desired for semiconductor devices incorporated therein.

そこで、以前から発想としては存在していた（例えば、特開昭５５ー１１１１５１７号）、１つのパッケージ内に複数の半導体チップを封止する技術が注目され、実現化する動きが出てきた。つまり図５（Ｂ）に示すように、アイランド３上に第１の半導体チップ１ａを固着し、第１の半導体チップ１ａの上に第２の半導体チップ１ｂを固着し、対応するボンディングパッドとリード端子４とをボンディングワイヤ５ａ、５ｂで接続し、樹脂２で封止したものである。
特開昭５５ー１１１１５１７号公報 Therefore, a technique that has existed as an idea for a long time (for example, Japanese Patent Application Laid-Open No. 55-1111517) has been attracting attention and a movement to realize it has attracted attention. That is, as shown in FIG. 5B, the first semiconductor chip 1a is fixed on the island 3, the second semiconductor chip 1b is fixed on the first semiconductor chip 1a, and the corresponding bonding pads and leads are fixed. The terminal 4 is connected with bonding wires 5 a and 5 b and sealed with a resin 2.
JP 55-1111517 A

図５（Ｂ）の構成は、第１の半導体チップ１ａとのワイヤボンディングを確保するため、第２の半導体チップ１ｂを固着したときに第１の半導体チップ１ａの電極パッド部分が露出していること、即ちチップサイズに差のあることが絶対的な条件となる。そのため、例えば同一機種のチップを２個組み込む、或いは別機種のチップであってもそのチップサイズが近似する場合には採用できない欠点があった。２つの半導体チップを十文字に重ね合わせることも考えられるが、これとてチップサイズの縦×横の寸法に差があることが条件となり、依然として制約が残るものである。   In the configuration of FIG. 5B, the electrode pad portion of the first semiconductor chip 1a is exposed when the second semiconductor chip 1b is fixed in order to secure wire bonding with the first semiconductor chip 1a. That is, the difference in chip size is an absolute condition. For this reason, for example, there are disadvantages that cannot be adopted when two chips of the same model are incorporated, or even if the chip size is similar even if the chips are of different models. It is conceivable to superimpose two semiconductor chips on a cross, but this still requires that there is a difference in the vertical and horizontal dimensions of the chip size, and there are still restrictions.

これを解決するために、例えば図５（Ｃ）に示すように、アイランド３の両面に各半導体チップ１ａ、１ｂの裏面が対向するようにこれらを固着する手法がある。しかしながら、ボンディングワイヤのループ高さの分が２倍必要になるので、半導体装置全体の厚み（図５（Ｃ）の図示Ｘ）が増して、薄形化できない欠点がある。   In order to solve this, for example, as shown in FIG. 5C, there is a method of fixing these so that the back surfaces of the semiconductor chips 1a and 1b face both surfaces of the island 3. However, since it is necessary to double the loop height of the bonding wire, the thickness of the entire semiconductor device (X shown in FIG. 5C) increases, and there is a drawback that it cannot be thinned.

本発明は上述した従来の課題に鑑み成されたもので、第一に、樹脂フィルムと、前記樹脂フィルム上に形成されたリード端子に相当する導電パターンと、前記導電パターンに電気的に接続され、前記樹脂フィルムに接着固定された第１の半導体チップと、前記第１の半導体チップ上に積層固定された第２の半導体チップと、 前記導電パターンの裏面に相当する前記樹脂フィルムに設けられた貫通穴と、前記樹脂フィルムの表面、前記導電パターン、前記第１の半導体チップおよび前記第２の半導体チップを封止する封止樹脂とを有し、
一方の半導体チップのＩ／Ｏ端子と他方の半導体チップのアドレス端子は、前記導電パターンに共用して接続され、イネーブル信号の印加によりどちらかの半導体チップを排他的に選択する事で解決するものである。
第２に、第１の半導体チップ及び前記第１の半導体チップ上に積層された第２の半導体チップと、前記第１及び第２の半導体チップの各第１主面に形成された第１及び第２の電極と、前記第１の電極上方と前記第２の半導体チップの第２主面との間に設けられる空間部と、前記第１の電極と一方が接続され前記空間を通過して延在される第１のボンディングワイヤーと、前記第２の電極と一方が接続されて延在される第２のボンディングワイヤーと、前記第１のボンディングワイヤーの他方および前記第２のボンディングワイヤーの他方が接続される外部接続用の電極手段とを有する半導体装置の製造方法であり、
所定の固着部に前記第１の半導体チップを固着した後、
前記第１の電極と一方を接続し、前記第１のボンディングワイヤーは、前記空間部を通過して横方向に導出され、前記第２の半導体チップの端より上昇する奇跡を描きながら前記第１のボンディングワイヤーの他方を前記電極手段に接続し、
前記第１のボンディングワイヤが、前記空間部に収まるように、前記第１の半導体チップ上に前記第２の半導体チップを固着し、
前記第２の電極と前記電極手段とを第２のボンディングワイヤで接続することで解決するものである。 The present invention has been made in view of the above-described conventional problems. First, a resin film, a conductive pattern corresponding to a lead terminal formed on the resin film, and the conductive pattern are electrically connected. A first semiconductor chip bonded and fixed to the resin film; a second semiconductor chip stacked and fixed on the first semiconductor chip; and the resin film corresponding to the back surface of the conductive pattern. A through-hole, and a sealing resin that seals the surface of the resin film, the conductive pattern, the first semiconductor chip, and the second semiconductor chip;
The I / O terminal of one semiconductor chip and the address terminal of the other semiconductor chip are connected in common to the conductive pattern, and can be solved by exclusively selecting one of the semiconductor chips by applying an enable signal It is.
Second, the first semiconductor chip, the second semiconductor chip stacked on the first semiconductor chip, and the first and second semiconductor chips formed on the first main surfaces of the first and second semiconductor chips. One of the second electrode, the space provided between the first electrode and the second main surface of the second semiconductor chip, and one of the first electrodes are connected and pass through the space. A first bonding wire that is extended, a second bonding wire that is extended with one of the second electrodes connected thereto, the other of the first bonding wire and the other of the second bonding wire Is a method of manufacturing a semiconductor device having external connection electrode means to which is connected,
After fixing the first semiconductor chip to a predetermined fixing portion,
One of the first electrodes is connected to the first electrode, and the first bonding wire passes through the space portion and is led out in a lateral direction, and draws a miracle rising from an end of the second semiconductor chip. Connecting the other bonding wire to the electrode means,
Fixing the second semiconductor chip on the first semiconductor chip so that the first bonding wire fits in the space;
The problem is solved by connecting the second electrode and the electrode means with a second bonding wire.

以上に説明した通り、本発明によれば、積層された複数の半導体チップのそれぞれに設けられた電極をすべてリード端子に接続することなく共用させることにより、リード端子の数を減らすことができる。   As described above, according to the present invention, it is possible to reduce the number of lead terminals by sharing all the electrodes provided on each of the stacked semiconductor chips without connecting them to the lead terminals.

また空間を利用して第１のボンディングワイヤをボンディングするので、半導体チップ１０、１１の大きさと形状が近似した場合でも複数の半導体チップを積層してワイヤボンディングが可能になる利点を有する。これにより、例えば１つのパッケージに２倍の記憶容量を持たせることが可能になる。   In addition, since the first bonding wire is bonded using the space, even when the size and shape of the semiconductor chips 10 and 11 are approximated, there is an advantage that a plurality of semiconductor chips can be stacked to perform wire bonding. As a result, for example, one package can have twice the storage capacity.

以下に本発明の一実施の形態を詳細に説明する。   Hereinafter, an embodiment of the present invention will be described in detail.

先ず、図１は本発明の半導体装置の主要部を示す断面図、図２（Ａ）は全体を示す断面図、同じく図２（Ｂ）は全体を示す平面図である。   First, FIG. 1 is a sectional view showing the main part of the semiconductor device of the present invention, FIG. 2A is a sectional view showing the whole, and FIG. 2B is a plan view showing the whole.

これらの図において、１０、１１は各々第１と第２の半導体チップを示している。第１と第２の半導体チップ１０、１１のシリコン表面には、前工程において各種の拡散熱処理などによって多数の能動、受動回路素子が形成されている。第１と第２の半導体チップ１０、１１のチップ周辺部分には外部接続用の第１と第２の電極パッド１２ａ、１２ｂがアルミ電極によって形成されている。各電極パッド１２ａ、１２ｂの上にはパッシベーション皮膜が形成され、電極パッド１２ａ、１２ｂの上部が電気接続のために開口されている。パッシベーション被膜はシリコン窒化膜、シリコン酸化膜、ポリイミド系絶縁膜などである。図２（Ｂ）の例では、各電極パッド１２ａ、１２ｂは半導体チップ１０、１１の対向する２辺に沿って集約して配置されている。   In these drawings, reference numerals 10 and 11 denote first and second semiconductor chips, respectively. A large number of active and passive circuit elements are formed on the silicon surfaces of the first and second semiconductor chips 10 and 11 by various diffusion heat treatments in the previous step. First and second electrode pads 12a and 12b for external connection are formed of aluminum electrodes in the peripheral portions of the first and second semiconductor chips 10 and 11. A passivation film is formed on each electrode pad 12a, 12b, and the upper part of electrode pad 12a, 12b is opened for electrical connection. The passivation film is a silicon nitride film, a silicon oxide film, a polyimide insulating film, or the like. In the example of FIG. 2B, the electrode pads 12a and 12b are collectively arranged along two opposing sides of the semiconductor chips 10 and 11.

第１の半導体チップ１０がリードフレームのアイランド１３上に接着剤１４に
よりダイボンドされる。第２の半導体チップ１１が第１の半導体チップ１０の前記パッシベーション皮膜上に接着剤１５により固着されている。接着剤１４は導電性または絶縁性、接着剤１５は絶縁性のエポキシ系接着剤である。 The first semiconductor chip 10 is die-bonded with an adhesive 14 on the island 13 of the lead frame. A second semiconductor chip 11 is fixed on the passivation film of the first semiconductor chip 10 with an adhesive 15. The adhesive 14 is conductive or insulating, and the adhesive 15 is an insulating epoxy adhesive.

第１の電極パッド１２ａには、金線からなる第１のボンディングワイヤ１６ａの一端が接続されており、第１のボンディングワイヤ１６ａの他端は外部導出用のリード端子１７にワイヤボンドされている。また、第２の電極パッド１２ｂの表面には、第２のボンディングワイヤ１６ｂの一端がワイヤボンドされており、第２のボンディングワイヤ１６ｂの他端は外部導出用のリード端子１７にワイヤボンドされている。   One end of a first bonding wire 16a made of a gold wire is connected to the first electrode pad 12a, and the other end of the first bonding wire 16a is wire-bonded to an external lead terminal 17. . One end of the second bonding wire 16b is wire-bonded to the surface of the second electrode pad 12b, and the other end of the second bonding wire 16b is wire-bonded to the lead terminal 17 for external lead-out. Yes.

第１と第２の半導体チップ１０、１１、リード端子１７の一部、および第１と第２のボンディングワイヤ１６ａ、１６ｂを含む主要部は、周囲をエポキシ系の熱硬化樹脂１８でモールドされて半導体装置のパッケージを形成する。リード端子１７はパッケージの側壁から外部に導出されて外部接続端子となる。導出されたリード端子１７はＺ字型に曲げ加工されている。アイランド１３の裏面側は樹脂１８の表面に露出しており、樹脂１８表面と同一平面を形成している。   The main parts including the first and second semiconductor chips 10 and 11, a part of the lead terminal 17, and the first and second bonding wires 16 a and 16 b are molded with an epoxy-based thermosetting resin 18. A semiconductor device package is formed. The lead terminal 17 is led out from the side wall of the package and becomes an external connection terminal. The derived lead terminal 17 is bent into a Z-shape. The back side of the island 13 is exposed on the surface of the resin 18 and forms the same plane as the surface of the resin 18.

第１と第２の半導体チップ１０、１１の組み合わせは任意である。例えば、第１と第２の半導体チップ１０、１１としてＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶装置を用いた場合（第１の組み合わせ例）は、１つのパッケージで記憶容量を２倍、３倍・・・にすることができる。また、第１の半導体チップ１０にＥＥＰＲＯＭ（フラッシュメモリ）等の半導体記憶装置を、第２の半導体チップ１１にはＳＲＡＭ等の半導体記憶装置を形成するような場合（第２の組み合わせ例）ことも考えられる。どちらの組み合わせの場合でも、各チップにはデータの入出力を行うＩ／Ｏ端子と、データのアドレスを指定するアドレス端子、及びデータの入出力を許可するチップイネーブル端子とを具備しており、両チップのピン配列が酷似している。そのため、第１と第２の半導体チップ１０、１１のＩ／Ｏ端子やアドレス端子用のリード端子１７を共用することが可能であり、各チップに排他的なチップイネーブル信号を印加することにより、どちらか一方の半導体チップのメモリセルを排他的に選択することが可能である。   The combination of the first and second semiconductor chips 10 and 11 is arbitrary. For example, when a semiconductor storage device such as an EEPROM (flash memory) is used as the first and second semiconductor chips 10 and 11 (first combination example), the storage capacity is doubled, tripled,・ ・In some cases, a semiconductor memory device such as an EEPROM (flash memory) is formed on the first semiconductor chip 10 and a semiconductor memory device such as an SRAM is formed on the second semiconductor chip 11 (second combination example). Conceivable. In either combination, each chip has an I / O terminal for inputting / outputting data, an address terminal for designating an address of data, and a chip enable terminal for permitting input / output of data, The pin arrangement of both chips is very similar. Therefore, it is possible to share the I / O terminal of the first and second semiconductor chips 10 and 11 and the lead terminal 17 for the address terminal, and by applying an exclusive chip enable signal to each chip, It is possible to exclusively select the memory cells of either one of the semiconductor chips.

上記第１の組み合わせ例の場合には当然の事ながら、第１の半導体チップ１０と第２の半導体チップ１１が大略同じ大きさと形状を有し、電極パッド１２ａ、１２ｂの配列も同じである。そのため、両者を重ねると、第１の半導体チップ１０の電極パッド１２ａが第２の半導体チップ１１の陰に隠れる。具体的に、図２（Ｂ）の例では第２の電極パッド１２ｂの直下に第１の電極パッド１２ａが位置する。又第２の組み合わせ例の場合でも、チップサイズと形状が近似し且つピン配列が酷似する場合があり得る。   In the case of the first combination example, as a matter of course, the first semiconductor chip 10 and the second semiconductor chip 11 have substantially the same size and shape, and the arrangement of the electrode pads 12a and 12b is also the same. Therefore, when both are overlapped, the electrode pad 12 a of the first semiconductor chip 10 is hidden behind the second semiconductor chip 11. Specifically, in the example of FIG. 2B, the first electrode pad 12a is located immediately below the second electrode pad 12b. Even in the case of the second combination example, the chip size and shape may be approximated and the pin arrangement may be very similar.

而して、第２の半導体チップ１２ｂの対向する２辺に沿って、第１の電極パッド１２ａの上方に凹部１９を形成し、第２の半導体チップ１１をひさし状に突出させている。凹部１９は第１の半導体チップ１０の端部から第１の電極１２ａを露出するだけの幅（図１：Ｗ）を持ち、更には第１のボンディングワイヤ１６ａのワイヤ高さ（図１：ｔ１）を収納するだけの高さを持つ。本実施の形態では、第２の半導体チップ１１の裏面をダイシングブレードによって厚みの約半分程度（図１：ｔ２）を研削することにより、前記収納する高さを実現している。尚、前記収納する高さは第１の半導体チップ１０の表面からの高さであるから、接着剤１５の膜厚も考慮してダイシングする深さ（ｔ２）を決定する。   Thus, the concave portion 19 is formed above the first electrode pad 12a along the two opposing sides of the second semiconductor chip 12b, and the second semiconductor chip 11 is projected in an eaves shape. The recess 19 has a width (FIG. 1: W) sufficient to expose the first electrode 12a from the end of the first semiconductor chip 10, and further has a wire height (FIG. 1: t1) of the first bonding wire 16a. ) Enough to store. In the present embodiment, the height of the second semiconductor chip 11 is realized by grinding the back surface of the second semiconductor chip 11 by about a half of the thickness (FIG. 1: t2) with a dicing blade. Since the height to be stored is the height from the surface of the first semiconductor chip 10, the dicing depth (t 2) is determined in consideration of the film thickness of the adhesive 15.

凹部１９は第１の電極パッド１２ａの上方に空間を形成し、この空間内で第１のボンディングワイヤ１６ａが第１の電極パッド１２ａにボールボンディングされている。ボール部２０から連続する第１のボンディングワイヤ１６ａは凹部１９を通過し、リード端子１７にセカンドボンドされる。第１の半導体チップ１０の表面の高さに対してリード端子１７の表面が高いような場合には、第１のボンディングワイヤ１６ａは第１の電極１２ａから凹部１９を通過して横方向に導出され、第２の半導体チップ１１の端より外側で上昇し、リード端子１７先端部に到達する様な軌跡を描く。接着剤１５は第１と第２の半導体チップ１０、１１の間で両者を固着すると共に、凹部１９にも流出し、第１のボンディングワイヤ１２ａのボール部２０周辺を包み込んで凹部１９を充満するように固化している。凹部１９で固化した接着剤１５は、第２の電極パッド１２ｂに第２のボンディングワイヤ１６ｂを接着するときに、第２の半導体チップ１１を支持する役割を果たす。   The recess 19 forms a space above the first electrode pad 12a, and the first bonding wire 16a is ball-bonded to the first electrode pad 12a in this space. The first bonding wire 16 a continuous from the ball portion 20 passes through the recess 19 and is second-bonded to the lead terminal 17. When the surface of the lead terminal 17 is higher than the height of the surface of the first semiconductor chip 10, the first bonding wire 16a passes through the recess 19 from the first electrode 12a and is led out laterally. Then, a locus is drawn that rises outside the end of the second semiconductor chip 11 and reaches the tip of the lead terminal 17. The adhesive 15 fixes both the first and second semiconductor chips 10 and 11, and also flows out into the recess 19, wraps around the ball portion 20 of the first bonding wire 12 a and fills the recess 19. So that it is solidified. The adhesive 15 solidified in the recess 19 serves to support the second semiconductor chip 11 when the second bonding wire 16b is bonded to the second electrode pad 12b.

この様に、凹部１９を設けることによって、第１の半導体チップ１１へのワイヤボンディングを可能にし、且つ第１のボンディングワイヤ１６ａが第２の半導体チップ１１の裏面と接触することを回避している。更に、第１のボンディングワイヤ１６ａを凹部１９を通過させることによって、半導体装置全体の高さ（図１：ｔ３）を薄くすることができる。   Thus, by providing the recess 19, wire bonding to the first semiconductor chip 11 is possible, and the first bonding wire 16a is prevented from coming into contact with the back surface of the second semiconductor chip 11. . Further, by passing the first bonding wire 16a through the recess 19, the height of the entire semiconductor device (FIG. 1: t3) can be reduced.

本実施の形態では、アイランド１３の板厚が１５０〜２００μであり、第１と第２の半導体チップ１０、１１の厚みがバックグラインド工程により２５０〜３００μとなっている、接着剤１４、１５の厚みとして２０〜３０μ必要であり、更にはボンディングワイヤの上部に樹脂の残り厚みとして１５０〜２００μは必要である。本願出願人は、これらの厚みを収納しつつ、パッケージの高さｔ３を１．０ｍｍ以下にまで薄形化した半導体装置を実現した。   In the present embodiment, the thickness of the island 13 is 150 to 200 μm, and the thickness of the first and second semiconductor chips 10 and 11 is 250 to 300 μm by the back grinding process. The thickness needs to be 20-30 μm, and further, the remaining thickness of the resin needs to be 150-200 μm above the bonding wire. The applicant of the present application has realized a semiconductor device in which the thickness t3 of the package is reduced to 1.0 mm or less while accommodating these thicknesses.

図３は、凹部１９の形成するときの製造ステップを示す図である。第１主面３０と第２主面３１とを具備する半導体ウェハ３２を準備し、その第１主面３０に前工程によって各種回路素子を形成し、第２主面３１を研磨してウェハ３２の厚みを所定の値に減じる。そして、図３（Ａ）に示したように、第２主面３１側からダイシングラインを認識し、幅広（約１．０ｍｍ）の第１のダイシングブレード３３によって、全体のウェハ厚み２８０μに対して１３０μの深さの溝３４を形成する。ダイシングブレード３３の中心線はダイシングラインの中心線に一致する。次いで、図３（Ｂ）に示したように、ダイシングラインに沿って幅狭（約４０μｍ）の第２のダイシングブレード３５によってウェハ３２を完全に切断する。尚、ハーフダイシングによる溝３４は、凹部１９を設ける箇所だけでも良いし、半導体チップ１０、１１の４辺全てに凹部１９を形成するように設けても良い。また、第２のダイシングブレード３５は第１主面３０側から切削する形態でも良いし、第２主面３１側から切削する形態でも良い。   FIG. 3 is a diagram showing manufacturing steps when the recess 19 is formed. A semiconductor wafer 32 having a first main surface 30 and a second main surface 31 is prepared, various circuit elements are formed on the first main surface 30 by a pre-process, and the second main surface 31 is polished to obtain a wafer 32. Is reduced to a predetermined value. Then, as shown in FIG. 3A, the dicing line is recognized from the second main surface 31 side, and a wide (about 1.0 mm) first dicing blade 33 is used for the entire wafer thickness of 280 μm. A groove 34 having a depth of 130 μ is formed. The center line of the dicing blade 33 coincides with the center line of the dicing line. Next, as shown in FIG. 3B, the wafer 32 is completely cut by the second dicing blade 35 having a narrow width (about 40 μm) along the dicing line. Note that the groove 34 by half dicing may be provided only at a location where the recess 19 is provided, or may be provided so that the recess 19 is formed on all four sides of the semiconductor chips 10 and 11. Further, the second dicing blade 35 may be cut from the first main surface 30 side or may be cut from the second main surface 31 side.

図４に第２の実施の形態を示した。リードフレームに代えてテープキャリアと半田ボールを用いた例である。第１の半導体チップ１０がポリイミド系のベースフィルム４０の上に接着固定され、第１の半導体チップ１０の上に第２の半導体チップ１１が固着される。ベースフィルム４０の表面にはリード端子１７に相当する導電パターン４１が形成されており、第１と第２の電極パッド１２ａ、１２ｂと導電パターン４１とが各々第１と第２のボンディングワイヤ１６ａ、１６ｂで接続されている。ベースフィルム４０には貫通穴が形成され、該貫通穴を介して、ベースフィルム４０の裏面に形成した半田ボール４２と接続されている、そして、周囲を熱硬化性の樹脂のでモールドされている。   FIG. 4 shows a second embodiment. In this example, a tape carrier and solder balls are used instead of the lead frame. The first semiconductor chip 10 is bonded and fixed onto the polyimide base film 40, and the second semiconductor chip 11 is fixed onto the first semiconductor chip 10. A conductive pattern 41 corresponding to the lead terminal 17 is formed on the surface of the base film 40, and the first and second electrode pads 12a, 12b and the conductive pattern 41 are respectively connected to the first and second bonding wires 16a, 16b. A through hole is formed in the base film 40, connected to a solder ball 42 formed on the back surface of the base film 40 through the through hole, and the periphery is molded with a thermosetting resin.

尚、上記実施例は半導体チップが２個の場合を記載したが、３個、４個を積層する場合でも同様に実施できることは言うまでもない。また、凹部１９を設ける手法として第２の半導体チップ１１の裏面側をハーフダイシングする例を示したが、例えば、第１と第２の半導体チップ１０、１１の間に絶縁スペーサを挟み、該絶縁スペーサの厚みによって第１の電極１２ａの上部に空間を形成するような形態でも良い。   In the above embodiment, the case where there are two semiconductor chips is described, but it goes without saying that the present invention can be similarly implemented even when three or four semiconductor chips are stacked. In addition, an example in which the back surface side of the second semiconductor chip 11 is half-diced as a method of providing the recess 19 has been shown. However, for example, an insulating spacer is sandwiched between the first and second semiconductor chips 10 and 11 and the insulation is performed. A configuration may be employed in which a space is formed above the first electrode 12a depending on the thickness of the spacer.

本発明を説明するための断面図である。It is sectional drawing for demonstrating this invention. 本発明を説明するための（Ａ）断面図、（Ｂ）平面図である。It is (A) sectional drawing and (B) top view for demonstrating this invention. 凹部１９の製造方法を示す断面図である。FIG. 11 is a cross-sectional view showing a method for manufacturing the recess 19. 本発明の、第２の実施の形態を示す断面図である。It is sectional drawing which shows the 2nd Embodiment of this invention. 従来例を説明するための断面図である。It is sectional drawing for demonstrating a prior art example.

符号の説明Explanation of symbols

１０ 第１の半導体チップ
１１ 第２の半導体チップ
４０ ベースフィルム
４１ 導電パターン
４２ 半田ボール DESCRIPTION OF SYMBOLS 10 1st semiconductor chip 11 2nd semiconductor chip 40 Base film 41 Conductive pattern 42 Solder ball

Claims (2)

樹脂フィルムと、前記樹脂フィルム上に形成されたリード端子に相当する導電パターンと、前記導電パターンに電気的に接続され、前記樹脂フィルムに接着固定された第１の半導体チップと、前記第１の半導体チップ上に積層固定された第２の半導体チップと、 前記導電パターンの裏面に相当する前記樹脂フィルムに設けられた貫通穴と、前記樹脂フィルムの表面、前記導電パターン、前記第１の半導体チップおよび前記第２の半導体チップを封止する封止樹脂とを有し、
一方の半導体チップのＩ／Ｏ端子と他方の半導体チップのアドレス端子は、前記導電パターンに共用して接続され、イネーブル信号の印加によりどちらかの半導体チップを排他的に選択する事を特徴とした半導体装置。 A resin film; a conductive pattern corresponding to a lead terminal formed on the resin film; a first semiconductor chip electrically connected to the conductive pattern and adhesively fixed to the resin film; A second semiconductor chip laminated and fixed on the semiconductor chip; a through-hole provided in the resin film corresponding to the back surface of the conductive pattern; a surface of the resin film; the conductive pattern; the first semiconductor chip. And a sealing resin for sealing the second semiconductor chip,
The I / O terminal of one semiconductor chip and the address terminal of the other semiconductor chip are connected in common to the conductive pattern, and one of the semiconductor chips is exclusively selected by applying an enable signal. Semiconductor device. 第１の半導体チップ及び前記第１の半導体チップ上に積層された第２の半導体チップと、前記第１及び第２の半導体チップの各第１主面に形成された第１及び第２の電極と、前記第１の電極上方と前記第２の半導体チップの第２主面との間に設けられる空間部と、前記第１の電極と一方が接続され前記空間を通過して延在される第１のボンディングワイヤーと、前記第２の電極と一方が接続されて延在される第２のボンディングワイヤーと、前記第１のボンディングワイヤーの他方および前記第２のボンディングワイヤーの他方が接続される外部接続用の電極手段とを有する半導体装置の製造方法であり、
所定の固着部に前記第１の半導体チップを固着した後、
前記第１の電極と一方を接続し、前記第１のボンディングワイヤーは、前記空間部を通過して横方向に導出され、前記第２の半導体チップの端より上昇する奇跡を描きながら前記第１のボンディングワイヤーの他方を前記電極手段に接続し、
前記第１のボンディングワイヤが、前記空間部に収まるように、前記第１の半導体チップ上に前記第２の半導体チップを固着し、
前記第２の電極と前記電極手段とを第２のボンディングワイヤで接続することを特徴とした半導体装置の製造方法。
The first semiconductor chip, the second semiconductor chip stacked on the first semiconductor chip, and the first and second electrodes formed on the first main surfaces of the first and second semiconductor chips And a space provided between the first electrode and the second main surface of the second semiconductor chip, and one of the first electrode is connected and extends through the space. A first bonding wire, a second bonding wire that is connected to one of the second electrodes and extends, and the other of the first bonding wire and the other of the second bonding wire are connected. A method of manufacturing a semiconductor device having electrode means for external connection,
After fixing the first semiconductor chip to a predetermined fixing portion,
One of the first electrodes is connected to the first electrode, and the first bonding wire passes through the space portion and is led out in a lateral direction, and draws a miracle rising from an end of the second semiconductor chip. Connecting the other bonding wire to the electrode means,
Fixing the second semiconductor chip on the first semiconductor chip so that the first bonding wire fits in the space;
A method of manufacturing a semiconductor device, wherein the second electrode and the electrode means are connected by a second bonding wire.
JP2005067089A 2005-03-10 2005-03-10 Semiconductor device and manufacturing method thereof Pending JP2005167286A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005039478A1 (en) * 2005-08-18 2007-02-22 Infineon Technologies Ag Power semiconductor device with semiconductor chip stack and method for producing the same
JP2018026982A (en) * 2016-08-12 2018-02-15 ミツミ電機株式会社 Battery protection device
JP2019033266A (en) * 2012-09-17 2019-02-28 コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス Cap for groove-attached and chip-attached device, cap-equipped device, assembly of device and wiring element, and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005039478A1 (en) * 2005-08-18 2007-02-22 Infineon Technologies Ag Power semiconductor device with semiconductor chip stack and method for producing the same
DE102005039478B4 (en) * 2005-08-18 2007-05-24 Infineon Technologies Ag Power semiconductor device with semiconductor chip stack and method for producing the same
US7898080B2 (en) 2005-08-18 2011-03-01 Infineon Technologies Ag Power semiconductor device comprising a semiconductor chip stack and method for producing the same
JP2019033266A (en) * 2012-09-17 2019-02-28 コミッサリア ア レネルジー アトミーク エ オ エナジーズ アルタナティブス Cap for groove-attached and chip-attached device, cap-equipped device, assembly of device and wiring element, and manufacturing method thereof
JP2018026982A (en) * 2016-08-12 2018-02-15 ミツミ電機株式会社 Battery protection device
TWI770043B (en) * 2016-08-12 2022-07-11 日商三美電機股份有限公司 Battery protection device

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