JP2005142284A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To thin a semiconductor device in a QFN (Quad Flat Non leaded package) form, and to improve reliability. <P>SOLUTION: The semiconductor device 1 has sealing resin sections 2 and semiconductor chips 3 sealed by the sealing resin sections 2. The device 1 further has a plurality of leads 4 and a plurality of bonding wires 6 being sealed by the sealing resin sections 2 and electrically connecting a plurality of the leads 4 and a plurality of electrodes 3a on the surfaces of the chips 3. The chips 3 are joined with the undersides of the inner lead sections 4g of the lead 4 through insulating junction materials 7. The back sides 3c of the chips 3 and the lower exposed surfaces 4e of each lead 4 are exposed on the back sides 2b of the sealing resin sections 2. The upper exposed surfaces 4d of each lead 4 are exposed on the surfaces 2a of the sealing resin sections 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device in the form of a semiconductor package.

  A semiconductor chip is mounted on the die pad part (tab) of the lead frame, the lead part of the lead frame and the electrode on the surface of the semiconductor chip are wire-bonded, and then sealed with resin, cut into individual pieces, and QFN (Quad Flat non leaded package) type semiconductor device is manufactured. On the mounting surface of the QFN type semiconductor device, a part of the lead portion of the lead frame is exposed from the sealing resin as an external terminal.

  Japanese Patent Application Laid-Open No. 10-270628 discloses a technology relating to a semiconductor device in which an outer lead portion of a lead frame on which a semiconductor chip is mounted is formed thicker than other portions, and an outer surface of the outer lead portion is exposed from a side surface of a mold resin. Is described (see Patent Document 1).

In Japanese Patent Laid-Open No. 9-92775, a lead frame is formed to have substantially the same size as a semiconductor chip, and a coining portion is formed by reducing the thickness by coining the surface of the inner lead of the lead frame. The frame and the semiconductor chip are attached with their end faces aligned, the inner lead coining part and the semiconductor chip bonding pad are connected by a bonding wire, the mold resin is sealed on the surface of the semiconductor chip, and the outer lead is on the sealing resin surface. A technique relating to a semiconductor device in which only the surface of the semiconductor device is exposed is described (see Patent Document 2).
JP-A-10-270628 JP-A-9-92775

  According to the study of the present inventor, the following has been found.

  By exposing the lead portions on both the front and back surfaces of the sealing resin of the QFN type semiconductor device and providing external terminals on both the front and back surfaces, a plurality of semiconductor devices can be used in a stacked manner. . In such a stacked semiconductor device, if the thickness of each semiconductor device is large, the thickness of the entire stacked structure when a plurality of semiconductor devices are stacked is considerably increased, and the electronic device having such a stacked structure is small. Making it difficult to make it thinner and thinner. For this reason, in a stacked semiconductor device, it is desired to make each semiconductor device as thin as possible. In addition, when a plurality of semiconductor devices are stacked, heat is easily trapped in the stacked semiconductor devices, and the reliability of the semiconductor device is likely to be reduced. For example, when moisture accumulates at the interface between the sealing resin and the semiconductor chip, the sealing resin is easily peeled off.

  An object of the present invention is to provide a technique that enables a semiconductor device to be thinned.

  Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention provides a plurality of lead portions, a semiconductor chip joined to the plurality of lead portions, a plurality of wires that electrically connect the plurality of lead portions and the plurality of electrodes of the semiconductor chip, and seals them. Each lead portion is exposed on the first surface of the sealing resin portion, and each lead portion and the semiconductor chip are on the second surface opposite to the first surface of the sealing resin portion. Exposed.

  Further, the present invention provides a plurality of lead portions, a semiconductor chip bonded to the plurality of lead portions, a plurality of wires that electrically connect the plurality of lead portions and the plurality of electrodes of the semiconductor chip, and seals them. Each lead portion is exposed on the first surface of the sealing resin portion, and each lead portion and the semiconductor chip on the second surface opposite to the first surface of the sealing resin portion. And a plurality of these semiconductor packages are stacked, and the exposed surface of each lead of the upper semiconductor package and the exposed surface of each lead of the lower semiconductor package are electrically connected to each other. It is connected.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A plurality of lead portions, a semiconductor chip bonded to the plurality of lead portions, a plurality of wires for electrically connecting the plurality of lead portions and the plurality of electrodes of the semiconductor chip, and a sealing resin portion for sealing them The lead portions are exposed on the first surface of the sealing resin portion, and the lead portions and the semiconductor chip are exposed on the second surface opposite to the first surface of the sealing resin portion. Thus, the semiconductor device can be thinned. In addition, the reliability of the semiconductor device can be improved.

  In addition, a plurality of lead portions, a semiconductor chip bonded to the plurality of lead portions, a plurality of wires that electrically connect the plurality of lead portions and the plurality of electrodes of the semiconductor chip, and sealing for sealing them Each lead portion is exposed on the first surface of the sealing resin portion, and each lead portion and the semiconductor chip are exposed on the second surface opposite to the first surface of the sealing resin portion. The plurality of semiconductor packages are stacked, and the exposed surface of each lead of the upper semiconductor package is electrically connected to the exposed surface of each lead of the lower semiconductor package. Thus, the semiconductor device can be thinned. In addition, the reliability of the semiconductor device can be improved.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections. However, unless otherwise specified, they are not irrelevant to each other, and one is a part of the other or All the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  The semiconductor device of the present embodiment will be described with reference to the drawings.

  1 is a plan view (top view) of a semiconductor device 1 according to an embodiment of the present invention, FIG. 2 is a bottom view (back view), FIG. 3 is a plan view (top view) thereof, and FIG. Is a cross-sectional view thereof. FIG. 3 corresponds to a plan view (upper surface) when the sealing resin portion 2 is seen through. 1 to 3 substantially corresponds to FIG.

  A semiconductor device (semiconductor package) 1 according to the present embodiment is a resin-encapsulated, surface-mounted semiconductor package, for example, a QFN (Quad Flat Non leaded package) semiconductor device.

  1 to 4 includes a sealing resin portion (sealing portion) 2, a semiconductor chip (semiconductor element) 3 sealed by the sealing resin portion 2, and a conductor. Electrically connecting a plurality of leads (lead portions) 4 formed by the above, a plurality of leads 4 sealed by the sealing resin portion 2 and a plurality of electrodes (bonding pads, pad electrodes) 3a on the surface of the semiconductor chip 3 And a plurality of bonding wires 6 to be connected.

  The sealing resin portion 2 is made of, for example, a resin material such as a thermosetting resin material, and can include a filler. For example, the sealing resin portion 2 can be formed using an epoxy resin containing a filler. The semiconductor chip 3, the lead 4 and the bonding wire 6 are sealed and protected by the sealing resin portion 2.

  For example, the semiconductor chip 3 is formed by forming various semiconductor elements or semiconductor integrated circuits on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, and then grinding the back surface of the semiconductor substrate as necessary, followed by dicing or the like. The semiconductor substrate is separated into each semiconductor chip 3. For example, a semiconductor chip (SRAM chip) in which an SRAM (Static Random Access Memory) circuit is formed can be used as the semiconductor chip 3.

  A plurality of electrodes 3 a are formed on the surface (main surface on the semiconductor element formation side) 3 b of the semiconductor chip 3. The electrode 3a is electrically connected to a semiconductor element or a semiconductor integrated circuit formed on the semiconductor chip 3. One end of a bonding wire 6 made of a fine metal wire such as a gold (Au) wire is connected to each electrode 3 a on the surface 3 b of the semiconductor chip 3, and the other end of the bonding wire 6 is connected to the lead 4. Therefore, each electrode 3 a on the surface 3 b of the semiconductor chip 3 is electrically connected to each lead 4 via the bonding wire 6.

  The plurality of leads 4 are arranged around the semiconductor chip 3, and a part (tip portion) thereof is located (extended) on the surface 3 b of the semiconductor chip 3. The lead 4 has both functions of an inner lead embedded in the sealing resin portion 2 and an outer lead exposed on the front surface 2a or the back surface 2b of the sealing resin portion 2. That is, the upper surface 4b of the region in the vicinity of the end portion (tip portion) 4a on the side (extended) of the lead 4 that is sealed by the sealing resin portion 2 and functions as a bonding portion of the lead 4 on the semiconductor chip 3 ( That is, the bonding wire 6 is connected (bonded) to the upper surface 4b) of the inner lead portion 4g, and the upper portion that is an exposed portion of the upper surface of the lead 4 that can function as an external connection terminal portion on the surface 2a of the sealing resin portion 2. An exposed surface (upper connection surface) 4d is exposed, and a lower exposed surface (lower connection surface) 4e that is an exposed portion of the lower surface of the lead 4 that can function as an external connection terminal portion is formed on the back surface 2b of the sealing resin portion 2. Exposed. In a region where the bonding wire 6 of the lead 4 is connected, a plating layer (for example, a silver plating layer) can be formed to facilitate the connection of the bonding wire 6. The upper exposed surface 4d and the lower exposed surface 4e of the lead 4 have a substantially rectangular shape or a substantially square shape.

  As described above, the lead 4 extends to the semiconductor chip 3, and a part of each lead 4 is located on the semiconductor chip 3. For this reason, the semiconductor chip 3 and the lead 4 are planarly overlapped. The surface 3b of the semiconductor chip 3 is bonded to the lower surface 4c of the region in the vicinity of the end 4a on the side of the lead 4 extending on the semiconductor chip 3 (that is, to the lower surface 4c of the tip of the inner lead 4g of the lead 4). Are joined or glued through. Therefore, the semiconductor chip 3 is suspended from the lower surface 4c in the vicinity of the end 4a of the lead 4 (that is, the lower surface 4c of the tip of the inner lead 4g of the lead 4) so that the surface 3b of the semiconductor chip 3 faces upward. The tab (die pad) as a chip mounting portion for mounting the semiconductor chip 3 is not formed. A back surface 3 c of the semiconductor chip 3 (a main surface opposite to the front surface 3 b which is the main surface on the semiconductor element forming side) 3 c is exposed from the sealing resin portion 2. That is, the back surface 3 c of the semiconductor chip 3 is exposed at the back surface 2 b of the sealing resin portion 2. Further, as the bonding material 7, for example, an insulating bonding material such as an insulating tape made of polyimide or an insulating paste can be used. By using an insulating bonding material as the bonding material 7, a short circuit between the semiconductor chip 3 and the lead 4 can be prevented, and the reliability of the semiconductor device can be further improved. Further, the space between the adjacent leads 4 is filled with the material constituting the sealing resin portion 2 so as not to contact each other.

  The electrode 3a of the semiconductor chip 3 is disposed in an inner region or a region relatively close to the center of the surface 3b. The end 4a of the lead 4 extends on the surface 3b of the semiconductor chip 3. For example, the end 4a of the lead 4 can be disposed relatively close to the electrode 3a. Can be made relatively short, and noise due to the inductance component of the bonding wire 6 can be reduced.

  As an end of the lead 4 on the side opposite to the end 4 a extending on the semiconductor chip 3, a cut surface (side surface, end surface) 4 f of the lead 4 is a cut surface (side surface) 2 c of the sealing resin portion 2. Exposed. The cut surface 4f of the lead 4 and the cut surface 2c of the sealing resin portion 2 are side surfaces (end surfaces) generated by a cutting process when manufacturing a semiconductor device.

  Further, as can be seen from FIG. 4 and the like, the lead 4 is located on the semiconductor chip 3 and in the vicinity of the end opposite to the side bonded to the semiconductor chip 3 (the upper exposed surface 4d and the lower exposed surface). In the region corresponding to 4e, the thickness is relatively thick, and in other regions, the upper surface side and the lower surface side of the lead 4 are half-etched, etc. so that the thickness is relatively thin. . For this reason, when the sealing resin portion 2 is formed, the upper exposed surface 4d of the lead 4 having a relatively large thickness is exposed on the surface 2a of the sealing resin portion 2, and the back surface 2b of the sealing resin portion 2 is formed. Then, the lower exposed surface 4e of the relatively thick lead 4 is exposed, and the inner lead portion 4g, which is a relatively thin region other than the upper exposed surface 4d and the lower exposed surface 4e, is sealed. Sealed in the resin part 2. Such processing can also be performed by a mold (press, coining, etc.). Further, the upper exposed surface 4d of the lead 4 can be substantially flush with the surface 2a of the sealing resin portion 2, and the lower exposed surface 4e of the lead 4 can be substantially flush with the back surface 2b of the sealing resin portion 2. The lower exposed surface 4 e of the lead 4 can be slightly protruded from the back surface 2 b of the sealing resin portion 2.

  Of the leads 4, a lead 14 a that can function as a Vcc terminal (a power supply potential terminal fixed at a power supply potential) has a Vcc bus bar (at the end opposite to the cut surface 4 f) at the tip (a side opposite to the cut surface 4 f). A lead 14b that is connected to or integrated with a bus bar lead) 15a and can function as a Vss terminal (a reference potential terminal that is fixed at a reference potential) has a leading end (an end opposite to the cut surface 4f). Are connected to or integrated with a bus bar (bus bar lead) 15b for Vss. The Vcc bus bar 15 a extends on the surface 3 b of the semiconductor chip 3 along the arrangement direction of the electrodes 3 a, and is between the end 4 a of the other lead 4 on the lead 14 a side and the electrode 3 a of the semiconductor chip 3. Has been placed. The Vss bus bar 15 b extends on the surface 3 b of the semiconductor chip 3 along the arrangement direction of the electrodes 3 a, and is between the end 4 a of the other lead 4 on the lead 14 b side and the electrode 3 a of the semiconductor chip 3. Has been placed. The bus bars 15 a and 15 b are electrically connected to the electrode 3 a of the semiconductor chip 3 through the bonding wires 6. Further, the bonding wire 6 connected to the lead 4 not connected to the bus bars 15a and 15b (that is, the lead 4 other than the leads 14a and 14b) is connected to the electrode 3a of the semiconductor chip 3 so as to exceed the bus bars 15a and 15b. can do. The surface 3b of the semiconductor chip 3 includes a lower surface 4c in the vicinity of the end 4a on the side of the lead 4 extending on the semiconductor chip 3 (that is, a lower surface 4c at the tip of the inner lead portion 4g of the lead 4), bus bars 15a, It is bonded or bonded to the lower surface of 15b via a bonding material 7. Therefore, the semiconductor chip 3 is suspended from the vicinity of the end 4a of the lead 4 (the end of the inner lead 4g) and the bus bars 15a and 15b so that the surface 3b of the semiconductor chip 3 faces upward. It has become.

  As described above, the upper exposed surface 4d and the lower exposed surface 4e of each lead 4 are exposed at the front surface 2a and the back surface 2b of the sealing resin portion 2 to constitute the external terminal (external connection terminal) of the semiconductor device 1. The front surface 2 a or the back surface 2 a of the sealing resin portion 2 (that is, the front surface or the back surface of the semiconductor device 1) is the mounting surface of the semiconductor device 1. In addition, a plating (solder plating) layer is formed on the upper exposed surface 4d and the lower exposed surface 4e of the lead 4 exposed on the front surface 2a and the back surface 2a of the sealing resin portion 2, but for the sake of easy understanding. In addition, illustration of the plating layer is omitted. Since the plating layer is formed on the upper exposed surface 4d and the lower exposed surface 4e of the lead 4, when the semiconductor device 1 is mounted on a substrate (external substrate, motherboard) or the like, a terminal or a conductor pattern on the substrate The reliability of the electrical connection between the terminals of the semiconductor device 1 (the upper exposed surface 4d or the lower exposed surface 4e of the lead 4) can be improved.

  FIG. 5 is a cross-sectional view showing a state where the semiconductor device 1 as described above is mounted on the substrate 21. 5 is a cross-sectional view corresponding to FIG.

  As shown in FIG. 5, when the semiconductor device 1 is mounted on a substrate (external substrate, motherboard) 21, the conductor pattern (terminal, conductor portion) 22 formed on the substrate 21 is connected to the outside of the semiconductor device 1. The lower exposed surface 4e of the lead 4 as a terminal is joined and electrically connected via a conductive joining material 23 made of solder or the like. In FIG. 5, the lower exposed surface 4 e of the lead 4 functions as an external terminal of the semiconductor device 1.

  In the semiconductor device 1 of the present embodiment, the upper exposed surface 4d of the lead 4 is exposed at the surface 2a of the sealing resin portion 2 (that is, the surface of the semiconductor device 1), and the upper exposed surface 4d of the lead 4 is also a semiconductor. It can function as an external terminal of the device 1. Therefore, another semiconductor device can be mounted (stacked) on the semiconductor device 1 and its external terminals can be electrically connected to the upper exposed surface 4 d of the lead 4 of the semiconductor device 1.

  FIG. 6 is a cross-sectional view showing a state in which a plurality of semiconductor devices (semiconductor packages) 1 as described above are prepared and stacked or stacked on the substrate 21. 6 is a cross-sectional view corresponding to FIG.

  In FIG. 6, a plurality of semiconductor devices 1 (in FIG. 6, semiconductor devices 1a, 1b, and 1c) are stacked and mounted on a substrate (external substrate, motherboard) 21. Each of the semiconductor devices 1a, 1b, and 1c has substantially the same configuration as the semiconductor device 1 of FIGS.

  As shown in FIG. 6, the lower exposed surface 4e of the lead 4 of the semiconductor device 1a has a conductive bonding material 23 made of solder or the like on a conductor pattern (terminal, conductor portion) 22 formed on the substrate 21. And are electrically connected. The semiconductor device 1b is mounted on the semiconductor device 1a, and the lower exposed surface 4e of the lead 4 of the upper (upper side) semiconductor device 1b is exposed on the upper surface of the lower (lower side) semiconductor device 1a. The lead 4 is joined and electrically connected to the upper exposed surface 4d via a conductive joining material (not shown) made of solder or the like. The semiconductor device 1c is mounted on the semiconductor device 1b, and the lower exposed surface 4e of the lead 4 of the upper (upper side) semiconductor device 1c is exposed on the upper surface of the lower (lower side) semiconductor device 1b. The lead 4 is joined and electrically connected to the upper exposed surface 4d via a conductive joining material (not shown) made of solder or the like. That is, a plurality of semiconductor devices 1 are stacked (stacked), and the lower exposed surface 4e of the lead 4 of the upper (upper side) semiconductor device 1 is used as the upper exposed surface 4d of the lead 4 of the lower (lower side) semiconductor device 1. Further, they are connected (bonded) via a conductive bonding material made of solder or the like. Between the semiconductor device 1a and the semiconductor device 1b and between the semiconductor device 1b and the semiconductor device 1c, a solder plating layer (not shown) provided on the upper exposed surface 4d and the lower exposed surface 4e of the lead 4 is reflowed. Can be connected (joined). In this way, the lead 4 of the semiconductor device 1a, the lead 4 of the semiconductor device 1b, and the lead 4 of the semiconductor device 1c are electrically connected. In FIG. 6, three semiconductor devices 1, that is, semiconductor devices 1a, 1b, and 1c are stacked. However, the number of stacked semiconductor devices 1 is not limited to three and can be changed as appropriate. Yes, two or more arbitrary numbers of semiconductor devices 1 can be stacked. Further, as shown in FIG. 5, the semiconductor device 1 can be used alone and mounted on the substrate 21 without being stacked.

  The semiconductor device 1 of the present embodiment has external terminals (external connection terminals) on both the upper surface and the lower surface, here, an upper exposed surface 4d and a lower exposed surface 4e, so that as shown in FIG. Thus, it becomes possible to easily stack a plurality of semiconductor devices 1.

  Further, the upper exposed surface 4d of the lead 4 can be substantially flush with the surface 2a of the sealing resin portion 2, and the lower exposed surface 4e of the lead 4 can be substantially flush with the back surface 2b of the sealing resin portion 2. The lower exposed surface 4 e of the lead 4 can be slightly protruded from the back surface 2 b of the sealing resin portion 2. By slightly projecting the lower exposed surface 4e of the lead 4 from the back surface 2b of the sealing resin portion 2, when a plurality of semiconductor devices 1 are stacked as shown in FIG. 6, the leads 4 of the upper semiconductor device 1 The lower exposed surface 4e can be more reliably connected to the upper exposed surface 4d of the lead 4 of the lower semiconductor device 1. Thereby, the reliability of the electrical connection when the semiconductor device is mounted can be further improved.

  In the semiconductor device 1 according to the present embodiment, as described above, the semiconductor chip 3 has a region in the vicinity of the end 4a of the lead 4 (the tip of the inner lead 4g and the inner lead 4g so that the surface 3b of the semiconductor chip 3 faces upward). It has a structure suspended from the bus bars 15a and 15b), and a tab (die pad) as a chip mounting portion on which the semiconductor chip 3 is mounted is not formed. The back surface 3 c of the semiconductor chip 3 is exposed from the sealing resin portion 2. That is, the back surface 3 c of the semiconductor chip 3 is exposed at the back surface 2 b of the sealing resin portion 2. Since the tab for mounting the semiconductor chip 3 is not provided and the material of the sealing resin portion 2 does not exist on the back surface 3c of the semiconductor chip 3, the thickness of the sealing resin portion 2 can be reduced, and the semiconductor device The thickness of 1 can be reduced. For this reason, the semiconductor device 1 can be thinned.

  In particular, as shown in FIG. 6, when a plurality of semiconductor devices (semiconductor packages) 1 are stacked (stacked) on a substrate 21, if the thickness of each semiconductor device 1 is large, the overall thickness becomes considerably thick. This is disadvantageous for downsizing and thinning of electronic equipment (semiconductor device) having such stacked semiconductor devices (semiconductor packages). For this reason, in the (stacked type) semiconductor device (semiconductor package) 1 that can be used in a stacked state, it is desired to make each semiconductor device 1 as thin as possible. In the present embodiment, the back surface 3c of the semiconductor chip 3 is exposed at the back surface 2b of the sealing resin part 2, and the tab and the material of the sealing resin part 2 do not exist on the back surface 3c of the semiconductor chip 3. The thickness of the semiconductor device 1 can be reduced. For this reason, as shown in FIG. 6, when a plurality of semiconductor devices (semiconductor packages) 1 are stacked, the entire thickness can be reduced. Therefore, it is possible to reduce the size or thickness of electronic devices (semiconductor devices) including a stack of a plurality of semiconductor devices (semiconductor packages) 1.

  Further, according to the study by the present inventor, unlike the present embodiment, the back surface 3c of the semiconductor chip 3 is completely sealed in the sealing resin portion 2 without being exposed (that is, the semiconductor chip 3). It was found that moisture easily collects at the interface between the sealing resin portion 2 and the semiconductor chip 3. If moisture accumulates at the interface between the sealing resin portion 2 and the semiconductor chip 3, the sealing resin portion 2 is likely to be peeled off, which may reduce the reliability of the semiconductor device. Such a defect is likely to occur due to heat generated when a semiconductor device (semiconductor package) is mounted on a substrate or the like. In particular, when a plurality of semiconductor devices (semiconductor packages) are stacked as shown in FIG. 6, heat easily accumulates in the stacked semiconductor devices (semiconductor packages), and the interface between the sealing resin portion 2 and the semiconductor chip 3. Adverse effects caused by moisture accumulation are likely to increase.

  In the present embodiment, the back surface 3 c of the semiconductor chip 3 is exposed from the sealing resin portion 2. For this reason, moisture hardly collects at the interface between the sealing resin portion 2 and the semiconductor chip 3. Therefore, it is possible to suppress or prevent the peeling of the sealing resin portion 2 from occurring. For this reason, even if heat is generated when the semiconductor device 1 is mounted on a substrate or the like and used, problems caused by accumulation of moisture at the interface between the sealing resin portion 2 and the semiconductor chip 3 can be prevented. In particular, when a plurality of semiconductor devices 1 are stacked as shown in FIG. 6, heat is easily trapped in the stacked semiconductor devices 1, and moisture accumulates at the interface between the sealing resin portion 2 and the semiconductor chip 3. However, each semiconductor device 1 (semiconductor devices 1a, 1b, 1c in FIG. 6) is formed on the back surface 2b of the sealing resin portion 2 on the semiconductor chip 3. Since the back surface 3c is exposed, moisture does not accumulate at the interface between the sealing resin portion 2 and the semiconductor chip 3, and it is possible to suppress or prevent the occurrence of problems such as peeling of the sealing resin portion 2. Therefore, even if a plurality of semiconductor devices 1 are stacked (stacked), no problem occurs, and the reliability of the stacked semiconductor device can be improved.

  When a plurality of semiconductor devices 1 are stacked, the connection (connection relationship) of the bonding wires 6 in each semiconductor device 1 can be changed by a bonding option.

  7 and 8 are conceptual plan views (planar perspective views) for explaining the connection relationship of the bonding wires 6 when two semiconductor devices 1 are stacked. 7 and 8 show a state in which the sealing resin portion 2 is seen through. 7 shows the connection relationship of the bonding wires 6 of the lower (lower) semiconductor device 1d when two semiconductor devices 1d and 1e are stacked, and FIG. 8 shows the connection of the upper (upper) semiconductor device 1e. Showing the relationship. 7 and 8, for example, a semiconductor chip (DRAM chip) in which a DRAM (Dynamic Random Access Memory) circuit is formed is used as the semiconductor chip 3. Further, the semiconductor devices 1d and 1e can have substantially the same configuration as the semiconductor device 1 except for the connection relationship between the lead 4 and the electrode 3a of the semiconductor chip 3 (connection relationship of the bonding wire 6). Then, the explanation is omitted.

  7 and 8, as the lead 4 of the semiconductor devices 1d and 1e, the lead 31 used for the Vcc terminal, the lead 32 used for the Vss terminal, the lead 33 used for the address pin (address input terminal), and the like. In addition, a lead 34 used for an I / O pin (data input / output terminal) or the like is provided, and a RAS for a lower PKG (package) is provided in both the lower semiconductor device 1d and the upper semiconductor device 1e. There are provided a lead 35a for CAS, a CAS lead 36a for the lower PKG, an RAS lead 35b for the upper PKG, and a CAS lead 36b for the upper PKG.

  In the lower-stage semiconductor device 1d, as shown in FIG. 7, the RAS and CAS electrodes 37 of the electrodes 3a of the semiconductor chip 3 and the RAS and CAS leads 35a for the lower PKG of the leads 4 are used. , 36a through a bonding wire 6a. In the upper-stage semiconductor device 1, as shown in FIG. 8, the RAS and CAS electrodes 37 of the electrodes 3a of the semiconductor chip 3 are used, and the RAS and CAS leads 35b for the upper PKG of the leads 4 are used. , 36b through a bonding wire 6a.

  When the semiconductor device 1e is stacked (mounted) on the semiconductor device 1d and the leads 4 of the semiconductor device 1d are electrically connected to the leads 4 of the semiconductor device 1e, the RAS and CAS leads for the lower PKG. The semiconductor chip 3 of the lower semiconductor device 1d can be selected by 35a and 36a, and the semiconductor chip 3 of the upper semiconductor device 1e can be selected by the RAS and CAS leads 35b and 36b for the upper PKG. .

  In a DRAM chip, the selected chip is usually controlled by RAS and CAS signal pins. When stacking semiconductor devices 1d and 1e in which DRAM chips are packaged in a semiconductor package, the number of RAS and CAS signal pins (RAS and CAS leads) in each of the semiconductor devices (semiconductor packages) 1d and 1e is increased, and bonding options are added. 7 and 8, the lower semiconductor device 1d and the upper semiconductor device 1e are separated and wire bonding (bonding wire 6 forming step) is performed, and test good products on a single unit basis are overlaid. By (stacking), it becomes possible to reduce a yield loss when a plurality of semiconductor devices 1 (here, two semiconductor devices 1d and 1e) are stacked.

  In addition, in the case of a three-stage stack in which three semiconductor devices 1 are stacked or a four-stage stack in which four semiconductor devices 1 are stacked, pins (RAS and SAS leads) for controlling a selected chip such as RAS and SAS are provided. By increasing that amount (by the increase in the number of stacked semiconductor devices) and using the wire bonding option, it is possible to switch signals appropriately.

  Next, the manufacturing process of the semiconductor device of this embodiment will be described. 9 to 15 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. 9 to 15 are sectional views corresponding to FIG.

  First, a lead frame 41 used for manufacturing the semiconductor device 1 of the present embodiment is prepared. The lead frame 41 is made of, for example, a conductor material such as copper, a copper alloy, or 42-alloy. Manufacturing or processing of the lead frame 41 is performed as follows.

  As shown in FIG. 9, a plate-like metal member (conductor member) 42 for forming the lead frame 41 is prepared. The metal member 42 is made of, for example, a conductor material such as copper, a copper alloy, or 42-alloy.

  Next, as shown in FIG. 10, the metal member 42 is processed to reduce the thickness within a range in which the outer shape of the semiconductor chip 3 to be mounted later can be accommodated, that is, a portion corresponding to the inner lead portion of the lead frame. Apply. This processing can be performed by half-etching the metal member 42 from the upper surface and the lower surface side. As another form, this processing can be performed by pressing or coining.

  Next, as shown in FIG. 11, the metal member 42 is patterned to form the individual leads 4 (including the inner lead portions 4g which are regions where the thickness is relatively thin) and the bus bars 15a and 15b. To do. This patterning can be performed by etching the metal member 42. In this way, the lead frame 41 can be formed. As another form, patterning of the metal member 42 can also be performed by pressing or coining.

  Next, as shown in FIG. 12, the bonding material 7 for bonding (adhering) the semiconductor chip 3 to the tip of the inner lead portion 4g of the lead 4 of the lead frame 41 and the bus bars 15a and 15b is disposed ( Glue, paste, apply). As the bonding material 7, for example, an insulating tape made of polyimide or the like, or an insulating bonding material such as an insulating paste can be used. The bonding material 7 is arranged on the surface of the lead frame 41 on the side on which the semiconductor chip 3 is mounted. Since the bonding wire 6 is connected later to the surface of the lead frame 41 opposite to the side where the bonding material 7 is disposed, in order to facilitate the wire bonding, before the bonding material 7 is disposed, It is more preferable to perform a plating treatment (for example, a silver plating treatment).

  Next, as shown in FIG. 13, the semiconductor chip 3 is lead through the bonding material 7 from the surface of the lead frame 41 on the semiconductor chip 3 mounting side (here, the lower surface 4 c side of the inner lead portion 4 g of the lead 4). 4 is bonded (adhered) to the tip of the inner lead portion 4g and the bus bars 15a and 15b, and fixed. At this time, the surface 3 b of the semiconductor chip 3 is bonded to the inner lead portion 4 g of the lead 4 and the lower surfaces of the bus bars 15 a and 15 b via the bonding material 7. The semiconductor chip 3 is formed by forming a semiconductor element (semiconductor integrated circuit) on a semiconductor substrate (semiconductor wafer) and then thinning the semiconductor substrate by grinding the back surface (back grind), and then dicing the semiconductor substrate to each semiconductor chip. If the one separated into three is used, the thickness of the semiconductor chip 3 can be reduced, and the thickness of the manufactured semiconductor device 1 can also be reduced, which is more preferable. When the semiconductor chip 3 is bonded to the inner lead portion 4g of the lead 4 and the bus bars 15a, 15b via the bonding material 7, the electrode (bonding pad) 3a provided on the surface 3b of the semiconductor chip 3 is 2 It is located between the bus bars 15a and 15b.

  Next, as shown in FIG. 14, a wire bonding step is performed to connect the plurality of electrodes 3 a of the semiconductor chip 3 and the upper surfaces 4 b of the inner lead portions 4 g of the plurality of leads 4 of the lead frame 41 to the plurality of bonding wires 6. Are electrically connected to each other. At the time of wire bonding, one end of the electrode 3a of the semiconductor chip 3 is connected to a plurality of decode signal pins (decode signal pin bonding pads) and a plurality of input / output pins (input / output pin bonding pads). The other ends of the plurality of bonding wires 6 are connected to the inner lead portions 4g of the individually independent leads 4 so as to cross the bus bars 15a and 15b. Further, among the electrodes 3a of the semiconductor chip 3, a plurality of bonding wires 6 whose one ends are connected to a plurality of Vcc pads (Vcc bonding pads) connect the other ends to a common bus bar 15a set for Vcc. Further, among the electrodes 3a of the semiconductor chip 3, the plurality of bonding wires 6 whose one ends are connected to a plurality of Vss pads (bonding pads for Vss) are connected to the other end to a common bus bar 15b set for Vss.

  Next, as shown in FIG. 15, a resin sealing (molding) process is performed to seal the semiconductor chip 3, the leads 4, the bus bars 15 a and 15 b, and the bonding wires 6 with the sealing resin portion 2. This resin sealing (molding) step can be performed by, for example, a transfer molding method. The sealing resin portion 2 is made of, for example, a resin material such as a thermosetting resin material, and can include a filler. For example, the sealing resin portion 2 can be formed using an epoxy resin containing a filler. Further, in the sealing resin step, the upper exposed surface 4d that is the upper surface of the outer lead portion of the lead 4 is exposed from the surface 2a of the sealing resin portion 2, and the lower surface of the outer lead portion of the lead 4 from the rear surface 2b of the sealing resin portion 2. The sealing resin portion 2 is formed so that the lower exposed surface 4e is exposed and the inner lead portion 4g is sealed. Further, when forming the sealing resin portion 2, the lower exposed surface 4 e of the lead 4 is made substantially flush with the back surface 2 b of the sealing resin portion 2, or the lower exposed surface 4 e of the lead 4 is It protrudes slightly from the back surface 2 b of the sealing resin portion 2.

  FIG. 16 and FIG. 17 are explanatory diagrams (main part plan views) of the resin sealing step (molding step) in the present embodiment. FIGS. 16 and 17 correspond to plan views showing the state immediately after the resin sealing step, but in order to simplify understanding, the mold region (region where the sealing resin is formed) 51 is hatched. The structure under the mold region 51 is seen through.

  As described above, in each semiconductor package region of the lead frame 41 (region where one semiconductor device 1 is manufactured) as shown in FIGS. 9 to 14, the inner lead portion 4g of the lead 4 and the bus bar 15a, After the semiconductor chip 3 is joined to 15b via the joining material 7, the electrode 3a of the semiconductor chip 3, the inner lead portion 4g of the lead 4 and the bus bars 15a and 15b are electrically connected via the bonding wire 6, As shown in FIG. 15, the sealing resin step (molding step) is performed to form the sealing resin portion 2. In this sealing resin step, as shown in FIG. 16, a mold region 51 is individually formed in each semiconductor package region (region from which one semiconductor device 1 is formed) of the lead frame 41 to form the sealing resin. The portion 2 can be formed, or as shown in FIG. 17, the mold region 51 is collectively formed in a plurality of semiconductor package regions (regions from which one semiconductor device 1 is formed) of the lead frame 41. The sealing resin portion 2 can also be formed by forming and later cutting into individual pieces. In FIG. 16 and FIG. 17, four semiconductor package regions are shown.

  As shown in FIG. 16, when each semiconductor package region is individually molded, each mold region 51 is connected by a mold gate portion (a portion corresponding to the resin injected into the gate of the mold) 52. ing. Each semiconductor package region is individually molded, and the resin material in the mold region 51 becomes the sealing resin portion 2. In a lead frame cutting process performed later, the portion of the lead frame 41 outside the mold region 51 is cut and removed, and each semiconductor package region is separated into the semiconductor device 1. For example, four semiconductor devices 1 can be obtained from the region shown in FIG.

  As shown in FIG. 17, when a plurality of semiconductor package regions are molded together (in FIG. 17, four semiconductor package regions are molded together), the mold region 51 is divided into a plurality of semiconductor package regions. The resin material in the mold region 51 is cut in the lead frame 41 cutting process performed later to become the sealing resin portion 2. In the cutting process of the lead frame 41, the semiconductor device 1 is cut along the dicing line 53, and each semiconductor package region is separated into the semiconductor device 1. For example, four semiconductor devices 1 can be obtained from the region shown in FIG.

  16 and 17, when the sealing resin is formed in the mold region 51, the upper and lower surfaces of the portion where the lead 4 is relatively thick are exposed from the sealing resin, and the upper portion of the lead 4 is exposed. The surface 4d and the lower exposed surface 4e can be formed.

  After performing the resin sealing step as described above (forming the sealing resin portion 2), if necessary, on the portion exposed from the sealing resin portion 2 of the lead frame 41 (portion made of a conductor). After forming a plating layer (not shown), that is, after forming a plating layer (for example, a solder plating layer, not shown) on the upper exposed surface 4d and the lower exposed surface 4e of the lead 4, the lead frame 41 is formed. By cutting at a predetermined position, the semiconductor device 1 divided into individual pieces as shown in FIGS. 1 to 4 is obtained (manufactured). The cutting process of the lead frame 41 can be performed by punching (punching) or dicing. When the lead frame 41 is cut by dicing, the cut surface 4f of the lead 4 and the cut surface 2c of the sealing resin portion 2 are set to the front surface 2a and the back surface 2b of the sealing resin 2 (that is, the front surface and the back surface of the semiconductor device 1). Since the plurality of semiconductor devices 1 can be stacked, the side surfaces of the plurality of semiconductor devices 1 can be aligned on substantially the same plane. In addition, after the lead frame 41 is cut to obtain the semiconductor device 1 divided into pieces, the upper exposed surface 4d and the lower exposed surface 4e of the lead 4 exposed from the sealing resin portion 2 of the semiconductor device 1 are plated. A layer (for example, a solder plating layer, not shown) can also be formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to, for example, a semiconductor device in the form of a semiconductor package.

It is a top view of the semiconductor device which is one embodiment of the present invention. FIG. 2 is a bottom view of the semiconductor device of FIG. 1. FIG. 2 is a plan perspective view of the semiconductor device of FIG. 1. FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1. It is sectional drawing which shows the state which mounted the semiconductor device on the board | substrate. It is sectional drawing which shows the state which laminated | stacked the several semiconductor device and mounted on the board | substrate. It is a top view for demonstrating the connection relation of the bonding wire in the case of laminating | stacking a semiconductor device. It is a top view for demonstrating the connection relation of the bonding wire in the case of laminating | stacking a semiconductor device. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; FIG. 12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; FIG. 13 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 12; FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; It is explanatory drawing of a sealing resin process. It is explanatory drawing of a sealing resin process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 1a Semiconductor device 1b Semiconductor device 1c Semiconductor device 1d Semiconductor device 1e Semiconductor device 2 Sealing resin part 2a Front surface 2b Back surface 2c Cut surface 3 Semiconductor chip 3a Electrode 3b Front surface 3c Back surface 4 Lead 4a End part 4b Upper surface 4c Lower surface 4d Upper part Exposed surface 4e Lower exposed surface 4f Cut surface 4g Inner lead part 6 Bonding wire 6a Bonding wire 7 Bonding material 14a Lead 14b Lead 15a Bus bar 15b Bus bar 21 Substrate 22 Conductive pattern 23 Bonding material 31 Lead 32 Lead 33 Lead 34 Lead 35a Lead for RAS 35b RAS lead 36a CAS lead 36b CAS lead 37 RAS / CAS electrode 41 Lead frame 42 Metal member 51 Mold region 52 Mold gate portion 53 Dicing line

Claims (10)

A semiconductor chip having a plurality of electrodes on the first main surface;
A plurality of lead portions formed of a conductor, a part of which is located on the first main surface of the semiconductor chip and bonded to the first main surface of the semiconductor chip;
A plurality of wires that electrically connect the plurality of lead portions and the plurality of electrodes of the semiconductor chip;
A sealing resin portion for sealing the semiconductor chip, the plurality of wires, and the plurality of lead portions;
Comprising
Each lead portion has a first exposed surface whose upper surface is exposed from the sealing resin portion, and a second exposed surface whose lower surface is exposed from the sealing resin portion,
The semiconductor device according to claim 1, wherein a second main surface opposite to the first main surface is exposed from the sealing resin portion. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of lead portions and the semiconductor chip are bonded via an insulating bonding material. The semiconductor device according to claim 1,
The first exposed surface of each lead portion is exposed from the first surface of the sealing resin portion, and the second exposed surface of each lead portion and the second main surface of the semiconductor chip are the sealing resin. The second exposed surface of each lead portion is exposed from a second surface opposite to the first surface of the portion, and the second surface of the sealing resin portion is substantially coplanar. Semiconductor device. The semiconductor device according to claim 1,
The first exposed surface of each lead portion is exposed from the first surface of the sealing resin portion, and the second exposed surface of each lead portion and the second main surface of the semiconductor chip are the sealing resin. And a second exposed surface of each lead portion protruding from the second surface of the sealing resin portion. The semiconductor device is exposed from a second surface opposite to the first surface of the portion. . The semiconductor device according to claim 1,
The first exposed surface of each lead portion is exposed from the first surface of the sealing resin portion, and the second exposed surface of each lead portion and the second main surface of the semiconductor chip are the sealing resin. The first exposed surface of each lead portion and the first surface of the sealing resin portion are substantially flush with each other, being exposed from a second surface opposite to the first surface of the portion. Semiconductor device. A first semiconductor chip having a plurality of first electrodes on the first main surface, and a portion of the first semiconductor chip that is formed of a conductor and located on the first main surface of the first semiconductor chip. A plurality of first leads joined to the first main surface, a plurality of first wires electrically connecting the plurality of first leads and the plurality of first electrodes of the first semiconductor chip; A first semiconductor package having a first sealing resin portion that seals the first semiconductor chip, the plurality of first wires, and the plurality of first lead portions;
A second semiconductor chip having a plurality of second electrodes on a third main surface; and a portion of the second semiconductor chip formed on a conductor and located on the third main surface of the second semiconductor chip. A plurality of second leads joined to the third main surface, a plurality of second wires electrically connecting the plurality of second leads and the plurality of second electrodes of the second semiconductor chip; A second semiconductor package having a second sealing resin portion for sealing the second semiconductor chip, the plurality of second wires, and the plurality of second lead portions;
Comprising
In the first semiconductor package, each of the first lead portions has a first exposed surface whose upper surface is exposed from the first sealing resin portion and a second exposure whose lower surface is exposed from the first sealing resin portion. And the first semiconductor chip has a second main surface opposite to the first main surface exposed from the first sealing resin portion,
In the second semiconductor package, each of the second lead portions has a third exposed surface whose upper surface is exposed from the second sealing resin portion and a fourth exposure whose lower surface is exposed from the second sealing resin portion. A second main surface of the second semiconductor chip that is opposite to the third main surface is exposed from the second sealing resin portion,
The second semiconductor package is mounted on the first semiconductor package, and the fourth exposed surface of each second lead portion of the second semiconductor package is the first lead portion of the first semiconductor package. 1. A semiconductor device, wherein the semiconductor device is electrically connected to an exposed surface. The semiconductor device according to claim 6.
The fourth exposed surface of each second lead portion of the second semiconductor package is bonded to the first exposed surface of each first lead portion of the first semiconductor package via a conductive bonding material. A semiconductor device. The semiconductor device according to claim 6.
In the second semiconductor package, the third exposed surface of each second lead portion is exposed from the first surface of the second sealing resin portion, and the fourth exposed surface of the second lead portion and the first 2 The fourth main surface of the semiconductor chip is exposed from a second surface opposite to the first surface of the second sealing resin portion, and the fourth exposed surface of each second lead portion is the first surface 2. A semiconductor device characterized by protruding from the second surface of the sealing resin portion. A semiconductor chip having a plurality of electrodes on the first main surface and a conductor, a part of which is located on the first main surface of the semiconductor chip and bonded to the first main surface of the semiconductor chip. A plurality of leads, a plurality of wires that electrically connect the plurality of leads and the plurality of electrodes of the semiconductor chip, and the semiconductor chip, the plurality of wires, and the plurality of leads are sealed. Each lead portion has a first exposed surface with an upper surface exposed from the sealing resin portion and a second exposed surface with a lower surface exposed from the sealing resin portion. And the semiconductor chip includes a plurality of semiconductor packages in which a second main surface opposite to the first main surface is exposed from the sealing resin portion,
The plurality of semiconductor packages are stacked, and among the plurality of stacked semiconductor packages, the second exposed surface of each lead portion of the upper semiconductor package has the second exposed surface of the lead portion of the lower semiconductor package. A semiconductor device, wherein the semiconductor device is electrically connected to the first exposed surface. The semiconductor device according to claim 9.
Of the plurality of stacked semiconductor packages, the second exposed surface of each lead portion of the upper semiconductor package has a conductive bonding material on the first exposed surface of each lead portion of the lower semiconductor package. A semiconductor device characterized by being bonded via

Images