JP2004311481A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device that can be reduced in on-resistance without increasing turning-off loss and, in addition, can be increased in withstand voltage. <P>SOLUTION: In a PT type IGBT having a planer structure, an n-type buffer layer 2 having a width of 40 μm and a peak concentration of 1×10<SP>16</SP>cm<SP>-3</SP>on a p<SP>-</SP>-type layer 3a side is formed on the rear surface of an n-type base layer 1 having an impurity concentration of 1×10<SP>13</SP>cm<SP>-3</SP>and a p-type emitter layer 3 composed of the p<SP>-</SP>-type layer 3a having a thickness of 5 μm and the peak concentration of 1×10<SP>16</SP>cm<SP>-3</SP>and a p<SP>+</SP>-type layer 3b having a thickness of 1μm and a peak concentration of 7×10<SP>17</SP>cm<SP>-3</SP>is formed on the rear surface of the buffer layer 2. In addition, a collector electrode 12 is formed on the p<SP>+</SP>-type layer 3b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a power semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) used as a high breakdown voltage element that operates in a bipolar mode.
[0002]
[Prior art]
In recent years, IGBTs have been improved in characteristics such as low on-resistance / high-speed / high-frequency / reduction of turn-off loss by miniaturization technology / optimization of device structure, etc., and low on-resistance without increasing turn-off loss. A possible IGBT has been announced.
[0003]
As this type of IGBT, those shown in FIGS. 4 and 5 are known (for example, Patent Document 1).
[0004]
FIG. 4 is a sectional view of the IGBT, and FIG. 5 is an impurity profile of the IGBT along the line BB in FIG.
[0005]
As shown in FIG. 4, the IGBT disclosed in Patent Document 1 has an N buffer layer 102 with a higher concentration than the N base layer 101 and an N buffer layer 102 with a lower concentration on the back surface of the N base layer 101 with a lower concentration. Also, a P-type emitter layer 103 of the opposite conductivity type with a high concentration is formed, and a plurality of P-base layers 105 are selectively formed on the surface of the N-base layer 101 of the silicon substrate 104 while being separated from each other. On the surface of the P base layer 105, a plurality of N emitter layers 106 having a higher concentration than the P base layer 105 are selectively formed separately from each other.
[0006]
A gate made of an N + polycrystalline silicon film is provided on a region from one of the N emitter layer 106 and the P base layer 105 to the other P base layer 105 and the N emitter layer 106 via the N base layer 101. The electrode 108 is formed on the silicon substrate 104 via the gate insulating film 107.
[0007]
Here, the surface portion of the P base layer 105 between the N emitter layer 106 and the N base layer 101 functions as a channel region.
[0008]
Further, in the insulating film 109 covering the gate electrode 108, contact openings 110 are provided so as to expose a part of the P base layer 105 and the N emitter layer 106 between the N emitter layers 106, respectively. An emitter electrode 111 is formed on each of the P base layer 105 and the N emitter layer 106. A collector electrode 112 is formed on the back surface of the P emitter layer 103 of the silicon substrate 104.
[0009]
In the above structure, as shown in FIG. 5, the N base layer 101 has an impurity concentration of 1 × 10 ¹³ cm ⁻³ , the N buffer layer 102 has a thickness of 40 μm, and has a peak concentration on the P emitter layer 103 side. It has 1 × 10 ¹⁶ cm ⁻³ . The P emitter layer 103 has a layer thickness of 1 μm and a peak concentration of 7 × 10 ¹⁷ cm ⁻³ on the collector electrode 111 side.
[0010]
As described above, by providing the thick and low-concentration N buffer layer 102 and the thin and high-concentration P emitter layer 103, the on-resistance (Eoff) is increased without increasing the turn-off loss (Eoff). Vce (sat.)), And the turn-off loss can be reduced even at high temperatures.
[0011]
[Patent Document 1]
JP-A-2001-332729 (page 7, FIGS. 1 and 3)
[0012]
[Problems to be solved by the invention]
However, in the above-mentioned conventional IGBT, since the impurity concentration gradient of the P emitter layer 103 is steep, when a reverse voltage is applied between the P emitter layer 103 and the N buffer layer 102, the P emitter layer 103 Since the depletion layer does not extend to the side, the reverse breakdown voltage is low, and the thickness of the P emitter layer 103 is as thin as 1 μm, so that the anode short-circuit state easily occurs due to the influence of defects introduced from the collector electrode 112 side. There is a problem that the directional breakdown voltage is reduced.
[0013]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that can have a low on-resistance and a high withstand voltage without increasing the turn-off loss.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, according to one embodiment of the present invention, there is provided a semiconductor device including a high-concentration layer of a first conductivity type and a low-concentration layer of the first conductivity type in contact with a main surface of the high-concentration layer. An emitter layer of a first conductivity type; a buffer layer of a second conductivity type formed on the low-concentration layer of the emitter layer of the first conductivity type and having the same concentration as the low-concentration layer of the first conductivity type; A second conductive type base layer formed on the second conductive type buffer layer; a first conductive type base layer selectively provided on the surface of the second conductive type base layer; A second conductivity type emitter layer selectively provided in the surface of the conductivity type base layer, and the first conductivity type base layer portion between the second conductivity type emitter layer and the second conductivity type base layer And a channel region formed on the surface of the channel region via a gate insulating film. A gate electrode, an emitter electrode formed on the first conductivity type base layer and the second conductivity type emitter layer, and a collector formed on the opposite surface of the first conductivity type high concentration layer. And an electrode.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
(First Embodiment)
First, an IGBT as a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a PT (punch through) type IGBT having a planar structure, and FIG. 2 is an impurity profile of the IGBT along the line AA in FIG. This embodiment is characterized in that the structure of the P emitter layer is changed in order to improve the breakdown voltage of the IGBT.
[0017]
In the IGBT according to the present embodiment, as shown in FIG. 1, on the back surface of the low-concentration N base layer 1, an N buffer layer 2 is formed. P-layer 3a and P-emitter layer 3 having high-concentration P + layer 3b in contact with P- layer 3a. On the other hand, a plurality of P base layers 5 are selectively formed on the surface of the N base layer 1 of the silicon substrate 4 while being separated from each other. On the surface of the P base layer 5, a plurality of N emitter layers 6 having a higher concentration than the P base layer 5 are selectively formed while being separated from each other.
[0018]
A gate made of an N + polycrystalline silicon film is provided on a region from one N emitter layer 6 and P base layer 5 to the other P base layer 5 and N emitter layer 6 via N base layer 1. The electrode 8 is formed on the silicon substrate 4 via the gate insulating film 7.
[0019]
Here, the surface portion of the P base layer 5 between the N emitter layer 6 and the N base layer 1 functions as a channel region.
[0020]
In the insulating film 9 covering the gate electrode 8, contact openings 10 are provided so as to expose a part of the P base layer 5 and the N emitter layer 6 between the N emitter layers 6, respectively. An emitter electrode 11 is formed on each of the P base layer 5 and the N emitter layer 6. A collector electrode 12 is formed on the back surface of the P emitter layer 3 of the silicon substrate 4.
[0021]
Then, as shown in FIG. 2, the N base layer 1 is formed with an impurity concentration of 1 × 10 ¹³ cm ⁻³ , the N buffer layer 2 has a layer thickness of 40 μm, and a peak concentration of 1 × 10 ¹³ cm ⁻³ on the P− layer 3a side. It has 10 ¹⁶ cm ⁻³ . The P− layer 3a has a layer thickness of 5 μm and a peak concentration of 1 × 10 ¹⁶ cm ⁻³ , and the P + layer 3b has a layer thickness of 1 μm and a peak concentration of 7 × 10 ¹⁷ cm ⁻³ . ing.
[0022]
As a method of forming the P− layer 3a and the P + layer 3b, boron is ion-implanted from the back surface side of the silicon substrate 4 at a low dose, and then the boron is thermally diffused to form the P− layer 3a. After boron is ion-implanted at a high dose, heat treatment is performed to the extent that boron is activated to form a P + layer 3b.
[0023]
Here, the N buffer layer 2 has a layer thickness of 40 μm and a peak concentration of 1 × 10 ¹⁶ cm ⁻³ . However, in order to reduce the ON resistance without increasing the turn-off loss, the N buffer layer 2 has a thickness of 20 to A range of 40 μm and a peak concentration of 3 × 10 ¹⁶ cm ⁻³ or less is preferable. The P− layer 3a has a layer thickness of 5 μm and a peak concentration of 1 × 10 ¹⁶ cm ^−3. To improve the reverse breakdown voltage between the P emitter layer 3 and the N buffer layer 2, The thickness is preferably ³ μm or more, and the peak concentration is preferably 3 × 10 ¹⁶ cm ⁻³ or less.
[0024]
Further, in order to control the injection of holes from the P emitter layer 3 at the time of a large current, the product of the peak concentration and the layer thickness of the P + layer 3b is 3 times smaller than the product of the peak concentration and the layer thickness of the P− region 3a. It is preferably larger by a factor of two or more. Further, in order to make good contact between the collector electrode 12 and the P emitter layer 3, the thickness of the P + layer 3b is preferably 1 μm or less.
[0025]
According to such an IGBT of the present embodiment, the peak concentration of N buffer layer 2 is formed as low as 1 × 10 ¹⁶ cm ^−3, and the P − layer formed in contact with N buffer layer 2 is formed. Since 3a has a layer thickness of 5 μm and a low concentration of 1 × 10 ¹⁶ cm ⁻³ , the amount of carriers accumulated in the N buffer layer 2 can be reduced. Further, the P + layer 3b is formed in contact with the P− layer 3a to have a layer thickness of 1 μm and a peak concentration of 7 × 10 ¹⁷ cm ^−3, and the peak concentration of the N buffer layer 2 is as low as 1 × 10 ¹⁶ cm ^−3. Since it is formed at a concentration, the amount of holes injected from the P emitter layer 3 composed of the P− layer 3a and the P + layer 3b into the N base layer 1 can be appropriately maintained. ON resistance can be achieved.
[0026]
Since the P− layer 3a is provided between the N buffer layer 2 and the P + layer 3b, the reverse voltage application (reverse voltage) of the PN junction composed of the low concentration N buffer layer 2 and the low concentration P− layer 3a is performed. (At the time of blocking), the depletion layer can be extended to the P − layer 3a, so that the reverse breakdown voltage can be increased (high breakdown voltage).
[0027]
Further, since the layer thickness of the P emitter layer 3 is relatively large, electrical contact between the collector electrode 12 and the N buffer layer 2 due to defects such as metal intrusion generated when forming the collector electrode 12 can be avoided. Therefore, a stable reverse breakdown voltage can be secured.
[0028]
Since the P + layer 3b is provided in contact with the P− layer 3a, the amount of holes injected into the N base layer 1 is ensured, and the injection of holes from the P emitter layer 3 at the time of large current and high voltage is controlled. Therefore, destruction at the time of load short-circuit can be prevented.
[0029]
Further, instead of controlling the lifetime by introducing recombination centers such as proton irradiation, a P emitter layer 3 including a low-concentration N buffer layer 2, a low-concentration P- layer 3a and a high-concentration P + layer 3b is provided. Therefore, even at a high temperature, a large current can be cut off when a load is short-circuited while reducing the on-resistance without increasing the turn-off loss at the time of conduction.
[0030]
(Second embodiment)
Next, an IGBT as a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a sectional view of the IGBT.
[0031]
This embodiment differs from the first embodiment in that a recombination center 13 is provided in the N base layer 1. Other configurations are the same, and only different points will be described.
[0032]
In the IGBT of the present embodiment, as shown in FIG. 3, recombination centers 13 are formed in N base layer 1 by electron beam irradiation or heavy metal diffusion. The introduction of the recombination center 13 accelerates the disappearance of carriers existing in the N base layer 1 at the time of turn-off, and reduces the carrier lifetime to, for example, 15 μs or less.
[0033]
Here, the recombination center 13 is formed in the N base layer 1, but may be formed in the N buffer layer 2 or in the N base layer 1 and the N buffer layer 2.
[0034]
As described above, in the semiconductor device of the present embodiment, in addition to the same effects as those of the first embodiment, since the recombination center 13 is provided in the N base layer 1, the carrier lifetime can be reduced. Turn-off loss can be reduced. Since the disappearance of carriers on the collector side is accelerated, the breakdown strength during current interruption is increased, and a larger current can be interrupted.
[0035]
Further, when the lifetime is reduced, the on-resistance generally increases. However, since the low-concentration N buffer layer 2 is provided, the layer width of the N base layer 1 can be made relatively small, and furthermore, the conduction time is reduced. Since the carrier concentration in the N base layer 1 is appropriately controlled, the turn-off loss can be further reduced while suppressing the increase in the on-resistance.
[0036]
In addition to providing the recombination center 13, the N buffer layer 2 having a low peak concentration (1 × 10 ¹⁶ cm ⁻³ ) on the back surface of the N base layer 1 and the peak concentration in contact with the N buffer layer 2 Is provided with a low concentration (1 × 10 ¹⁶ cm ⁻³ ) P− layer 3a and a P emitter layer 3 composed of a high concentration P + layer 3b in contact with the P− layer 3a, so that turn-off loss is reduced. The amount of recombination centers introduced for this purpose can be reduced to the minimum necessary, and an increase in turn-off loss at high temperatures can be suppressed.
[0037]
The present invention is not limited to the above embodiment, and may be implemented with various modifications without departing from the spirit of the invention.
[0038]
For example, in the above-described embodiment, the IGBT having the planar structure has been described. However, the IGBT having the trench structure, the Injection Enhanced Gate Transistor (IEBT), and the bipolar device which operates in the bipolar mode such as the Carrier Stored Trench Gate Bipolar Transistor (CSTBT). Applicable.
[0039]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor device that can have a low on-resistance without increasing the turn-off loss and a high withstand voltage.
[Brief description of the drawings]
FIG. 1 is a sectional view of an IGBT according to a first embodiment of the present invention.
FIG. 2 is an impurity profile of the IGBT according to the first embodiment of the present invention.
FIG. 3 is a sectional view of an IGBT according to a second embodiment of the present invention.
FIG. 4 is a cross-sectional view of a conventional IGBT.
FIG. 5 is an impurity profile of a conventional IGBT.
[Explanation of symbols]
1, 101 N base layer 2, 102 N buffer layer 3, 103 P emitter layer 3a P− layer 3b P + layer 4, 104 silicon substrate 5, 105 P base layer 6, 106 N emitter layer 7, 107 gate insulating film 8, 108 Gate electrode 9, 109 Insulating film 10, 110 Contact opening 11, 111 Emitter electrode 12, 112 Collector electrode 13, Recombination center

Claims (5)

A first conductivity type emitter layer having a first conductivity type high concentration layer and a first conductivity type low concentration layer in contact with a main surface of the high concentration layer;
A second-conductivity-type buffer layer formed on the low-concentration layer in the first-conductivity-type emitter layer and having the same concentration as the first-conductivity-type low-concentration layer;
A second conductivity type base layer formed on the second conductivity type buffer layer;
A first conductivity type base layer selectively provided in the surface of the second conductivity type base layer;
A second conductivity type emitter layer selectively provided in the surface of the first conductivity type base layer;
A channel region formed by the first conductive type base layer portion between the second conductive type emitter layer and the second conductive type base layer;
A gate electrode provided on the surface of the channel region via a gate insulating film;
An emitter electrode formed on the first conductive type base layer and the second conductive type emitter layer;
A collector electrode formed on the opposite side of the first conductivity type high concentration layer;
A semiconductor device operating in a bipolar mode, comprising: The second conductive type buffer layer has a peak concentration of 3 × 10 ¹⁶ cm ⁻³ or less, the first conductive type low concentration layer has a peak concentration of 3 × 10 ¹⁶ cm ⁻³ or less, and the first conductive type buffer layer has a peak concentration of 3 × 10 ¹⁶ cm ⁻³ or less. 2. The semiconductor device operating in a bipolar mode according to claim 1, wherein a peak concentration of the conductive high-concentration layer is 5 × 10 ¹⁷ cm ⁻³ or more. The thickness of the buffer layer of the second conductivity type is 20 to 40 μm, the thickness of the low-concentration layer of the first conductivity type is 3 μm or more, and the thickness of the high-concentration layer of the first conductivity type is 1 μm or less. 3. The semiconductor device according to claim 1, wherein the semiconductor device operates in a bipolar mode. 2. The product of the peak concentration and the thickness of the high concentration layer of the first conductivity type is at least three times the product of the peak concentration and the thickness of the low concentration layer of the first conductivity type. 3. 4. The semiconductor device operating in the bipolar mode according to any one of claims 1 to 3. In the second conductivity type base layer, in the second conductivity type buffer layer, or in the second conductivity type base layer and the second conductivity type buffer layer, the lifetime is reduced to reduce the lifetime. 5. The semiconductor device according to claim 1, wherein the semiconductor device has a coupling center and has a lifetime of 15 μs or less.

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