JP2004348745A - Bus system for mediating system bus having high-speed bandwidth, and its method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus system for mediating a system bus having a high-speed bandwidth, and to provide its method. <P>SOLUTION: This bus system generates a virtual approval signal to all requesting master units, and receives processing information from all the requesting master units. Specifically, the bus system makes all bus masters each having a bus use request operate as if they have obtained a bus use right to acquire drive information required in slave access, and thereby mediates to carry out optimized access to improve a slave access bandwidth. In accessing a synchronous DRAM having a long waiting time, the bus system makes all the bus masters each having a bus use right operate as if they have obtained the bus use right to acquire necessary drive information, whereby the access bandwidth of the synchronous DRAM is optimized by using a bus interleaving method. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  Arbitration mechanisms for improving bus bandwidth between at least one master and at least one slave are well known. The basic operations of the arbitration include a request, an arbitration, an grant, and a data transfer.

  The arbiter grants bus ownership to the master that has requested access to the target slave. If the target slave is not in the data transmission state, the master has to wait until the target slave is ready for data transmission, so that ownership acknowledgment is not required. If the master accesses a target slave having a long latency, the bandwidth is also reduced.

  FIG. 1 is a general timing chart showing a waiting time (T).

  Referring to FIG. 1, when a first set of address information ADDR1 to ADDR4 is provided, a first set of data DATA D1 to D4 follows. Subsequently, when a second set of address information ADDR5-8 is provided, a second set of data DATAD5-D8 follows. The waiting time T is a delay time between the data D4 and D5, and it is not desirable to have this delay time. FIG. 2 is a preferred timing diagram in which the waiting time has been eliminated.

  Bank interleaving is used as a typical technique for dividing memory into several banks, thereby making each bank accessible successfully. In bank interleaving, the operations of the two banks are overlapped. For example, to improve bus bandwidth, data is accessed in one bank and simultaneously precharged in another.

  However, bank interleaving has some disadvantages. That is, the master can drive the master with valid addresses and control information after receiving bus ownership through arbitration. Therefore, such information is generated after arbitration and cannot be used for arbitration. As a result, bandwidth improvement is limited. Further, since the request for the target slave cannot be sent in advance, the waiting time T is delayed and still exists, as described above.

  Other common devices with a master generate a cycle type signal upon request. The cycle type signal indicates a specific target resource (slave) to be accessed and indicates reading or writing of the target. Based on the cycle type signal and the associated target resource information, the arbiter prioritizes bus ownership. In this manner, target slave retry cycles are avoided, and bus bandwidth and overall system performance can be improved. However, additional pins are required to provide a cycle type signal, so that it cannot immediately send a request for a target slave, is delayed by a waiting time T, and still exists.

  FIG. 3 shows a general bus structure including masters 1 to 3, an arbiter 4, an SDRAM controller 5, and an SDRAM bank 6. Each of the masters 1 to 3 requests a bus access from the arbiter 4 by the HBUSREQN signal. The arbiter 4 includes an arbitration logic for selecting any one of the masters 1 to 3, and the bus access is performed by an HGRANTN signal provided to the selected master among the masters 1 to 3. Arbitration and approval. Referring to FIG. 3, the signals HADDRN, HWRITEN, HBURSTN, HSIZEN, and HTRANN are signals for driving respective slaves. Such signals are provided from the masters 1 to 3 to the SDRAM controller 5 via one or more multiplexers MUX7 to MUX8. The MUXs 7 to 8 receive the HMASTER signal from the arbiter 4 and transmit the selected HADDR, HWRITER, HBURSTR, HSIZER and / or HTRANSR signal to the SDRAM controller 5. The MUX 7 receives the HWDATAN signal from each of the masters 1 to 3, and transmits one of the HWDATAN signals to the SDRAM controller 5 as a BIWDATA signal. When ready, the SDRAM controller 5 transmits a BIREADYD signal to each of the masters 1 to 3. Further, the SDRAM controller 5 converts the signal and the data so as to move back and forth between the SDRAMs 6.

FIG. 4 is a timing chart showing a typical bus structure described in Non-Patent Document 1. As shown in FIG. 4, the waiting time T exists between transmissions between the first data BOD0 to BOD3 and the second data BID0 to BID3. This waiting time T is caused by the inability of the arbiter 4 to request the target slave to previously prepare for data access to accept bus ownership through arbitration, thus reducing bus bandwidth. Let it.
Advanced Microcontroller Bus Architecture (AMBA) Specification 2.0

  SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide an arbiter and a system for improving the access bandwidth between a large number of masters and slaves on a bus of a system having a high bandwidth. To provide.

  Another object of the present invention is to solve the above-mentioned problems, and to improve an access bandwidth between a large number of masters and slaves on a system bus having a high-speed bandwidth, an arbiter and an arbiter. An object of the present invention is to realize a method for suppressing slave access of a system.

  Still another object of the present invention is to solve the above-mentioned problems, and to maximize an access bandwidth using a bank interleaving method when accessing data of a slave having a long waiting time. A system and a method thereof are provided.

  In an embodiment of the present invention, the present invention provides a virtual-acknowledge (pseudo-grant) signal to all master units that generate a request signal, and all master units that generate a request signal in response to the virtual-acknowledge signal. Implements a system arbiter for accepting transmission information from

  In an embodiment of the present invention, the present invention provides at least one master unit for generating a request signal for bus use, receiving a request signal from at least one master unit, and responding to the request signal from the at least one master unit. An arbiter for generating a virtual-approval signal, wherein the at least one master unit provides target information to the arbiter in response to the virtual-approval signal, and the at least one slave unit includes the at least one slave unit. A system for preparing for data transmission in response to the target information provided by one master unit is realized.

  In an embodiment of the present invention, the present invention realizes a mediation method for a system that generates a virtual-approval signal in response to a request signal and accepts target information in response to the virtual-approval signal.

  In an embodiment of the present invention, the present invention generates a request signal, accepts the request signal, generates a virtual-authorization signal in response to the request signal, and provides target information in response to the virtual-authorization signal. And arbitrating a system for preparing data transmission in response to the target information.

  The bus system of the present invention operates all bus masters having a bus use request as if they had the right to use the bus, and acquires necessary drive information at the time of slave access, so that optimized access is obtained. Arbitrate to improve slave access bandwidth.

  Also, when accessing a synchronous DRAM having a long waiting time, all the bus masters that have a bus use request are operated as if they have the right to use the bus, necessary drive information is obtained, and the bank interleaving method is used. The access bandwidth of the synchronous DRAM can be optimized.

  FIG. 5 illustrates a bus arbitration structure according to an embodiment of the present invention. Referring to FIG. 5, the bus arbitration structure includes N master units 110, 120, and 130, an arbiter 140, and M slave units. Here, N is an integer of 1 or more, M is an integer of 1 or more, and is not the same value as N. In operation, each master unit 110, 120, 130 transmits a request signal HBUSREQN to the arbiter 140. The HBUSREQN signal is a request signal for accessing one target slave, for example, the slave unit 150, 160 or 170. The arbiter 140 provides a virtual grant signal HGRANT to each of the N requesting master units 110, 120, 130. The HGRANT signal is a signal for acknowledging bus ownership for bus use by one master. Each of the N master units 110, 120, 130 provides target information to the arbiter 140 such that the arbiter 140 performs arbitration. In the preferred embodiment shown in FIG. 5, the target information is a HADDRN signal. The arbiter 140 performs arbitration and indicates that the data transmission is ready to occur by providing a ready signal HREADYN to each master 110,120.

  When at least two or more masters 110, 120, and 130 request a bus access, the HBUSREGN signal becomes asserted. In such a case, the arbiter 140 responds to the HGRANTN signal in response to the HGRANTN signal to all of the requested masters 110, 120, and 130 prior to the arbitration. pseudo) 'grant ownership. Masters 110, 120, 130 accept the bus ownership and drive the necessary information (eg, HADDRN) for the target slave. The arbiter 140 uses the target slave information associated with this information to perform the arbitration operation. After arbitration and checking the bus availability, the arbiter 140 actually transmits the activated HREADY signal to the selected master having bus ownership.

  Generally, the HGRANT signal is granted after arbitration. In a preferred embodiment of the present invention, the HGRANT signal is granted after the request and before the arbitration as described above.

  FIG. 6 is a preferred timing diagram of the present invention. Referring to FIG. 6, the HGRANT1 signal is triggered to be high in response to the HBUSREQ1 signal. The HADDR1 signal is generated in response to the transition of the HGRANT1 signal to high, and is synchronized with HCLK. Similarly, the HGRANT2 signal is triggered high in response to the HBUSREQ2 signal. Also, the HADDR2 signal is generated in response to the HGRANT2 signal going high, and is synchronized with HCLK. As shown in FIG. 6, data information HRDATA including DARA1 is generated in response to the HREADY1 signal, and data, that is, DATA5 is generated in response to the HREADY2 signal. As shown in FIG. 6, in the preferred embodiment of the present invention, the arbiter 140 receives the HADDR2 signal from the masters 110, 120, 130 earlier, thus reducing the time delay.

  Referring to FIG. 7 and / or FIG. 8, the HADDR, HBURST, and HWRITE signals are signals for driving a target slave, respectively. The BIREQD signal is a signal requesting a target slave to prepare for data access. The BIADDR, BIBA, and BIRCCONT signals are all signals containing information for controlling the target slave. The BICONFIRMD signal is a signal (acknowledgment signal: ACK) for recognizing the BIREQD signal. The NDCAS, NRAS, NCAS, and NDWE signals are command signals for accessing a target slave or another embodiment of the present invention, ie, a special memory bank. The BA signal is a bank address signal and the BIREADYD signal is a signal that is triggered to be activated when the target slave regulates data transmission. The HREADYN signal is a signal indicating whether a specific master currently has the bus ownership for data transmission to / from a target slave.

  FIG. 7 illustrates the bus structure of FIG. 5 according to an embodiment of the present invention in more detail. As shown in FIG. 7, the arbiter 550 includes a master interface 552 and a slave controller interface 554. The master interface 552 interacts with the N master units 510, 520, 530, and the slave controller interface 554 interacts with the M slave controllers 571, 572, 573. The M slave controllers 571, 572, 573 control at least one or more slave units 541, 542, 543.

  As shown in FIG. 7, each master unit 510, 520, 530 provides an HBUSREQ signal to the arbiter 550. Arbiter 550 generates an HGRANT signal for each of the master units. Next, each of the master units provides a HADDR signal, an HBURST signal, and / or an HWRITE signal to the arbiter 550.

  Each of the master units 510, 520, and 530 supplies the HWDATAn signal to the multiplexer MUX 560, and one of the HWDATAn is supplied to the slave controllers 571, 572, and 573 as BIWDATA. The slave controllers 571, 572, 573 transmit data to / from the slave units 541, 542, 543. Also, the slave controllers 571, 572, and 573 provide a BIRDATAn signal to the multiplexer MUX 580, and one of the BIRDATAn is supplied to the master units 510, 520, and 530 as a BIRDATA signal.

  FIG. 8 is a diagram showing a detailed configuration of the general-purpose bus arbitration circuit shown in FIG. 5 according to another embodiment of the present invention. Referring to FIG. 8, arbiter 250 includes a master interface 252 and an SDRAM controller interface 254. Master interface 252 interacts with master units 210, 220, 230 and multiplexer 260 as described in connection with FIG. The SDRAM controller interface 254 supplies the BIRAMD, BIADDR, BIBA, BIBE, BIRCONT, and BICCONT signals to the SDRAM controller 270, and accepts the BIREADYD and BICONFIRMD signals from the SDRAM controller 270. The SDRAM controller 270 receives the BIWDATA from the selected one of the master units 210, 220, and 230 via the MUX 260, and provides the BIRDATA to the selected one of the master units 210, 220, and 230. SDRAM controller 270 provides NDCS, NRAS, NCAS, NDWE, BA and ADDR signals to SDRAM 240 and accepts data from SDRAM 240 again. In this embodiment, the SDRAM 240 includes at least one or more memory banks indicated by reference numerals 241, 242, 243 and 244.

  FIG. 9 is a timing diagram according to an embodiment of the present invention. As shown in FIG. 9, the master can transmit information quickly because the arbiter sends the permission signal early through the virtual approval signal. Since the arbiter can receive the information of the target slave earlier, it can request the slave to prepare for data transmission through the RAS1 and CAS1 signals.

  FIG. 10 shows an embodiment of the master interface shown in FIG. 7 or FIG. Referring to FIG. 10, the master interfaces 252, 552 include synchronization units 1001, 1002, 1003, each of which receives an HBUSREQ signal from the master unit and outputs an HGRANT signal. Master interfaces 252, 552 further include multiplexers 1005, 1006, 1008. These accept a BIREADYD signal indicating whether the target slave is ready for data transmission and output at least one or more HREADY signals. As shown in FIG. 10, master interfaces 252, 552 may be any arbitration logic.

  FIG. 11 is a flowchart according to an embodiment of the present invention. As shown in step S310, the arbiter determines whether at least one master issues a bus request. As a result of the determination, if there is no request, the arbiter stays in the holding loop. If there is a request, in step S320, the arbiter transmits an HGRANT signal to all requested master units. In step S330, the arbiter receives driving information from all requested master units. In step S340, a specific master is selected by the arbiter based on the driving information and the target slave status information.

  In step S350, the arbiter requests the slave accessed by the selected master to prepare for data transmission in order to reduce the waiting time with the target slave regardless of the availability of the bus. In operation S360, the slave controller transmits a command signal to the target slave. The flow chart shown in FIG. 11 shows the first stage according to an embodiment of the method of the present invention.

  FIG. 12 shows the second stage. In step S410, the arbiter determines what target slave the data transmission is prepared for. If not, the arbiter will stay on the holding roof. If so, in step S420, the arbiter determines whether the bus is available. If the bus is not available, the arbiter will stay on the holding roof. If the bus is available, in step S430, the arbiter selects one of the masters that has requested access to the target slave ready for data transmission. In operation S440, the data is transmitted between the selected bus master and the connection target slave. Then, such a process is repeated.

  As described above, the embodiment of the present invention changes the arbitration signal procedure from the general arbitration signal procedure. In particular, in embodiments of the present invention, the virtual acknowledgment signal is processed prior to arbitration. Also, since the information transmission is processed prior to the arbitration, the information included in the data transmission is used for the arbitration decision. Therefore, the embodiment of the present invention can reduce or eliminate the waiting time T.

  Although embodiments of the present invention have been described in detail using specific controller interfaces and memories, it will be apparent that other interfaces and / or memories well known in the art can be used. . Further, while the embodiments of the present invention have been described with respect to a specific bus contention, the idea of the present invention solves other bus races or other resource races well known in the related art. It can also be used to

  Obviously, the invention described above can be modified in various ways. It is obvious for those having ordinary skill in the art that various modifications and changes can be made without departing from the scope and spirit of the invention. It is obvious that such modifications are included in the technical scope of the present invention.

FIG. 4 is a typical timing chart showing a waiting time T. FIG. 9 is a desired timing chart in which the waiting time T is removed. It is a figure showing a typical bus structure. FIG. 4 is a timing diagram of a typical bus structure. FIG. 2 is a diagram illustrating a bus arbitration structure according to an embodiment of the present invention. FIG. 4 is a timing diagram according to an embodiment of the present invention. FIG. 6 is a diagram illustrating the bus structure of FIG. 5 in further detail according to an embodiment of the present invention. FIG. 6 is a diagram illustrating a detailed structure of another embodiment of the general-purpose bus arbitration circuit illustrated in FIG. 5. FIG. 4 is a timing diagram of an embodiment according to the present invention. FIG. 9 is a diagram illustrating a master interface shown in FIG. 7 or 8 according to an embodiment of the present invention. 4 is a flowchart showing a first state of the method according to an embodiment of the present invention. 4 is a flowchart illustrating a second state of the method according to an embodiment of the present invention.

Claims (33)

  An arbiter for a system, wherein a virtual approval signal is generated for all requested master units, and processing information is received from all requested master units in response to the virtual approval signal. The arbiter is
The arbiter of claim 1, wherein the arbiter further performs arbitration based on the processing information received from the requesting master unit. The arbiter is
The virtual approval signal is generated for all the requested master units, the processing information is received from the requested master units in response to the virtual approval signal, and one of the requested master units is selected. The arbiter of claim 1, further comprising a master interface for generating a ready signal. The master interface comprises:
The arbiter according to claim 3, further comprising at least one generator for generating the virtual acknowledgment signal from at least one request signal generated from all the requested master units. The master interface comprises:
4. The apparatus as claimed in claim 3, further comprising at least one circuit for converting one target slave preparation signal from at least one slave into a data transmission preparation signal for one of the requested master units. The arbiter described in 1.   The arbiter according to claim 3, wherein the preparation signal is a signal for data transmission.   The arbiter according to claim 3, wherein the preparation signal indicates bus availability. The arbiter is
A controller interface for requesting at least one slave unit to prepare for data transmission in response to the target information from the selected one of the requested master units. Item 7. The arbiter according to item 1. The controller interface includes:
The arbiter of claim 8, wherein the arbiter is a slave controller interface operatively associated with at least one slave controller of the at least one slave unit.   The arbiter according to claim 9, wherein each slave controller controls at least one slave memory.   The arbiter of claim 8, wherein the controller interface is an SDRAM controller interface that operates in conjunction with at least one SDRAM controller of at least one slave unit.   The arbiter of claim 11, wherein each SDRAM controller controls at least one SDRAM memory bank.   The arbiter according to claim 1, wherein the requests from all the requested master units are synchronized with a system clock. At least one master unit for generating a request signal;
An arbiter receiving the request from the at least one master unit and generating a virtual acknowledgment signal in response to the request from the at least one master unit;
The at least one master unit that supplies target information to the arbiter in response to the virtual acknowledgment signal;
At least one slave unit that prepares for data transmission in response to the target information provided by the at least one master unit.   The data of at least one slave unit may be transmitted between the at least one master unit and one of the at least one slave units when data transmission preparation is completed. System.   The system of claim 14, wherein all master units requested by the system accept the virtual acknowledgment signal from the arbiter.   The system of claim 14, wherein the request from the at least one master unit is synchronized with a system clock.   The system of claim 14, wherein the virtual acknowledgment signal from the arbiter and the target information from the at least one master unit are synchronized. In the arbitration method of the system,
Generating a virtual authorization signal in response to the request;
Accepting target information in response to the virtual acknowledgment signal.   The method of claim 19, further comprising arbitrating based on the target information.   The method of claim 19, wherein the request and the target information are generated from a plurality of master units.   The method of claim 19, wherein the virtual approval signal is generated in response to all requests.   20. The method of claim 19, further comprising requesting a preparation for data transmission in response to the target information.   The method of claim 19, wherein the request is synchronized with a system clock.   The method of claim 19, wherein the method is by software or hardware. Generating a request;
Accepting the request and generating a virtual acknowledgment signal in response to the request;
Providing target information in response to the virtual acknowledgment signal;
Preparing a data transmission in response to the target information.   The method of claim 26, wherein the request and the target information are generated from a plurality of request master units. Completing data transmission preparations;
28. The method of claim 27, further comprising transmitting data.   The generating, receiving, supplying, and preparing steps constitute a first stage, the completing and transmitting steps constitute a second stage, and the first and second steps are performed. The method of claim 26, wherein the second stage occurs simultaneously.   30. The method of claim 29, wherein when the data transmission preparation is completed, the bus is available, and the method includes determining a selected one of the requesting masters.   The method of claim 26, wherein the virtual acknowledgment signal is generated in response to all requests.   The method of claim 26, wherein the request is synchronized with a system clock.   The method of claim 26, wherein the method is implemented by software or hardware.

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