JP2003309266A - Method for manufacturing organic thin-film transistor element - Google Patents
Method for manufacturing organic thin-film transistor elementInfo
- Publication number
- JP2003309266A JP2003309266A JP2002114588A JP2002114588A JP2003309266A JP 2003309266 A JP2003309266 A JP 2003309266A JP 2002114588 A JP2002114588 A JP 2002114588A JP 2002114588 A JP2002114588 A JP 2002114588A JP 2003309266 A JP2003309266 A JP 2003309266A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- thin film
- film transistor
- transistor element
- organic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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Landscapes
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、有機薄膜トランジ
スタ素子の製造方法に関する。TECHNICAL FIELD The present invention relates to a method for manufacturing an organic thin film transistor element.
【0002】[0002]
【従来の技術】情報端末の普及に伴い、コンピュータ用
のディスプレイとしてFPD(フラットパネルディスプ
レイ)に対するニーズが高まっている。また、更に情報
化の進展に伴い、従来は紙媒体で提供されていた情報が
電子化されて提供される機会が増え、薄くて軽い、手軽
に持ち運び可能なモバイル用表示媒体として、電子ペー
パーまたは、デジタルペーパー等へのニーズも高まりつ
つある。2. Description of the Related Art With the spread of information terminals, there is an increasing need for FPDs (flat panel displays) as displays for computers. In addition, with the progress of computerization, the opportunity to electronically provide information that was conventionally provided in paper medium is increased, and as a thin, light, and easily portable mobile display medium, electronic paper or The need for digital paper is also increasing.
【0003】一般に平板型のディスプレイ装置のおいて
は、液晶、有機EL、電気泳動等を利用した素子を用い
て表示媒体を形成している。また、こうした表示媒体で
は画面輝度の均一性や画面書き換え速度等を確保する為
に、アクティブ駆動素子を用いる技術が主流になってい
る。例えば、通常のコンピュータディスプレイではガラ
ス基板上にこれら、TFT(Thin Film Tr
ansistor)素子を形成し、液晶、有機EL等が
封止されている。Generally, in a flat panel display device, a display medium is formed by using elements utilizing liquid crystal, organic EL, electrophoresis or the like. Further, in such a display medium, a technique using an active driving element has become mainstream in order to secure the uniformity of screen brightness and the screen rewriting speed. For example, in a normal computer display, these TFTs (Thin Film Tr
A liquid crystal, organic EL, etc. are sealed.
【0004】一方、最近、薄膜トランジスタ(TFT)
内の活性半導体層として使用するために有機材料が検討
されている。有機材料は加工が容易であり、一般にTF
Tが形成されるプラスチック基板と親和性が高いので、
薄膜デバイス内の活性半導体層とshちえの利用が期待
されている。On the other hand, recently, thin film transistors (TFTs)
Organic materials are being considered for use as active semiconductor layers within. Organic materials are easy to process and generally TF
Since it has a high affinity with the plastic substrate on which T is formed,
It is expected to utilize the active semiconductor layer and sh tie in a thin film device.
【0005】従って、低コストで大面積のデバイス、特
にディスプレイのアクティブ駆動素子として検討が進め
られており、例えば、特開平10−190001号、特
開2000−307172等の技術が開示されている。Therefore, studies are underway as a low-cost, large-area device, particularly as an active driving element for a display, and techniques such as Japanese Patent Laid-Open Nos. 10-190001 and 2000-307172 are disclosed.
【0006】有機半導体が薄膜TFT内の活性半導体層
として使用されるためには、結果として得られるデバイ
スのオン/オフ比やリーク電流、ゲートの駆動電圧が充
分に満たされるものでなくてはならない。In order for an organic semiconductor to be used as an active semiconductor layer in a thin film TFT, the on / off ratio, leakage current and gate drive voltage of the resulting device must be sufficiently satisfied. .
【0007】しかしながら、近年、TFTとして成果が
報告されている有機半導体は、イントリンシック型が主
流であり、チャネルを形成する有機半導体は非常に高純
度であることが要求される。有機半導体の材料は純度が
高くとも、素子形成においてチャネル近傍の不純物が混
入することで、リーク電流が大きくなる問題が生じてい
る。また、TFTシートの製造工程において、TFTに
微小なゴミ(パーティクル)が付着することにより、デ
ィスプレイの画素欠陥になりやすいという問題点があ
る。However, in recent years, the organic semiconductors that have been reported to be successful as TFTs are mainly of the intrinsic type, and the organic semiconductor forming the channel is required to have a very high purity. Even if the material of the organic semiconductor has high purity, there is a problem that the leakage current becomes large due to the inclusion of impurities in the vicinity of the channel during element formation. Further, in the manufacturing process of the TFT sheet, there is a problem that minute dust (particles) adheres to the TFT, which easily causes pixel defects of the display.
【0008】これら、上記の問題点の改良が要望されて
いる。There is a demand for improvement in these problems.
【0009】[0009]
【発明が解決しようとする課題】本発明の目的は、素子
形成時のチャネル近傍の不純物の混入や微小なゴミ(パ
ーティクル)の付着を防止することにより、リーク電流
が低減し、且つ、画素欠陥の少ない有機薄膜トランジス
タ素子の製造方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to reduce the leak current and prevent pixel defects by preventing impurities from mixing in the vicinity of the channel and adhesion of fine dust (particles) during element formation. It is an object of the present invention to provide a method for manufacturing an organic thin film transistor element with less power consumption.
【0010】[0010]
【課題を解決するための手段】本発明の上記目的は、下
記の構成1、2によって達成された。The above objects of the present invention have been achieved by the following constitutions 1 and 2.
【0011】1.支持体上に、少なくともゲート電極、
絶縁層、ソース電極、ドレイン電極、有機半導体層を有
する有機薄膜トランジスタ素子の製造方法において、該
有機半導体層と接する部位の表面を予めプラズマ処理す
る工程の後、前記有機半導体層を設ける工程を有するこ
とを特徴とする有機薄膜トランジスタ素子の製造方法。1. At least a gate electrode on the support,
In a method for manufacturing an organic thin film transistor element having an insulating layer, a source electrode, a drain electrode, and an organic semiconductor layer, a step of providing the organic semiconductor layer after the step of plasma-treating a surface of a portion in contact with the organic semiconductor layer in advance A method for manufacturing an organic thin film transistor element, comprising:
【0012】2.プラズマ処理が、大気圧プラズマ処理
法であることを特徴とする前記1に記載の有機薄膜トラ
ンジスタ素子の製造方法。2. 2. The method for manufacturing an organic thin film transistor element described in 1 above, wherein the plasma treatment is an atmospheric pressure plasma treatment method.
【0013】以下、本発明を詳細に説明する。本発明者
等は、上記記載の問題点を種々検討した結果、請求項1
に記載のように、支持体上に、少なくともゲート電極、
ゲート絶縁層、ソース電極、ドレイン電極、有機半導体
層を有する有機薄膜トランジスタ素子の製造方法におい
て、該有機半導体層と接する部位の表面を予めプラズマ
処理する工程の後、前記有機半導体層を儲ける工程を設
けることにより、素子形成時のチャネル近傍の不純物の
混入や微小なゴミ(パーティクル)の付着を防止するこ
とにより、リーク電流が低減し、且つ、画素欠陥の少な
い有機薄膜トランジスタ素子の製造方法を見出した。The present invention will be described in detail below. The present inventors have made various studies on the problems described above, and as a result, claim 1
At least a gate electrode on the support,
In a method of manufacturing an organic thin film transistor element having a gate insulating layer, a source electrode, a drain electrode, and an organic semiconductor layer, a step of making a profit of the organic semiconductor layer is provided after a step of plasma-treating a surface of a portion in contact with the organic semiconductor layer in advance. As a result, the inventors have found a method for manufacturing an organic thin film transistor element in which the leak current is reduced and the number of pixel defects is small by preventing the mixing of impurities near the channel and the adhesion of minute dust (particles) at the time of element formation.
【0014】[0014]
【発明の実施の形態】以下、本発明について詳しく述べ
る。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below.
【0015】本発明に係る有機薄膜トランジスタ素子の
構成を図1(a)、図1(b)及び図1(c)を各々用
いて説明する。The structure of the organic thin film transistor element according to the present invention will be described with reference to FIGS. 1 (a), 1 (b) and 1 (c).
【0016】図1(a)は、トップゲート型の有機薄膜
トランジスタ素子の一例を示す模式図である。FIG. 1A is a schematic view showing an example of a top gate type organic thin film transistor element.
【0017】図1(a)において、本発明に係るトップ
ゲート型の有機薄膜トランジスタ素子は、支持体7上
に、ソース電極2、ドレイン電極3、前記ソース電極2
と前記ドレイン電極3を連結する有機半導体層4が配設
され、ソース電極2、ドレイン電極3、有機半導体層4
の全体を被覆するように絶縁層6を設け、更に、絶縁層
6上にゲート電極5が配設された構成を有する。In FIG. 1A, the top gate type organic thin film transistor element according to the present invention has a source electrode 2, a drain electrode 3 and the source electrode 2 on a support 7.
And an organic semiconductor layer 4 connecting the drain electrode 3 with the source electrode 2, the drain electrode 3, and the organic semiconductor layer 4.
The insulating layer 6 is provided so as to cover the whole of the above, and the gate electrode 5 is further provided on the insulating layer 6.
【0018】図1(b)、(c)は、各々ボトムゲート
型の有機薄膜トランジスタ素子の一例を示す模式図であ
る。FIGS. 1B and 1C are schematic views showing an example of a bottom gate type organic thin film transistor element.
【0019】図1(b)において、本発明に係るボトム
ゲート型の有機薄膜トランジスタ素子は、支持体7上に
ゲート電極5が配設され、ゲート電極5の全体を被覆す
るように絶縁層6が設けられ、前記絶縁層6の上にソー
ス電極2とドレイン電極3が配設され、更に、ソース電
極2とドレイン電極3とを連結するように有機半導体層
4が設けられる。In FIG. 1B, in the bottom gate type organic thin film transistor element according to the present invention, the gate electrode 5 is provided on the support 7, and the insulating layer 6 is formed so as to cover the entire gate electrode 5. A source electrode 2 and a drain electrode 3 are provided on the insulating layer 6, and an organic semiconductor layer 4 is further provided so as to connect the source electrode 2 and the drain electrode 3.
【0020】図1(c)において、本発明に係るボトム
ゲート型の有機薄膜トランジスタ素子は、支持体7上に
ゲート電極が配設され、ゲート電極5の全体を被覆する
ように絶縁層6、次いで、前記絶縁層6の上に有機半導
体層4を配設した後、ソース電極2とドレイン電極3が
設けられている。In FIG. 1C, in the bottom gate type organic thin film transistor element according to the present invention, a gate electrode is provided on a support 7, and an insulating layer 6 is formed so as to cover the entire gate electrode 5, and then the gate electrode 5. After disposing the organic semiconductor layer 4 on the insulating layer 6, the source electrode 2 and the drain electrode 3 are provided.
【0021】図1(a)〜(c)において、本発明に係
る有機トランジスタ素子1を構成する、各材料について
説明する。1 (a) to 1 (c), each material constituting the organic transistor element 1 according to the present invention will be described.
【0022】《有機半導体層》本発明に係る有機半導体
層は、有機半導体素子において、ソース電極とドレイン
電極を連結する機能を有するが、有機半導体層を形成す
る有機半導体材料としては、π共役系材料が好ましく用
いられる。<< Organic Semiconductor Layer >> The organic semiconductor layer according to the present invention has a function of connecting a source electrode and a drain electrode in an organic semiconductor element, but as an organic semiconductor material forming the organic semiconductor layer, a π-conjugated system is used. Materials are preferably used.
【0023】π共役系材料としては、例えば、ポリピロ
ール、ポリ(N−置換ピロール)、ポリ(3−置換ピロ
ール)、ポリ(3,4−二置換ピロール)などのポリピ
ロール類、ポリチオフェン、ポリ(3−置換チオフェ
ン)、ポリ(3,4−二置換チオフェン)、ポリベンゾ
チオフェンなどのポリチオフェン類、ポリイソチアナフ
テンなどのポリイソチアナフテン類、ポリチエニレンビ
ニレンなどのポリチエニレンビニレン類、ポリ(p−フ
ェニレンビニレン)などのポリ(p−フェニレンビニレ
ン)類、ポリアニリン、ポリ(N−置換アニリン)、ポ
リ(3−置換アニリン)、ポリ(2,3−置換アニリ
ン)などのポリアニリン類、ポリアセチレンなどのポリ
アセチレン類、ポリジアセチレンなどのポリジアセチレ
ン類、ポリアズレンなどのポリアズレン類、ポリピレン
などのポリピレン類、ポリカルバゾール、ポリ(N−置
換カルバゾール)などのポリカルバゾール類、ポリセレ
ノフェンなどのポリセレノフェン類、ポリフラン、ポリ
ベンゾフランなどのポリフラン類、ポリ(p−フェニレ
ン)などのポリ(p−フェニレン)類、ポリインドール
などのポリインドール類、ポリピリダジンなどのポリピ
リダジン類、ナフタセン、ペンタセン、ヘキサセン、ヘ
プタセン、ジベンゾペンタセン、テトラベンゾペンタセ
ン、ピレン、ジベンゾピレン、クリセン、ペリレン、コ
ロネン、テリレン、オバレン、クオテリレン、サーカム
アントラセンなどのポリアセン類およびポリアセン類の
炭素の一部をN、S、Oなどの原子、カルボニル基など
の官能基に置換した誘導体(トリフェノジオキサジン、
トリフェノジチアジン、ヘキサセン−6,15−キノン
など)、ポリビニルカルバゾール、ポリフエニレンスル
フィド、ポリビニレンスルフィドなどのポリマーや特開
平11−195790号に記載された多環縮合体などを
用いることができる。また、これらのポリマーと同じ繰
返し単位を有するたとえばチオフェン6量体であるα−
セクシチオフェン、α,ω−ジヘキシル−α−セクシチ
オフェン、α,ω−ジヘキシル−α−キンケチオフェ
ン、α,ω−ビス(3−ブトキシプロピル)−α−セク
シチオフェン、スチリルベンゼン誘導体などのオリゴマ
ーも好適に用いることができる。さらに銅フタロシアニ
ンや特開平11−251601号に記載のフッ素置換銅
フタロシアニンなどの金属フタロシアニン類、ナフタレ
ン1,4,5,8−テトラカルボン酸ジイミド、N,
N′−ビス(4−トリフルオロメチルベンジル)ナフタ
レン−1,4,5,8−テトラカルボン酸ジイミドとと
もに、N,N′−ビス(1H,1H−ペルフルオロオク
チル)、N,N′−ビス(1H,1H−ペルフルオロブ
チル)及びN,N′−ジオクチルナフタレン−1,4,
5,8−テトラカルボン酸ジイミド誘導体、ナフタレン
−2,3,6,7−テトラカルボン酸ジイミドなどのナ
フタレンテトラカルボン酸ジイミド類、及び、アントラ
セン−2,3,6,7−テトラカルボン酸ジイミドなど
のアントラセンテトラカルボン酸ジイミド類などの縮合
環テトラカルボン酸ジイミド類、C60、C70、C76、C
78、C84等フラーレン類、SWNTなどのカーボンナノ
チューブ、メロシアニン色素類、ヘミシアニン色素類な
どの色素などがあげられる。Examples of the π-conjugated material include polypyrroles such as polypyrrole, poly (N-substituted pyrrole), poly (3-substituted pyrrole), poly (3,4-disubstituted pyrrole), polythiophene and poly (3). -Substituted thiophene), poly (3,4-disubstituted thiophene), polythiophenes such as polybenzothiophene, polyisothianaphthenes such as polyisothianaphthene, polythienylenevinylenes such as polythienylenevinylene, poly ( poly (p-phenylene vinylene) such as p-phenylene vinylene), polyaniline, poly (N-substituted aniline), poly (3-substituted aniline), polyaniline such as poly (2,3-substituted aniline), polyacetylene, etc. Polyacetylenes, polydiacetylenes and other polydiacetylenes, polyazulenes , Polypyrenes such as polypyrene, polycarbazoles such as polycarbazole and poly (N-substituted carbazole), polyselenophenes such as polyselenophene, polyfurans such as polyfuran and polybenzofuran, and poly (p-phenylene) ) Etc., polyindoles such as polyindole, polypyridazines such as polypyridazine, naphthacene, pentacene, hexacene, heptacene, dibenzopentacene, tetrabenzopentacene, pyrene, dibenzopyrene, chrysene, perylene. , Coronene, terylene, ovalene, quaterrylene, circumanthracene, and other polyacenes, and derivatives of polyacene in which some of the carbon atoms are replaced with atoms such as N, S, O, and functional groups such as carbonyl groups (triphenodiene). Oxazine,
Polymers such as triphenodithiazine, hexacene-6,15-quinone), polyvinylcarbazole, polyphenylene sulfide, and polyvinylene sulfide, and polycyclic condensates described in JP-A No. 11-195790 can be used. . In addition, α-, which is, for example, a thiophene hexamer having the same repeating unit as those polymers,
Oligomers such as sexithiophene, α, ω-dihexyl-α-sexithiophene, α, ω-dihexyl-α-kinkethiophene, α, ω-bis (3-butoxypropyl) -α-sexithiophene, and styrylbenzene derivatives are also suitable. Can be used for. Further, metal phthalocyanines such as copper phthalocyanine and fluorine-substituted copper phthalocyanine described in JP-A No. 11-251601, naphthalene 1,4,5,8-tetracarboxylic acid diimide, N,
N'-bis (4-trifluoromethylbenzyl) naphthalene-1,4,5,8-tetracarboxylic acid diimide together with N, N'-bis (1H, 1H-perfluorooctyl), N, N'-bis ( 1H, 1H-perfluorobutyl) and N, N′-dioctylnaphthalene-1,4
Naphthalenetetracarboxylic acid diimides such as 5,8-tetracarboxylic acid diimide derivative and naphthalene-2,3,6,7-tetracarboxylic acid diimide, and anthracene-2,3,6,7-tetracarboxylic acid diimide Condensed ring tetracarboxylic acid diimides such as anthracene tetracarboxylic acid diimides, C 60 , C 70 , C 76 , C
Examples include fullerenes such as 78 and C 84 , carbon nanotubes such as SWNT, and dyes such as merocyanine dyes and hemicyanine dyes.
【0024】これらのπ共役系材料のうちでも、チオフ
ェン、ビニレン、チエニレンビニレン、フェニレンビニ
レン、p−フェニレン、これらの置換体またはこれらの
2種以上を繰返し単位とし、かつ該繰返し単位の数nが
4〜10であるオリゴマー若しくは該繰返し単位の数n
が20以上であるポリマー、ペンタセンなどの縮合多環
芳香族化合物、フラーレン類、縮合環テトラカルボン酸
ジイミド類、金属フタロシアニンよりなる群から選ばれ
た少なくとも1種が好ましい。Among these π-conjugated materials, thiophene, vinylene, thienylenevinylene, phenylenevinylene, p-phenylene, their substitution products or two or more of these repeating units are used as repeating units, and the number of repeating units is n. Is 4 to 10 or the number of repeating units n
Is preferably 20 or more, at least one selected from the group consisting of condensed polycyclic aromatic compounds such as pentacene, fullerenes, condensed ring tetracarboxylic acid diimides, and metal phthalocyanines.
【0025】また、その他の有機半導体材料としては、
テトラチアフルバレン(TTF)−テトラシアノキノジ
メタン(TCNQ)錯体、ビスエチレンテトラチアフル
バレン(BEDTTTF)−過塩素酸錯体、BEDTT
TF−ヨウ素錯体、TCNQ−ヨウ素錯体、などの有機
分子錯体も用いることができる。さらにポリシラン、ポ
リゲルマンなどのσ共役系ポリマーや特開2000−2
60999に記載の有機・無機混成材料等も用いること
ができる。As other organic semiconductor materials,
Tetrathiafulvalene (TTF) -Tetracyanoquinodimethane (TCNQ) complex, Bisethylenetetrathiafulvalene (BEDTTTF) -Perchloric acid complex, BEDTT
Organic molecular complexes such as TF-iodine complex and TCNQ-iodine complex can also be used. Further, σ-conjugated polymers such as polysilane and polygermane, and JP-A-2000-2
The organic / inorganic hybrid material described in 60999 can also be used.
【0026】本発明においては、有機半導体層に、例え
ば、アクリル酸、アセトアミド、ジメチルアミノ基、シ
アノ基、カルボキシル基、ニトロ基などの官能基を有す
る材料や、ベンゾキノン誘導体、テトラシアノエチレン
およびテトラシアノキノジメタンやそれらの誘導体など
のように電子を受容するアクセプターとなる材料や、例
えば、アミノ基、トリフェニル基、アルキル基、水酸
基、アルコキシ基、フェニル基などの官能基を有する材
料、フェニレンジアミンなどの置換アミン類、アントラ
セン、ベンゾアントラセン、置換ベンゾアントラセン
類、ピレン、置換ピレン、カルバゾールおよびその誘導
体、テトラチアフルバレンとその誘導体などのように電
子の供与体であるドナーとなるような材料を含有させ、
いわゆるドーピング処理を施してもよい。In the present invention, a material having a functional group such as acrylic acid, acetamide, dimethylamino group, cyano group, carboxyl group or nitro group in the organic semiconductor layer, benzoquinone derivative, tetracyanoethylene and tetracyano Materials such as quinodimethane and their derivatives that serve as acceptors for accepting electrons, materials having functional groups such as amino groups, triphenyl groups, alkyl groups, hydroxyl groups, alkoxy groups, phenyl groups, and phenylenediamine Substituted amines such as, anthracene, benzoanthracene, substituted benzanthracenes, pyrene, substituted pyrene, carbazole and its derivatives, tetrathiafulvalene and its derivatives, etc. Let
A so-called doping process may be performed.
【0027】前記ドーピングとは電子受容性分子(アク
セプター)または電子供与性分子(ドナー)をドーパン
トとして該有機半導体層薄膜に導入することを意味す
る。従って,ドーピングが施された薄膜は、前記の縮合
多環芳香族化合物とドーパントを含有する薄膜である。
本発明に用いるドーパントとしてアクセプター、ドナー
のいずれも使用可能である。このアクセプターとしてC
l2、Br2、I2、ICl、ICl3、IBr、IFなど
のハロゲン、PF5、AsF5、SbF5、BF3、BCl
3、BBr3、SO3などのルイス酸、HF、HC1、H
NO3、H2SO4、HClO4、FSO3H、ClSO
3H、CF3SO3Hなどのプロトン酸、酢酸、蟻酸、ア
ミノ酸などの有機酸、FeCl3、FeOCl、TiC
l4、ZrCl 4、HfCl4、NbF5、NbCl5、T
aCl5、MoCl5、WF5、WCl6、UF6、LnC
l3(Ln=La、Ce、Nd、Pr、などのランタノ
イドとY)などの遷移金属化合物、Cl-、Br-、
I-、ClO4 -、PF6 -、AsF5 -、SbF6 -、B
F4 -、スルホン酸アニオンなどの電解質アニオンなどを
挙げることができる。またドナーとしては、Li、N
a、K、Rb、Csなどのアルカリ金属、Ca、Sr、
Baなどのアルカリ土類金属、Y、La、Ce、Pr、
Nd、Sm、Eu、Gd、Tb、Dy、Ho、Er、Y
bなどの希土類金属、アンモニウムイオン、R4P+、R
4As+、R3S+、アセチルコリンなどをあげることがで
きる。これらのドーパントのドーピングの方法として予
め有機半導体の薄膜を作製しておき、ドーパントを後で
導入する方法、有機半導体の薄膜作製時にドーパントを
導入する方法のいずれも使用可能である。前者の方法と
して、ガス状態のドーパントを用いる気相ドーピング、
溶液あるいは液体のドーパントを該薄膜に接触させてド
ーピングする液相ドーピング、固体状態のドーパントを
該薄膜に接触させてドーパントを拡散ドーピングする固
相ドーピングの方法をあげることができる。また液相ド
ーピングにおいては電解を施すことによってドーピング
の効率を調整することができる。後者の方法では、有機
半導体材料とドーパントの混合溶液あるいは分散液を同
時に塗布、乾燥してもよい。例えば、真空蒸着法を用い
る場合、有機半導体材料とともにドーパントを共蒸着す
ることによりドーパントを導入することができる。また
スパッタリング法で薄膜を作製する場合、有機半導体材
料とドーパントの二元ターゲットを用いてスパッタリン
グして薄膜中にドーパントを導入させることができる。
さらに他の方法として、電気化学的ドーピング、光開始
ドーピング等の化学的ドーピングおよび例えば刊行物
(工業材料、34巻、第4号、55頁、1986年)に
示されたイオン注入法等の物理的ドーピングの何れも使
用可能である。The doping is an electron-accepting molecule (activator).
Dopant with scepter) or electron donating molecule (donor)
Means to be introduced into the thin film of the organic semiconductor layer as
It Therefore, the doped thin film is
It is a thin film containing a polycyclic aromatic compound and a dopant.
Acceptor and donor as dopants used in the present invention
Any of these can be used. C as this acceptor
l2, Br2, I2, ICl, ICl3, IBr, IF, etc.
Halogen, PFFive, AsFFive, SbFFive, BF3, BCl
3, BBr3, SO3Lewis acids such as HF, HC1, H
NO3, H2SOFour, HClOFour, FSO3H, ClSO
3H, CF3SO3Proton acids such as H, acetic acid, formic acid,
Organic acids such as mino acids, FeCl3, FeOCl, TiC
lFour, ZrCl Four, HfClFour, NbFFive, NbClFive, T
aClFive, MoClFive, WFFive, WCl6, UF6, LnC
l3(Ln = La, Ce, Nd, Pr, etc.
And transition metal compounds such as Y), Cl-, Br-,
I-, ClOFour -, PF6 -, AsFFive -, SbF6 -, B
FFour -, Electrolyte anions such as sulfonate anions
Can be mentioned. Further, as a donor, Li, N
Alkali metals such as a, K, Rb, Cs, Ca, Sr,
Alkaline earth metals such as Ba, Y, La, Ce, Pr,
Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Y
rare earth metal such as b, ammonium ion, RFourP+, R
FourAs+, R3S+, Acetylcholine, etc.
Wear. As a method of doping these dopants,
Thin film of organic semiconductor for
Introducing method, Dopant during thin film formation of organic semiconductor
Any of the methods of introduction can be used. With the former method
And vapor phase doping using a gaseous dopant,
A solution or liquid dopant is brought into contact with the thin film to
Liquid phase doping, solid state dopant
A solid material for diffusively doping a dopant by contacting the thin film.
The method of phase doping can be mentioned. Liquid phase
Doping by applying electrolysis
The efficiency of can be adjusted. The latter method is organic
Use the same mixed solution or dispersion of semiconductor material and dopant.
It may be applied and dried at times. For example, using the vacuum deposition method
Co-evaporate dopant with organic semiconductor material
By doing so, the dopant can be introduced. Also
When forming a thin film by the sputtering method, an organic semiconductor material
Sputtering using a dual target of dopant and dopant
The dopant can be introduced into the thin film.
Still other methods include electrochemical doping, photoinitiation
Chemical doping such as doping and publications for example
(Industrial Materials, Vol. 34, No. 4, p. 55, 1986)
Use any of the physical doping techniques shown, such as ion implantation.
It can be used.
【0028】(有機半導体層の作製方法)これら有機半
導体の薄膜の作製法としては、真空蒸着法、分子線エピ
タキシャル成長法、イオンクラスタービーム法、低エネ
ルギーイオンビーム法、イオンプレーティング法、CV
D法、スパッタリング法、プラズマ重合法、電解重合
法、化学重合法、スプレーコート法、スピンコート法、
ブレードコート法、ディップコート法、キャスト法、ロ
ールコート法、バーコート法、ダイコート法およびLB
法等が挙げられ、材料に応じて使用できる。ただし、こ
の中で生産性の点で、有機半導体材料の溶液をもちいて
簡単かつ精密に薄膜が形成できるスピンコート法、ブレ
ードコート法、ディップコート法、ロールコート法、バ
ーコート法、ダイコート法等が好ましい。(Method for Producing Organic Semiconductor Layer) As a method for producing a thin film of these organic semiconductors, vacuum vapor deposition method, molecular beam epitaxial growth method, ion cluster beam method, low energy ion beam method, ion plating method, CV
D method, sputtering method, plasma polymerization method, electrolytic polymerization method, chemical polymerization method, spray coating method, spin coating method,
Blade coating method, dip coating method, casting method, roll coating method, bar coating method, die coating method and LB
Method, etc., and can be used depending on the material. However, among these, from the viewpoint of productivity, spin coating, blade coating, dip coating, roll coating, bar coating, die coating, etc. can be used to easily and precisely form a thin film using a solution of an organic semiconductor material. Is preferred.
【0029】(有機半導体層の膜厚)これら有機半導体
からなる薄膜の膜厚としては、特に制限はないが、得ら
れたトランジスタの特性は有機半導体からなる活性層の
膜厚に大きく左右される場合が多く、その膜厚は、有機
半導体により異なるが、1μm以下が好ましく、特に好
ましくは、10nm〜300nmの範囲である。(Film Thickness of Organic Semiconductor Layer) The film thickness of the thin film made of these organic semiconductors is not particularly limited, but the characteristics of the obtained transistor are greatly influenced by the film thickness of the active layer made of the organic semiconductor. In many cases, the film thickness varies depending on the organic semiconductor, but is preferably 1 μm or less, particularly preferably in the range of 10 nm to 300 nm.
【0030】《ゲート電極、ソース電極、ドレイン電
極》本発明に係る、ゲート電極、ソース電極、ドレイン
電極について説明する。<< Gate Electrode, Source Electrode, Drain Electrode >> The gate electrode, source electrode, and drain electrode according to the present invention will be described.
【0031】ソース電極、ドレイン電極及びゲート電極
は、導電性材料であれば特に限定されず、白金、金、
銀、ニッケル、クロム、銅、鉄、錫、アンチモン鉛、タ
ンタル、インジウム、パラジウム、テルル、レニウム、
イリジウム、アルミニウム、ルテニウム、ゲルマニウ
ム、モリブデン、タングステン、酸化スズ・アンチモ
ン、酸化インジウム・スズ(ITO)、フッ素ドープ酸
化亜鉛、亜鉛、炭素、グラファイト、グラッシーカーボ
ン、銀ペーストおよびカーボンペースト、リチウム、ベ
リリウム、ナトリウム、マグネシウム、カリウム、カル
シウム、スカンジウム、チタン、マンガン、ジルコニウ
ム、ガリウム、ニオブ、ナトリウム、ナトリウム−カリ
ウム合金、マグネシウム、リチウム、アルミニウム、マ
グネシウム/銅混合物、マグネシウム/銀混合物、マグ
ネシウム/アルミニウム混合物、マグネシウム/インジ
ウム混合物、アルミニウム/酸化アルミニウム混合物、
リチウム/アルミニウム混合物等が用いられるが、特
に、白金、金、銀、銅、アルミニウム、インジウム、I
TOおよび炭素が好ましい。The source electrode, drain electrode and gate electrode are not particularly limited as long as they are conductive materials, and platinum, gold,
Silver, nickel, chromium, copper, iron, tin, antimony lead, tantalum, indium, palladium, tellurium, rhenium,
Iridium, aluminum, ruthenium, germanium, molybdenum, tungsten, tin antimony oxide, indium tin oxide (ITO), fluorine-doped zinc oxide, zinc, carbon, graphite, glassy carbon, silver paste and carbon paste, lithium, beryllium, sodium , Magnesium, potassium, calcium, scandium, titanium, manganese, zirconium, gallium, niobium, sodium, sodium-potassium alloy, magnesium, lithium, aluminum, magnesium / copper mixture, magnesium / silver mixture, magnesium / aluminum mixture, magnesium / indium. Mixture, aluminum / aluminum oxide mixture,
A lithium / aluminum mixture or the like is used, but in particular platinum, gold, silver, copper, aluminum, indium, I
TO and carbon are preferred.
【0032】また、ドーピング等で導電率を向上させた
公知の導電性ポリマー、例えば導電性ポリアニリン、導
電性ポリピロール、導電性ポリチオフェン、ポリエチレ
ンジオキシチオフェンとポリスチレンスルホン酸の錯体
なども好適に用いられる。Further, a known conductive polymer whose conductivity is improved by doping or the like, such as conductive polyaniline, conductive polypyrrole, conductive polythiophene, or a complex of polyethylenedioxythiophene and polystyrenesulfonic acid, is also preferably used.
【0033】本発明に係る、ソース電極、ドレイン電極
は、上に挙げた中でも半導体層との接触面において電気
抵抗が少ないものが好ましい。Among the source electrodes and the drain electrodes according to the present invention, those having a small electric resistance at the contact surface with the semiconductor layer are preferable among the above.
【0034】(電極の形成方法)電極の形成方法として
は、上記記載の導電性材料を原料として蒸着やスパッタ
リング等の方法を用いて形成した導電性薄膜を、公知の
フォトリソグラフ法やリフトオフ法を用いて電極形成す
る方法、アルミニウムや銅などの金属箔上に熱転写、イ
ンクジェット等によるレジストを用いてエッチングする
方法がある。(Method for forming electrode) As a method for forming an electrode, a conductive thin film formed by using the above-mentioned conductive material as a raw material by a method such as vapor deposition or sputtering is subjected to a known photolithography method or lift-off method. There are a method of forming an electrode by using it, a method of thermal transfer on a metal foil such as aluminum or copper, and a method of etching using a resist such as an inkjet.
【0035】また、導電性ポリマーの溶液あるいは分散
液、導電性微粒子分散液を直接インクジェットによりパ
ターニングしてもよいし、塗工膜からリソグラフやレー
ザーアブレーションなどにより形成してもよい。さらに
導電性ポリマーや導電性微粒子を含むインク、導電性ペ
ーストなどを凸版、凹版、平版、スクリーン印刷などの
印刷法でパターニングする方法も用いることができる。The conductive polymer solution or dispersion or the conductive fine particle dispersion may be directly patterned by ink jet, or may be formed from a coating film by lithography or laser ablation. Further, a method of patterning an ink containing a conductive polymer or conductive fine particles, a conductive paste or the like by a printing method such as letterpress, intaglio, planographic printing or screen printing can also be used.
【0036】上記導電性微粒子としては、粒子径が1n
m〜50nm好ましくは1nm〜10nmの白金、金、
銀、ニッケル、クロム、銅、鉄、錫、タンタル、インジ
ウム、コバルト、パラジウム、テルル、レニウム、イリ
ジウム、アルミニウム、ルテニウム、ゲルマニウム、モ
リブデン、タングステン、亜鉛、等を用いることができ
るが、特に好ましくは、仕事関数が4.5eV以上の白
金、金、銀、銅、コバルト、クロム、イリジウム、ニッ
ケル、パラジウム、モリブデン、タングステン等の金属
微粒子が挙げられる。The conductive fine particles have a particle size of 1 n.
m-50 nm, preferably 1 nm-10 nm platinum, gold,
Silver, nickel, chromium, copper, iron, tin, tantalum, indium, cobalt, palladium, tellurium, rhenium, iridium, aluminum, ruthenium, germanium, molybdenum, tungsten, zinc, etc. can be used, but particularly preferably, Examples thereof include fine metal particles having a work function of 4.5 eV or more, such as platinum, gold, silver, copper, cobalt, chromium, iridium, nickel, palladium, molybdenum, and tungsten.
【0037】このような金属微粒子分散液の製造方法と
して、ガス中蒸発法、スパッタリング法、金属蒸気合成
法などの物理的生成法や、コロイド法、共沈法などの、
液相で金属イオンを還元して金属微粒子を生成する化学
的生成法が挙げられるが、好ましくは、特開平11−7
6800、同11−80647、同319538、特開
2000−239853などに示されたコロイド法、特
開2001−254185、特開2001−5302
8、特開2001−35814、特開2001−352
55、特開2000−124157、特開2000−1
23634などに記載されたガス中蒸発法により製造さ
れた分散物である。これらの分散物を、塗設し電極パタ
ーン状に成型した後、溶媒を乾燥させ、さらに100℃
〜300℃、好ましくは150℃〜200℃の範囲で熱
処理することにより、金属微粒子を熱融着させることで
電極形成することが出来る。As a method for producing such a metal fine particle dispersion, a physical production method such as an in-gas evaporation method, a sputtering method, a metal vapor synthesis method, a colloid method, a coprecipitation method or the like can be used.
A chemical production method of producing metal fine particles by reducing metal ions in a liquid phase can be mentioned, and preferably, JP-A No. 11-7.
No. 6800, No. 11-80647, No. 319538, the colloid method shown in JP-A-2000-239853, JP-A-2001-254185, and JP-A-2001-5302.
8, JP 2001-35814A, JP 2001-352A
55, JP 2000-124157, JP 2000-1.
It is a dispersion produced by the gas evaporation method described in 23634. After coating these dispersions and molding them into an electrode pattern, the solvent is dried and the temperature is raised to 100 ° C.
The electrode can be formed by heat-sealing the metal fine particles by heat treatment in the range of 300 to 300 ° C., preferably 150 to 200 ° C.
【0038】(ソース電極、ドレイン電極の作製)本発
明に係るソース電極、ドレイン電極の作製、を図2、図
3を用いて説明する。図2の工程(1)〜(3)、図3
の工程(c)〜(e)で示されているように、電極膜の
切削により形成された間隙を有機半導体層で連結し、ソ
ース電極及びドレイン電極が構成される。(Production of Source Electrode and Drain Electrode) Production of the source electrode and the drain electrode according to the present invention will be described with reference to FIGS. Steps (1) to (3) of FIG. 2 and FIG.
As shown in steps (c) to (e), the gaps formed by cutting the electrode film are connected by the organic semiconductor layer to form the source electrode and the drain electrode.
【0039】ここで、電極膜を切削する方法としては、
レーザアブレーション法、ダイシングソー、ダイアモン
ドブレード、または、ダイアモンドニードルによる加工
等が挙げられる。Here, as a method of cutting the electrode film,
Examples thereof include laser ablation method, dicing saw, diamond blade, and diamond needle processing.
【0040】切削加工用のレーザとしては、ルビーレー
ザ、ガラスレーザ、YAGレーザ、GaAlAsやIn
GaAsP等の半導体レーザ、ArF、KrF、XeC
l、XeF等のエキシマレーザ、炭酸ガスレーザ、Ar
イオンレーザ等が挙げられるが、中でも、エキシマレー
ザが好ましく、特に好ましく用いられるのは、KrFエ
キシマレーザである。As a laser for cutting, a ruby laser, a glass laser, a YAG laser, GaAlAs or In
Semiconductor laser such as GaAsP, ArF, KrF, XeC
1, excimer laser such as XeF, carbon dioxide laser, Ar
Examples thereof include ion lasers, and among them, excimer lasers are preferable, and KrF excimer lasers are particularly preferably used.
【0041】例えば、エキシマレーザによるアブレーシ
ョン法は、常温常圧で、短時間にミクロンオーダーの精
度の、熱歪みやバリの無い穴や溝を形成できる。またマ
スクを通してエキシマレーザ光を被加工物(ワーク)に
照射すれば、マスクパターンを転写して任意の形状の穴
や溝を形成できる。エキシマレーザはパルスとして発振
され、材料を1パルスで約0.01μm〜0.5μm除
去できるので、パルス数で除去する深さを正確に制御で
きる。For example, the ablation method using an excimer laser can form holes and grooves free from thermal distortion and burrs and having micron order accuracy in a short time at room temperature and atmospheric pressure. Further, by irradiating the work (work) with the excimer laser light through the mask, the mask pattern can be transferred to form holes or grooves of any shape. The excimer laser is oscillated as a pulse, and the material can be removed by about 0.01 μm to 0.5 μm in one pulse, so that the depth of removal can be accurately controlled by the number of pulses.
【0042】《絶縁層》本発明に係る絶縁層について説
明する。<< Insulating Layer >> The insulating layer according to the present invention will be described.
【0043】絶縁層としては、種々の絶縁膜を用いるこ
とができるが、特に、比誘電率の高い無機酸化物皮膜が
好ましい。無機酸化物としては、酸化ケイ素、酸化アル
ミニウム、酸化タンタル、酸化チタン、酸化スズ、酸化
バナジウム、チタン酸バリウムストロンチウム、ジルコ
ニウム酸チタン酸バリウム、ジルコニウム酸チタン酸
鉛、チタン酸鉛ランタン、チタン酸ストロンチウム、チ
タン酸バリウム、フッ化バリウムマグネシウム、チタン
酸ビスマス、チタン酸ストロンチウムビスマス、タンタ
ル酸ストロンチウムビスマス、タンタル酸ニオブ酸ビス
マス、トリオキサイドイットリウムなどが挙げられる。
それらのうち好ましいのは、酸化ケイ素、酸化アルミニ
ウム、酸化タンタル、酸化チタンである。窒化ケイ素、
窒化アルミニウムなどの無機窒化物も好適に用いること
ができる。Although various insulating films can be used as the insulating layer, an inorganic oxide film having a high relative dielectric constant is particularly preferable. As the inorganic oxide, silicon oxide, aluminum oxide, tantalum oxide, titanium oxide, tin oxide, vanadium oxide, barium strontium titanate, barium zirconate titanate, lead zirconate titanate, lead lanthanum titanate, strontium titanate, Examples thereof include barium titanate, barium magnesium fluoride, bismuth titanate, strontium bismuth titanate, strontium bismuth tantalate, bismuth tantalate niobate, and yttrium trioxide.
Of these, preferred are silicon oxide, aluminum oxide, tantalum oxide, and titanium oxide. Silicon nitride,
Inorganic nitrides such as aluminum nitride can also be preferably used.
【0044】(絶縁層の形成方法)上記皮膜の形成方法
としては、真空蒸着法、分子線エピタキシャル成長法、
イオンクラスタービーム法、低エネルギーイオンビーム
法、イオンプレーティング法、CVD法、スパッタリン
グ法、大気圧プラズマ法などのドライプロセスや、スプ
レーコート法、スピンコート法、ブレードコート法、デ
イップコート法、キャスト法、ロールコート法、バーコ
ート法、ダイコート法などの塗布による方法、印刷やイ
ンクジェットなどのパターニングによる方法などのウェ
ットプロセスが挙げられ、材料に応じて使用できる。(Method for forming insulating layer) As the method for forming the above film, a vacuum vapor deposition method, a molecular beam epitaxial growth method,
Dry process such as ion cluster beam method, low energy ion beam method, ion plating method, CVD method, sputtering method, atmospheric pressure plasma method, spray coating method, spin coating method, blade coating method, dip coating method, casting method A wet process such as a coating method such as a roll coating method, a bar coating method, a die coating method, a patterning method such as printing or inkjet, and the like can be used depending on the material.
【0045】ウェットプロセスは、無機酸化物の微粒子
を、任意の有機溶剤あるいは水に必要に応じて界面活性
剤などの分散補助剤を用いて分散した液を塗布、乾燥す
る方法や、酸化物前駆体、例えばアルコキシド体の溶液
を塗布、乾燥する、いわゆるゾルゲル法が用いられる。The wet process is carried out by coating and drying a liquid in which fine particles of an inorganic oxide are dispersed in an arbitrary organic solvent or water using a dispersion auxiliary agent such as a surfactant, if necessary, or an oxide precursor. A so-called sol-gel method is used in which a solution of a body, for example, an alkoxide body is applied and dried.
【0046】上記記載の皮膜の形成方法の中でも好まし
いのは、大気圧プラズマ法とゾルゲル法である。Among the methods for forming the film described above, the atmospheric pressure plasma method and the sol-gel method are preferable.
【0047】大気圧下でのプラズマ製膜処理による絶縁
膜の形成方法については以下にように説明される。即
ち、上記大気圧下でのプラズマ製膜処理とは、大気圧ま
たは大気圧近傍の圧力下で放電し、反応性ガスをプラズ
マ励起し、基材上に薄膜を形成する処理を指し、その方
法については特開平11−133205号、特開200
0−185362、特開平11−61406号、特開2
000−147209、同2000−121804に記
載されている(以下、大気圧プラズマ法とも称する)。
大気圧下でのプラズマ製膜処理により、高機能性の薄膜
を、生産性高く形成することができる。The method of forming the insulating film by the plasma film forming process under the atmospheric pressure will be described below. That is, the plasma film forming process under the atmospheric pressure refers to a process of discharging under the atmospheric pressure or a pressure in the vicinity of the atmospheric pressure, plasma-exciting the reactive gas, and forming a thin film on the substrate. For details, see JP-A-11-133205 and JP-A-200
0-185362, JP-A-11-61406, JP-A-2
000-147209 and 2000-121804 (hereinafter, also referred to as atmospheric pressure plasma method).
By the plasma film forming process under atmospheric pressure, a highly functional thin film can be formed with high productivity.
【0048】また、有機化合物皮膜としては、ポリイミ
ド、ポリアミド、ポリエステル、ポリアクリレート、光
ラジカル重合系、光カチオン重合系の光硬化性樹脂、あ
るいはアクリロニトリル成分を含有する共重合体、ポリ
ビニルフェノール、ポリビニルアルコール、ノボラック
樹脂、及び、シアノエチルプルラン、ポリマー体、エラ
ストマー体を含むホスファゼン化合物、等を用いること
もできる。As the organic compound film, polyimide, polyamide, polyester, polyacrylate, photoradical polymerization type, photocationic polymerization type photocurable resin, or copolymer containing an acrylonitrile component, polyvinylphenol, polyvinyl alcohol. , Novolak resins, phosphazene compounds including cyanoethyl pullulan, polymers and elastomers can also be used.
【0049】有機化合物皮膜の形成法としては、前記ウ
ェットプロセスが好ましい。無機酸化物皮膜と有機酸化
物皮膜は積層して併用することができる。The above-mentioned wet process is preferable as the method for forming the organic compound film. The inorganic oxide film and the organic oxide film can be laminated and used together.
【0050】(絶縁層の厚さ)絶縁膜の膜厚としては、
50nm〜3μmの範囲が好ましく、更に好ましくは、
100nm〜1μmである。(Thickness of Insulating Layer) As the thickness of the insulating film,
The range of 50 nm to 3 μm is preferable, and more preferably,
It is 100 nm to 1 μm.
【0051】(支持体)本発明に係る支持体について説
明する。(Support) The support according to the present invention will be described.
【0052】支持体としては、高分子フィルムを用いる
ことが好ましく、例えばポリエチレンテレフタレート
(PET)、ポリエチレンナフタレート(PEN)、ポ
リエーテルスルホン(PES)、ポリエーテルイミド、
ポリエーテルエーテルケトン、ポリフェニレンスルフィ
ド、ポリアリレート、ポリイミド、ポリカーボネート
(PC)、セルローストリアセテート(TAC)、セル
ロースアセテートプロピオネート(CAP)等からなる
フィルム等が挙げられる。As the support, it is preferable to use a polymer film, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), polyether imide,
Examples thereof include films made of polyether ether ketone, polyphenylene sulfide, polyarylate, polyimide, polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP) and the like.
【0053】これらの高分子フィルムには、トリオクチ
ルホスフェートやジブチルフタレート等の可塑剤を添加
してもよく、ベンゾトリアゾール系やベンゾフェノン系
等の公知の紫外線吸収剤を添加してもよい。また、テト
ラエトキシシラン等の無機高分子の原料を添加し、化学
触媒や熱、光等のエネルギーを付与することにより高分
子量化する、いわゆる有機−無機ポリマーハイブリッド
法を適用して作製した樹脂を原料として用いることもで
きる。A plasticizer such as trioctyl phosphate or dibutyl phthalate may be added to these polymer films, or a known ultraviolet absorber such as benzotriazole or benzophenone may be added. In addition, a resin produced by applying a so-called organic-inorganic polymer hybrid method, in which a raw material of an inorganic polymer such as tetraethoxysilane is added, and a high molecular weight is obtained by applying energy such as a chemical catalyst, heat, or light. It can also be used as a raw material.
【0054】《有機薄膜トランジスタ素子の製造方法》
本発明の有機薄膜トランジスタ素子の製造方法を図2、
図3により説明する。<< Method of Manufacturing Organic Thin Film Transistor Element >>
2, a method for manufacturing an organic thin film transistor element of the present invention,
This will be described with reference to FIG.
【0055】図2は、図1(a)に示したトップゲート
型の有機薄膜トランジスタ素子の製造工程を説明する図
である。FIG. 2 is a view for explaining the manufacturing process of the top gate type organic thin film transistor element shown in FIG. 1 (a).
【0056】図2では、下記の工程(1)〜(5)によ
り有機薄膜トランジスタ素子が製造される。In FIG. 2, the organic thin film transistor element is manufactured by the following steps (1) to (5).
【0057】工程(1):支持体7上に電極膜8を形成
する。電極膜8はフォトリソグラフィー法、蒸着、スパ
ッタリングによる形成でも、電極物質のペーストのパタ
ーニングによる形成でもよく、金属箔などを貼り付けて
形成することもできる。Step (1): The electrode film 8 is formed on the support 7. The electrode film 8 may be formed by a photolithography method, vapor deposition, or sputtering, or may be formed by patterning a paste of an electrode material, or may be formed by attaching a metal foil or the like.
【0058】工程(2):次いで形成した電極膜8を、
例えばKrFエキシマレーザやダイシングソーを用いて
切削し、ソース電極2、ドレイン電極3を形成し、次い
で、後述する、プラズマ処理を行い、支持体7と切削さ
れた電極膜の表面近傍部位に存在する微小なゴミ(パー
ティクル)や不純物を除去する。Step (2): Next, the electrode film 8 formed is
For example, a source electrode 2 and a drain electrode 3 are formed by cutting using a KrF excimer laser or a dicing saw, and then plasma treatment, which will be described later, is performed to exist in the vicinity of the surface of the support 7 and the cut electrode film. Removes minute dust (particles) and impurities.
【0059】工程(3);フォトリソグラフィー法、イ
ンクジェット法等を用いて、有機半導体層4を形成す
る。Step (3): The organic semiconductor layer 4 is formed by using a photolithography method, an ink jet method or the like.
【0060】工程(4):上記記載のプラズマ成膜処理
により、絶縁層6を形成する。但し、工程(4)で用い
られるプラズマ成膜処理は、無機酸化物等の材料をプラ
ズマ状態の反応性ガスとして用いて絶縁層6を形成する
物であり、工程(2)で用いられるような、ゴミ(パー
ティクル)や不純物を除去するプラズマ処理とは異なる
処理である。Step (4): The insulating layer 6 is formed by the plasma film forming process described above. However, the plasma film forming process used in the step (4) is a step of forming the insulating layer 6 by using a material such as an inorganic oxide as a reactive gas in a plasma state, and is the same as that used in the step (2). This is a process different from the plasma process for removing dust (particles) and impurities.
【0061】工程(5):絶縁層6の上に電極膜8の形
成と同様な方法でゲート電極5を形成して、トップゲー
ト型の有機薄膜トランジスタ素子が形成される。Step (5): The gate electrode 5 is formed on the insulating layer 6 in the same manner as the formation of the electrode film 8 to form a top gate type organic thin film transistor element.
【0062】図3は、図1(b)に示したボトムゲート
型の有機薄膜トランジスタ素子の製造工程を説明する図
である。FIG. 3 is a diagram for explaining a manufacturing process of the bottom gate type organic thin film transistor element shown in FIG. 1 (b).
【0063】図3では、下記の工程(a)〜(e)によ
り有機薄膜トランジスタ素子が製造される。In FIG. 3, the organic thin film transistor element is manufactured by the following steps (a) to (e).
【0064】工程(a):支持体7上に、上記記載の工
程(1)に記載と同様の方法を用いて、ゲート電極5を
配設する。Step (a): The gate electrode 5 is provided on the support 7 in the same manner as in the step (1) described above.
【0065】工程(b):前記ゲート電極5を絶縁層6
で被覆処理を行う。ここで、絶縁層6の形成には、上記
工程(4)に記載のプラズマ成膜処理等を同様に適用す
ることができる。Step (b): The gate electrode 5 is formed on the insulating layer 6
Coating treatment is performed. Here, for forming the insulating layer 6, the plasma film forming process or the like described in the step (4) can be similarly applied.
【0066】工程(c):絶縁層6上に、上記記載の工
程(1)と同様にして電極膜8を形成する。Step (c): The electrode film 8 is formed on the insulating layer 6 in the same manner as in the step (1) described above.
【0067】工程(d):上記記載の工程(2)と同様
にして、電極膜8を切削処理し、ついで、プラズマ処理
により絶縁層6とソース電極2、ドレイン電極3の表面
近傍部位のゴミ(パーティクル)や不純物を除去する。Step (d): In the same manner as in the above-mentioned step (2), the electrode film 8 is cut, and then plasma treatment is performed to remove dust on the insulating layer 6, the source electrode 2 and the drain electrode 3 near the surface thereof. (Particles) and impurities are removed.
【0068】工程(e):ソース電極2とドレイン電極
3との間に有機半導体層4を形成し、ボトムゲート型の
有機薄膜トランジスタ素子が形成される。Step (e): The organic semiconductor layer 4 is formed between the source electrode 2 and the drain electrode 3 to form a bottom gate type organic thin film transistor element.
【0069】《プラズマ処理工程:エッチング処理工程
ともいう》図2の工程(2)、図3の工程(d)で各々
示した、有機半導体層4と接する部位(例えば、支持体
7、ソース電極2、ドレイン電極3、絶縁層6等)の表
面を予めプラズマ処理して、ゴミ(パーティクル)や不
純物を除去する工程では、プラズマ放電状態にした不活
性ガスまたは反応性ガスを用いて前記部位のエッチング
処理(具体的には、ゴミや不純物の除去)が行われる。<< Plasma Treatment Step: Also referred to as Etching Treatment Step >> The portions in contact with the organic semiconductor layer 4 shown in the step (2) of FIG. 2 and the step (d) of FIG. 3 (for example, the support 7 and the source electrode). (2, drain electrode 3, insulating layer 6, etc.) is subjected to a plasma treatment in advance to remove dust (particles) and impurities, an inert gas or a reactive gas in a plasma discharge state is used to remove the above-mentioned components. Etching processing (specifically, removal of dust and impurities) is performed.
【0070】ここで、エッチング処理に用いられる、プ
ラズマ放電状態で用いる不活性ガスとしては、希ガスの
ヘリウム、アルゴン等が挙げられ、プラズマ放電状態で
用いる反応性ガスとしては、テトラフルオロメタンや酸
素等が好ましく用いられ、中でも、酸素が好ましく用い
られる。Here, examples of the inert gas used in the plasma discharge state used for the etching treatment include rare gases such as helium and argon, and examples of the reactive gas used in the plasma discharge state include tetrafluoromethane and oxygen. Etc. are preferably used, and among them, oxygen is preferably used.
【0071】ここで、酸素をエッチング処理に用いる場
合(酸素単独での使用〜酸素とその他の不活性ガスとの
混合での使用も含めて)、酸素プラズマ処理法ともい
う。Here, when oxygen is used for etching treatment (including use of oxygen alone to use of mixture of oxygen and other inert gas), it is also called oxygen plasma treatment method.
【0072】また、エッチング処理においては、上記記
載の不活性ガスや反応性ガスをエッチング処理の程度に
応じて、適切な混合比を選択することが好ましい。In the etching process, it is preferable to select an appropriate mixing ratio of the above-mentioned inert gas or reactive gas according to the degree of the etching process.
【0073】本発明に係る大気圧プラズマ処理法とは、
上記の放電プラズマ処理が大気圧または大気圧近傍で行
われることであるが、ここで、大気圧近傍とは、20k
Pa〜110kPaの圧力を表すが、本発明に記載の効
果を好ましく得るためには、93kPa〜104kPa
が好ましい。The atmospheric pressure plasma processing method according to the present invention is
The above-mentioned discharge plasma treatment is performed at or near atmospheric pressure. Here, near atmospheric pressure means 20 k.
It represents a pressure of Pa to 110 kPa, but in order to obtain the effect described in the present invention preferably, it is 93 kPa to 104 kPa.
Is preferred.
【0074】《プラズマ放電処理装置》プラズマ放電処
理に用いられるプラズマ放電処理装置を図4、図5を用
いて説明する。<< Plasma Discharge Treatment Device >> A plasma discharge treatment device used for plasma discharge treatment will be described with reference to FIGS.
【0075】本発明に用いられるプラズマ放電処理装置
は、後述する図4に示すようなプラズマ放電処理容器を
具備し、アース電極であるロール電極と、対向する位置
に配置された印加電極である固定電極との間で放電さ
せ、当該電極間に、不活性ガスまたは反応性ガスを導入
してプラズマ状態とし、前記ロール電極に巻回された、
有機薄膜トランジスタ素子作製用の基板材料(本願で
は、有機半導体層4が配設される前の素子の構成を表
す)にプラズマ状態の不活性ガスまたは反応性ガスに晒
すことによって、前記基板材料上に有機半導体層を形成
するものである。The plasma discharge processing apparatus used in the present invention comprises a plasma discharge processing container as shown in FIG. 4 which will be described later, and a roll electrode which is a ground electrode and a fixed application electrode which is arranged at a position opposed to the roll electrode. Discharged between the electrodes, between the electrodes, introduced an inert gas or a reactive gas into a plasma state, wound on the roll electrode,
By exposing the substrate material for organic thin film transistor element production (in the present application, the configuration of the element before the organic semiconductor layer 4 is arranged) to an inert gas or a reactive gas in a plasma state, the substrate material is formed on the substrate material. The organic semiconductor layer is formed.
【0076】図4は、プラズマ放電処理装置に配設され
た、プラズマ放電処理容器の一例を示す概略図である。FIG. 4 is a schematic view showing an example of a plasma discharge processing container provided in the plasma discharge processing apparatus.
【0077】図4において、有機薄膜トランジスタ素子
作製用の基板材料は搬送方向(図中、時計回り)に回転
するロール電極25に巻回されながら搬送される。固定
されている電極26は複数の円筒から構成され、ロール
電極25に対向させて設置される。ロール電極25に巻
回された前記基板材料は、ニップローラ65、66で押
圧され、ガイドローラ64で規制されてプラズマ放電処
理容器31によって確保された放電処理空間に搬送さ
れ、放電プラズマ処理され、次いで、ガイドローラ67
を介して次工程に搬送される。また、仕切板54は前記
ニップローラ65、66に近接して配置され、前記基板
材料に同伴する空気のプラズマ放電処理容器31内への
進入を調整する機能を有する。In FIG. 4, the substrate material for producing the organic thin film transistor element is transported while being wound around the roll electrode 25 which rotates in the transport direction (clockwise in the figure). The fixed electrode 26 is composed of a plurality of cylinders and is installed so as to face the roll electrode 25. The substrate material wound around the roll electrode 25 is pressed by the nip rollers 65 and 66, is regulated by the guide roller 64, is transported to the discharge processing space secured by the plasma discharge processing container 31, is subjected to discharge plasma processing, and is then subjected to discharge plasma processing. , Guide roller 67
It is conveyed to the next process via. Further, the partition plate 54 is disposed in the vicinity of the nip rollers 65 and 66, and has a function of adjusting entry of air entrained in the substrate material into the plasma discharge processing container 31.
【0078】尚、放電プラズマ処理に用いられるプラズ
マ放電状態の不活性ガスまたは本能性ガスは、給気口5
2からプラズマ放電処理容器31に導入され、処理後の
ガスは排気口53から排気される。The inert gas or instinct gas in the plasma discharge state used for the discharge plasma treatment is the gas supply port 5.
2 is introduced into the plasma discharge treatment container 31 and the treated gas is exhausted from the exhaust port 53.
【0079】印加電極に電圧を印加する電源としては、
特に限定はないが、パール工業製高周波電源(200k
Hz)、パール工業製高周波電源(800kHz)、日
本電子製高周波電源(13.56MHz)、パール工業
製高周波電源(150MHz)等が使用できる。As a power source for applying a voltage to the applying electrode,
High frequency power supply (200k
Hz), a high frequency power supply manufactured by Pearl Industry (800 kHz), a high frequency power supply manufactured by JEOL Ltd. (13.56 MHz), a high frequency power supply manufactured by Pearl Industry (150 MHz) and the like can be used.
【0080】図5は、プラズマ放電処理装置の一例を示
す概念図である。図5において、プラズマ放電処理容器
31の部分は図4の記載と同様であるが、更に、ガス発
生装置51、電源41、電極冷却ユニット60等が装置
構成として配置されている。電極冷却ユニット60の冷
却剤としては、蒸留水、油等の絶縁性材料が好ましく用
いられる。図5に記載の電極25、36は、対向する電
極間のギャップは、例えば1mm程度に設定されること
が好ましい。FIG. 5 is a conceptual diagram showing an example of the plasma discharge processing apparatus. 5, the part of the plasma discharge processing container 31 is the same as that described in FIG. 4, but a gas generator 51, a power supply 41, an electrode cooling unit 60 and the like are further arranged as a device configuration. As the coolant for the electrode cooling unit 60, an insulating material such as distilled water or oil is preferably used. The electrodes 25 and 36 shown in FIG. 5 preferably have a gap between opposing electrodes set to, for example, about 1 mm.
【0081】上記電極間の距離は、電極の母材に設置し
た固体誘電体の厚さ、印加電圧の大きさ、プラズマを利
用する目的等を考慮して決定される。上記電極の一方に
固体誘電体を設置した場合の固体誘電体と電極の最短距
離、上記電極の双方に固体誘電体を設置した場合の固体
誘電体同士の距離としては、いずれの場合も均一な放電
を行う観点から0.5mm〜20mmが好ましく、特に
好ましくは1mm±0.5mmである。The distance between the electrodes is determined in consideration of the thickness of the solid dielectric material provided on the base material of the electrodes, the magnitude of the applied voltage, the purpose of utilizing plasma, and the like. The shortest distance between the solid dielectric and the electrode when the solid dielectric is installed on one of the electrodes, and the distance between the solid dielectrics when the solid dielectric is installed on both of the electrodes are uniform in all cases. From the viewpoint of discharging, it is preferably 0.5 mm to 20 mm, and particularly preferably 1 mm ± 0.5 mm.
【0082】前記プラズマ放電処理容器31内にロール
電極25、固定されている電極36を所定位置に配置
し、ガス発生装置51で発生させた混合ガスを流量制御
して、給気口52よりプラズマ放電処理容器31内に入
れ、前記プラズマ放電処理容器31内をプラズマ処理に
用いる不活性ガスまたは反応性ガスで充填し排気口53
より排気する。次に電源41により電極36に電圧を印
加し、ロール電極25はアースに接地し、放電プラズマ
を発生させる。ここでロール状の元巻き基材61より有
機薄膜トランジスタ素子作製用の基板材料Fを供給し、
ガイドローラ64を介して、プラズマ放電処理容器31
内の電極間を片面接触(ロール電極25に接触してい
る)の状態で搬送され、有機薄膜トランジスタ素子作製
用の基板材料Fは搬送中に放電プラズマにより表面がプ
ラズマ放電処理され、その後にガイドローラ67を介し
て、次工程に搬送される。The roll electrode 25 and the fixed electrode 36 are arranged at predetermined positions in the plasma discharge processing container 31, the flow rate of the mixed gas generated by the gas generator 51 is controlled, and the plasma is supplied from the air supply port 52. It is placed in an electric discharge processing container 31, the inside of the plasma electric discharge processing container 31 is filled with an inert gas or a reactive gas used for plasma processing, and an exhaust port 53 is provided.
Exhaust more. Next, a voltage is applied to the electrode 36 by the power source 41, the roll electrode 25 is grounded to the ground, and discharge plasma is generated. Here, a substrate material F for producing an organic thin film transistor element is supplied from a roll-shaped original winding base material 61,
Through the guide roller 64, the plasma discharge treatment container 31
The inner electrode is conveyed in a single-sided contact state (in contact with the roll electrode 25), the surface of the substrate material F for producing the organic thin film transistor element is subjected to plasma discharge treatment by discharge plasma, and then the guide roller It is conveyed to the next process via 67.
【0083】電源41より固定されている電極36に印
加される電圧の値は適宜決定されるが、例えば、電圧が
0.5kV〜10kV程度で、電源周波数は100kH
zを越えて150MHz以下に調整されることが好まし
い。電源の印加法に関しては、連続モードと呼ばれる連
続サイン波状の連続発振モードとパルスモードと呼ばれ
るON/OFFを断続的に行う断続発振モードのどちら
を採用しても良い。The value of the voltage applied to the electrode 36 fixed by the power supply 41 is appropriately determined. For example, the voltage is about 0.5 kV to 10 kV and the power supply frequency is 100 kH.
It is preferable that the frequency is adjusted to z and 150 MHz or less. Regarding the method of applying a power supply, either a continuous sine wave continuous oscillation mode called a continuous mode or an intermittent oscillation mode called ON / OFF which is intermittently called a pulse mode may be adopted.
【0084】プラズマ放電処理容器31はパイレックス
(R)ガラス製の処理容器等が好ましく用いられるが、
電極との絶縁がとれれば金属製を用いることも可能であ
る。例えば、アルミニウムまたは、ステンレスのフレー
ムの内面にポリイミド樹脂等を張り付けても良く、該金
属フレームにセラミックス溶射を行い絶縁性をとっても
良い。As the plasma discharge treatment container 31, a treatment container made of Pyrex (R) glass is preferably used.
It is also possible to use metal as long as it can be insulated from the electrodes. For example, a polyimide resin or the like may be attached to the inner surface of an aluminum or stainless steel frame, and the metal frame may be sprayed with ceramics to have an insulating property.
【0085】また、放電プラズマ処理時の有機薄膜トラ
ンジスタ素子作製用の基板材料への影響を最小限に抑制
するために、放電プラズマ処理時の有機薄膜トランジス
タ素子作製用の基板材料の温度を常温(15℃〜25
℃)〜200℃未満の温度に調整することが好ましく、
更に好ましくは常温〜100℃に調整することである。
上記の温度範囲に調整する為、必要に応じて電極、基材
は冷却手段で冷却しながら放電プラズマ処理される。Further, in order to minimize the influence on the substrate material for producing the organic thin film transistor element during the discharge plasma treatment, the temperature of the substrate material for producing the organic thin film transistor element during the discharge plasma treatment is kept at room temperature (15 ° C.). ~ 25
C.) to less than 200.degree. C.,
More preferably, the temperature is adjusted to room temperature to 100 ° C.
In order to adjust to the above temperature range, the electrode and the base material are subjected to discharge plasma treatment while being cooled by a cooling means, if necessary.
【0086】また、放電用電極においては、電極の少な
くとも有機薄膜トランジスタ素子作製用の基板材料と接
する側の、JIS B 0601で規定される表面粗さ
の最大高さ(Rmax)が10μm以下になるように調
整されることが、本発明に記載の効果を得る観点から好
ましいが、更に好ましくは、表面粗さの最大値が8μm
以下であり、特に好ましくは、7μm以下に調整するこ
とである。Further, in the discharge electrode, the maximum height (Rmax) of the surface roughness defined by JIS B 0601 at least on the side of the electrode which is in contact with the substrate material for producing the organic thin film transistor element is 10 μm or less. From the viewpoint of obtaining the effects described in the present invention, it is more preferable that the maximum value of the surface roughness is 8 μm.
It is below, and particularly preferably, it is adjusted to 7 μm or less.
【0087】また、JIS B 0601で規定される
中心線平均表面粗さ(Ra)は0.5μm以下が好まし
く、更に好ましくは0.1μm以下である。The center line average surface roughness (Ra) defined by JIS B 0601 is preferably 0.5 μm or less, more preferably 0.1 μm or less.
【0088】[0088]
【実施例】以下、実施例により本発明を説明するが、本
発明はこれらに限定されない。EXAMPLES The present invention will be described below with reference to examples, but the present invention is not limited thereto.
【0089】実施例1
《有機薄膜トランジスタ素子1の作製》以下のようにし
て、図1(a)に示すような構成を有する、トップゲー
ト型有機薄膜トランジスタ素子1を作製した。Example 1 << Preparation of Organic Thin-Film Transistor Element 1 >> A top-gate organic thin-film transistor element 1 having a structure as shown in FIG. 1A was prepared as follows.
【0090】150μm厚のポリイミドフィルム(PI
フィルム)上に、20nmの金薄膜を蒸着し、フォトリ
ソ法により各々ソース、ドレイン電極を形成した。チャ
ネルの長さは5μmとした。150 μm thick polyimide film (PI
20 nm gold thin film was vapor-deposited on the (film), and the source and drain electrodes were formed by the photolithography method. The channel length was 5 μm.
【0091】ここで、ソース電極、ドレイン電極及び有
機半導体層を付与するポリイミドフィルムの表面部位
に、図4に示すようなプラズマ放電処理容器、図5に示
すようなプラズマ放電処理装置を用いて、大気圧プラズ
マ処理(酸素ガス導入)を施した。Here, using a plasma discharge treatment container as shown in FIG. 4 and a plasma discharge treatment apparatus as shown in FIG. 5 on the surface portion of the polyimide film on which the source electrode, the drain electrode and the organic semiconductor layer are provided, Atmospheric pressure plasma treatment (oxygen gas introduction) was performed.
【0092】(プラズマ処理装置及びプラズマ処理条
件)図4に示すようなプラズマ放電処理容器を図5に示
すプラズマ放電処理装置に配置し、下記に記載の放電条
件、反応性ガスを用いて、有機薄膜半導体素子1を製造
した。(Plasma processing apparatus and plasma processing conditions) A plasma discharge processing container as shown in FIG. 4 was placed in the plasma discharge processing apparatus shown in FIG. A thin film semiconductor device 1 was manufactured.
【0093】ここで、プラズマ発生に用いる電源は、神
鋼電機製高周波電源(50kHz)、ハイデン研究所製
インパルス高周波電源(連続モードで使用100kH
z)、パール工業製高周波電源(200kHz)、パー
ル工業製高周波電源(800kHz)、日本電子製高周
波電源(13.56MHz)、パール工業製高周波電源
(150MHz)等が好ましく使用できる。Here, the power source used for plasma generation is a high frequency power source (50 kHz) manufactured by Shinko Electric Co., Ltd., an impulse high frequency power source (100 kH used in continuous mode) manufactured by HEIDEN LABORATORY
z), high frequency power source manufactured by Pearl Industry (200 kHz), high frequency power source manufactured by Pearl Industry (800 kHz), high frequency power source manufactured by JEOL Ltd. (13.56 MHz), high frequency power source manufactured by Pearl Industry (150 MHz) and the like can be preferably used.
【0094】《放電条件》放電出力を4W/cm2に調
整した。<< Discharge Condition >> The discharge output was adjusted to 4 W / cm 2 .
【0095】《エッチングガス組成物》プラズマ処理に
用いた反応性ガスの組成を以下に記す。<< Etching Gas Composition >> The composition of the reactive gas used for the plasma treatment is described below.
【0096】
不活性ガス :アルゴン 98.75体積%
反応性ガス1:酸素ガス(エッチングガス全体に対し1
体積%)
更に、ポリ(3−ヘキシルチオフェン)のクロロホルム
溶液をピエゾ方式のインクジェットノズルを用いて吐出
し、ソース、ドレイン電極間に前記溶液を満たした。溶
媒であるクロロホルムを乾燥により除去後、100℃で
1分間熱処理した。このとき、ポリ(3−ヘキシルチオ
フェン)膜の厚さは約100nmであった。アンモニア
ガス雰囲気下に室温で5時間曝露した後、ソース電極、
ドレイン電極、及び、ポリ(3−ヘキシルチオフェン)
膜の上に、上記記載の大気圧プラズマ法により、厚さ3
00nmの酸化珪素膜を形成した。Inert gas: Argon 98.75% by volume Reactive gas 1: Oxygen gas (1 with respect to the whole etching gas)
Further, a chloroform solution of poly (3-hexylthiophene) was discharged using a piezo system inkjet nozzle to fill the space between the source and drain electrodes. After removing the solvent chloroform by drying, it was heat-treated at 100 ° C. for 1 minute. At this time, the thickness of the poly (3-hexylthiophene) film was about 100 nm. After being exposed to the atmosphere of ammonia gas at room temperature for 5 hours, the source electrode,
Drain electrode and poly (3-hexylthiophene)
A film having a thickness of 3 is formed on the film by the atmospheric pressure plasma method described above.
A silicon oxide film having a thickness of 00 nm was formed.
【0097】ポリ(3−ヘキシルチオフェン)膜に対し
て密着性が良好であり、且つ、緻密な膜が得られた。Adhesiveness to the poly (3-hexylthiophene) film was good, and a dense film was obtained.
【0098】次に、市販の銀ペーストを用いて幅10μ
mのゲート電極を形成し、図1に示すような構成例
(a)に示す有機薄膜トランジスタ素子1を得た。Then, using a commercially available silver paste, the width is 10 μm.
m gate electrodes were formed to obtain the organic thin film transistor element 1 shown in the structural example (a) as shown in FIG.
【0099】《有機薄膜トランジスタ素子2の作製》:
比較例
有機薄膜トランジスタ素子1の作製において、ソース、
ドレイン及びチャネル部分のポリイミド表面に上記記載
の大気圧プラズマ処理を実施しなかった以外は、同様に
して、有機薄膜トランジスタ素子2を作製した。<< Preparation of Organic Thin Film Transistor Element 2 >>:
Comparative Example In the production of the organic thin film transistor element 1, the source,
An organic thin film transistor element 2 was produced in the same manner except that the atmospheric pressure plasma treatment described above was not performed on the polyimide surface of the drain and channel portions.
【0100】得られた有機薄膜トランジスタ素子1、2
の各々について下記に記載のようにして、トランジスタ
特性を評価した。Obtained organic thin film transistor elements 1 and 2
For each of the above, the transistor characteristics were evaluated as described below.
【0101】《トランジスタ特性評価》有機薄膜トラン
ジスタ素子1、2を用いて、各々図6に示すような配線
を付設し、トランジスタ特性の評価を行った。<< Evaluation of Transistor Characteristics >> Using organic thin film transistor elements 1 and 2, wirings as shown in FIG. 6 were respectively attached, and transistor characteristics were evaluated.
【0102】(リーク電流評価)有機薄膜トランジスタ
素子1、2の各々100個の素子について、ソース電極
とドレイン電極間の印加電圧を−30Vとしたときのリ
ーク電流Ioff(nA)を測定した。下記に示すリーク
電流値(nA)は、100個の平均値である。(Evaluation of Leakage Current) The leak current I off (nA) was measured for each of 100 organic thin film transistor elements 1 and 2 when the applied voltage between the source electrode and the drain electrode was −30V. The leak current value (nA) shown below is an average value of 100 pieces.
【0103】(歩留まり評価)100個の有機薄膜トラ
ンジスタ素子1、100個の有機薄膜トランジスタ素子
2の各々について、当該業者公知の方法により、トラン
ジスタ動作を調べ、動作しないものをカウントし、歩留
まりを評価した。(Yield Evaluation) With respect to each of 100 organic thin film transistor elements 1 and 100 organic thin film transistor elements 2, the transistor operation was examined by a method known to those skilled in the art, and those not operating were counted to evaluate the yield.
【0104】得られた結果を下記に示す。 有機薄膜トランジスタ素子 リーク電流(nA) 歩留まり 1(本発明) 0.1 0個 2(比較) 5.0 20個The results obtained are shown below. Organic thin film transistor element Leakage current (nA) Yield 1 (invention) 0.1 0 2 (Comparison) 5.0 20
【0105】[0105]
【発明の効果】本発明により、素子形成時のチャネル近
傍の不純物の混入や微小なゴミ(パーティクル)の付着
を防止することにより、リーク電流が低減し、且つ、画
素欠陥の少ない有機薄膜トランジスタ素子の製造方法を
提供することが出来た。EFFECTS OF THE INVENTION According to the present invention, by preventing impurities from being mixed in the vicinity of a channel and adhesion of fine dust (particles) at the time of forming an element, a leakage current is reduced and an organic thin film transistor element with few pixel defects is formed. It was possible to provide a manufacturing method.
【図1】本発明の有機トランジスタ素子の構成の一例を
示す模式図である。FIG. 1 is a schematic diagram showing an example of the configuration of an organic transistor element of the present invention.
【図2】図1(a)の構成のトランジスタ素子の製造プ
ロセスを示す概念図である。FIG. 2 is a conceptual diagram showing a manufacturing process of the transistor element having the configuration of FIG.
【図3】図1(b)の構成のトランジスタ素子の製造プ
ロセスを示す概念図である。FIG. 3 is a conceptual diagram showing a manufacturing process of the transistor element having the configuration of FIG. 1 (b).
【図4】プラズマ放電処理容器の一例を示す概略図であ
る。FIG. 4 is a schematic view showing an example of a plasma discharge processing container.
【図5】プラズマ放電処理装置の一例を示す概念図であ
る。FIG. 5 is a conceptual diagram showing an example of a plasma discharge processing apparatus.
【図6】トランジスタ素子のFET特性を評価する回路
を示す概念図である。FIG. 6 is a conceptual diagram showing a circuit for evaluating the FET characteristics of a transistor element.
1 有機トランジスタ素子 2 ソース電極 3 ドレイン電極 4 チャネル 5 ゲート電極 6 絶縁層 7 支持体 1 Organic transistor element 2 Source electrode 3 drain electrode 4 channels 5 Gate electrode 6 insulating layers 7 Support
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Claims (2)
縁層、ソース電極、ドレイン電極、有機半導体層を有す
る有機薄膜トランジスタ素子の製造方法において、 該有機半導体層と接する部位の表面を予めプラズマ処理
する工程の後、前記有機半導体層を設ける工程を有する
ことを特徴とする有機薄膜トランジスタ素子の製造方
法。1. In a method of manufacturing an organic thin film transistor element having at least a gate electrode, an insulating layer, a source electrode, a drain electrode, and an organic semiconductor layer on a support, the surface of a portion in contact with the organic semiconductor layer is plasma-treated in advance. After the step, there is a step of providing the organic semiconductor layer, and a method of manufacturing an organic thin film transistor element.
であることを特徴とする請求項1に記載の有機薄膜トラ
ンジスタ素子の製造方法。2. The method for manufacturing an organic thin film transistor element according to claim 1, wherein the plasma treatment is an atmospheric pressure plasma treatment method.
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