JP2003204263A - Phase lock circuit and tuning device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reliably suppress a reference leak over a wide frequency band and to provide satisfactory phase noise characteristics in a phase lock circuit. <P>SOLUTION: A loop filter circuit 30 for smoothing the output of a phase comparator 18 is provided, in addition to an LPF32, with a primary lag lead filter 50 composed of resistors R50 and R52 and a capacitor C52 provided with phase characteristics that a phase is temporarily delayed and then advanced as frequency increases. Thus, the reference leak can be reliably suppressed over the wide oscillation frequency band and the satisfactory phase noise characteristics can be provided. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to phase synchronization (PL).
L: Phase Locked Loop) circuit, or a tuning device such as a PLL frequency synthesizer or tuner using a phase-locked loop circuit used for receiving or transmitting devices such as a television device or a mobile phone. In particular, it relates to improvement of phase noise characteristics.

[0002]

2. Description of the Related Art For example, in various communication devices and transceivers, tuning devices (tuning circuits) such as frequency synthesizers and tuners are used for frequency conversion of transmission signals and reception signals. Then, in order to obtain accurate tuning characteristics, a phase synchronization circuit may be incorporated in the tuning device.

FIG. 6A is a block diagram showing the basic structure of a phase locked loop circuit. This phase synchronization circuit 1 is
An L integrated circuit (PLLIC) 10 and a voltage controlled oscillator (VCO: Vo) having a control input terminal 22 and an output terminal 24.
ltage controlled oscillator) 20 and a loop filter circuit 30. The PLLIC 10 has a reference oscillator 12 that generates a voltage signal f1 having a reference frequency, variable frequency dividers 14 and 16 such as programmable counters, and a phase comparator 18, which are integrated into a single chip. .

The VCO 20 generates a voltage signal f3 having a frequency corresponding to the control signal input to the frequency control input terminal 22, and outputs it from the output terminal 24. Variable frequency divider 14
Is the voltage signal f1 output from the reference oscillator 12
The frequency is divided into A and the divided output signal f2 is input to one terminal 18a of the phase comparator 18. The variable frequency divider 16 is VC
The voltage signal f3 output from O20 is divided into 1 / N,
The divided output signal f4 is sent to the other terminal 1 of the phase comparator 18.
Enter in 8b. Dividing ratio of variable dividers 14 and 16 1 /
A and 1 / N are designated by, for example, a microcomputer (not shown). The phase comparator 18 compares the phases of the two voltage signals f3 and f4, and inputs an error signal indicating the phase difference, which is the comparison result, to the loop filter circuit 30. The loop filter circuit 30 has two voltage signals f3 and
The phase comparison result (error signal) of f4 is smoothed, and this smoothed signal is applied to the frequency control input terminal 22 of the VCO 20 as a frequency control signal.

In the phase locked loop circuit 1, the output voltage signal f3 from the VCO 20 is divided by the variable frequency divider 16 in the PLLIC 10 at a division ratio of 1 / N, and the PLLIC 10 is then divided.
The output signal f4 of the variable frequency divider 16 and the signal f2 obtained by dividing the output signal f1 of the reference oscillator 12 into 1 / A are phase-compared by the internal phase comparator 18, and the output voltage V0 of the phase comparator 18 is obtained. , Control signal V through the loop filter circuit 30
It is converted into 1 and supplied to the VCO 20, and the oscillation frequency of the VCO 20 is controlled.

Here, the loop filter circuit 30 in the conventional phase locked loop circuit 1 attenuates a frequency component above a predetermined cutoff frequency (also called a rolloff frequency or a pole) in the output signal of the phase comparator 18. VCO2
In order to smooth the control voltage supplied to 0, a low-pass filter consisting of, for example, CR (C is a capacitive element, R is a resistive element) and exhibits at least one cutoff frequency is provided.

FIG. 6B shows a low pass filter (LPF) provided in the loop filter circuit 30.
It is a figure which shows an example of r). The illustrated LPF 32 is C
A parallel circuit of the series circuit 34 of 34 and R34 and C32 constitutes an active filter (active filter) connected between the input and output of the negative feedback amplifier 36, and two cutoff frequencies are set. The LPF is not limited to this configuration, and one cutoff frequency composed of one C and one R may be set, or C
The LPFs made of R may be connected in multiple stages. .

On the other hand, in the phase locked loop circuit, it is known that a sideband reference leak (spurious) is superimposed on the output of the VCO in addition to the center frequency component. This reference leak becomes a factor that deteriorates the performance of the phase locked loop. As a method of suppressing the reference leakage, for example, as shown in FIG. 6C, a loop filter circuit in which a primary lag filter 40 composed of C40 and R40 is connected to the latter stage of the LPF 32 is used to reduce the attenuation amount in the high frequency band. It is possible to reduce the reference leak on the high frequency side by making it larger.

[0009]

However, when the cutoff frequency f32 of the LPF 32 in the preceding stage and the cutoff frequency f40 of the first-order lag filter 40 added in the following stage are close to each other, the group delay characteristic which is the phase characteristic of the filter is obtained. Is deteriorated, and, for example, as shown in FIG. 7, the gain characteristic rises near the cutoff frequency, and the gain characteristic deteriorates. Since such a gain characteristic acts to increase the noise power, it has a drawback that the phase noise is deteriorated. Then, this phase noise consequently deteriorates the performance of the phase locked loop. That is, increasing the attenuation of the LPF at the frequency where the reference leak occurs to improve the reference leak may have a trade-off relationship with the phase noise characteristic in the loop band. There was a problem in constructing the circuit. The increase of the phase noise is caused by the PL using the phase locked loop.
This causes a decrease in the performance of a tuning device such as an L frequency synthesizer or a tuner, or a receiving or transmitting device such as a television device or a mobile phone using the tuning device. For example, since the phase noise is the most important characteristic among the characteristics of the digital TV considered as the application of the phase locked loop, the deterioration of the phase noise should not occur.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a phase locked loop circuit capable of reducing the reference leak without increasing the phase noise. Another object of the present invention is to provide a tuning device that does not have the problems of reference leak and phase noise.

[0011]

That is, in a phase locked loop circuit according to the present invention, a loop filter section has a first low pass filter section in which at least one cutoff frequency is set, and a phase increase in frequency. And a second low-pass filter section (so-called lag-lead filter) in which a phase characteristic of being delayed and then proceeding to the next is set. Further, the tuning device according to the present invention includes a phase locked loop circuit having a loop filter section having such first and second low pass filter sections.

In this phase synchronization circuit and tuning device,
The configuration of the second low-pass filter unit is, for example, 2
It is preferable to provide a first-order lag-lead filter circuit having one resistance element and one capacitance element after the first low-pass filter section.

[0013]

In the phase-locked loop circuit having the above structure, in addition to the first low-pass filter section, the second low-pass filter section having the phase characteristic that the phase temporarily delays and then advances with the increase in frequency is set. By providing the band-pass filter unit, the group delay characteristic does not deteriorate even if the cutoff frequencies of the first and second low-pass filter units are close to each other.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a phase locked loop circuit according to the present invention. The basic configuration is the same as that of the prior art except for the loop filter circuit portion, and therefore, the same reference numerals as those shown in FIG. 6 are given to the same functional portions, and the description of the functions will be omitted. The loop filter circuit 30 of the first embodiment in the illustrated phase locked loop circuit 1 has an R50, which is an example of a first low-pass filter unit, and is provided after the LPF (active filter) 32 having two cutoff frequencies. It has the primary lag lead filter 50 which is an example of the 2nd low-pass filter part which consists of R52 and C52. The primary lag-lead filter 50 has a phase characteristic in which the phase temporarily delays and then advances as the frequency increases. The cutoff frequency of the primary lag-lead filter 50 is set to be near or higher than the cutoff frequency of the LPF 32 on the preceding stage side.

FIG. 2 shows the loop filter circuit 3 having the above configuration.
A gain-phase characteristic of 0 is shown. As shown in the figure, since the primary lag lead filter 50 is added to the latter stage of the LPF 32, even if the cutoff frequencies are close to each other, the characteristic phase of the primary lag lead filter 50 is once delayed with an increase in frequency and then The group delay characteristic does not deteriorate due to the progressive phase characteristic. Therefore, the gain characteristic becomes stable and there is no tendency to increase the noise power,
It is possible to reliably suppress the reference leak over a wide voltage controlled oscillation frequency band and obtain good phase noise characteristics. In the conventional loop filter circuit, for example, a lag filter is used for the added filter,
The group delay characteristic deteriorates, which is very different from the deterioration of the gain characteristic.

FIG. 3 is a diagram showing the second and third embodiments of the loop filter circuit 30. The loop filter circuit 30 of the second embodiment shown in FIG.
However, the series circuit of the parallel circuit 38 and C32 of C38 and R38 constitutes an active filter connected between the input and output of the negative feedback amplifier 36, and two cutoff frequencies are set. Different from the embodiment. See also FIG.
The loop filter circuit 30 of the second embodiment shown in FIG.
Differs from the first embodiment in that the LPF 32 does not have C32 and one cutoff frequency is set. However, in any of the aspects, in the latter stage of the LPF 32, as in the first embodiment, the primary lag lead filter 5 is provided.
Since 0 is connected, the same effect as the first embodiment can be obtained.

FIG. 4 shows the fourth to fourth loop filter circuits 30.
It is a figure which shows 6th Embodiment. Both modes are LPF3
2 is a passive filter (passive filter) configuration, which is different from the first embodiment. That is, first, the LPF 32 of the fourth embodiment shown in FIG. 4A is the LPF of the first embodiment.
32, the LPF 32 of the fifth embodiment shown in FIG. 4 (B) is the LPF 32 of the second embodiment, and the LPF 32 of the sixth embodiment shown in FIG. 4 (C) is the LPF 32 of the third embodiment. It has a configuration of. Further, in any of the aspects, since the primary lag lead filter 50 is connected to the latter stage of the LPF 32 as in the first embodiment, the same effect as that of the first embodiment can be enjoyed.

FIG. 5 is a block diagram showing an example of a television system (television receiving system) including a tuner having the phase locked loop circuit of the above embodiment. The illustrated television system 3 includes a tuner IC 70, a high-frequency signal receiving circuit 80 that is an example of a receiving unit that receives a television signal that is an example of a communication signal, and a tuner IC 70.
The digital signal demodulation IC 82 that demodulates the MPEG-TS signal based on the signal output from the CPU, and the CPU 84 that controls the entire television system 3 are provided.

The tuner IC 70 includes a VCO 20 and a loop filter circuit 30, and mixes the phase locked loop circuit 1 functioning as a local oscillation circuit, the received wave f5 input from the high frequency signal receiving circuit 80 and the output signal f3 of the VCO 20. A mixer unit (mixing circuit) 72 for extracting an intermediate frequency (IF) signal of 57 MHz (meaning that the center of the IF signal is 57 MHz) V3, and an IF amplifier for amplifying the IF signal V3 output from the mixer unit 72 to a predetermined level. 74
And a data converter 76, which are integrated into a single chip. In the case of a system that receives a television signal wirelessly, the high-frequency signal receiving circuit 80 transmits a television signal via an antenna or, in the case of a system that receives a cable such as CATV (cable television), via a cable. Entered in.

The oscillator circuit 26 constituting the VCO 20 is, for example, a VHF band (1 to 12 CH; 90 to 222M).
Hz) and UHF band (13-62CH; 470-770M
Resonant circuits that oscillate at a frequency according to the tuning frequency band such as (Hz) may be provided and these may be switched.

When the received wave (received channel image carrier) f5 and the output f3 of the oscillation circuit 26 functioning as a local oscillation circuit are mixed in a circuit having a nonlinear input / output relationship, the signal of f5 + f3 and f5- The signal of f3 is generated.
In the television system 3, the frequency f3 of the oscillator circuit 26 (that is, the local oscillator circuit) is 57 MHz from the received wave f5.
The frequency is increased by z, and the mixer 72 is provided with a 57 MHz resonance circuit to extract a signal of f5-f3 = 57 MHz as an intermediate frequency signal.

The CPU 84 inputs tuning control data for switching the frequency division ratios 1 / A and 1 / N (only one of them may be used) of the variable frequency dividers 14 and 16 to the phase synchronization circuit 1. The digital signal demodulation IC 82 performs various digital demodulation processes such as video detection and audio detection based on the intermediate frequency (IF) signal output from the IF amplifier 74.

With the above configuration, the television system 3
Forms a PLL synthesizer type tuning circuit.
For example, the oscillation frequency of the reference oscillator 12 (reference frequency)
f1 is 3.58 MHz, the frequency division ratio of the variable frequency divider 14 is 1 / A
Is set to 1/3667. At this time, the tuner IC 70
Is the frequency f2 = 97 of 1/3667 of 3.58 MHz
6 Hz, local oscillation frequency 15 when receiving ch1
It matches 1 / (2400 * 64) of 0 MHz, and is 1 / (2 of local oscillation frequency 162 MHz when receiving ch3.
592 * 64), the phase-locked loop 1 works to adjust the local oscillation frequency to a predetermined frequency.

For example, it is assumed that the VCO 20 emits an output signal having a higher frequency as the voltage V1 applied to the frequency control input terminal 22 is higher. In this case, when a channel button (not shown) is pressed to receive “ch1”, “0” or “1”, the CPU 84 causes the one frequency control input terminal 23 of the frequency control unit 27 to apply VHF as the band switching voltage to the frequency control input terminal 23.
Apply a voltage to receive the low band and divide by 1
The tuning control data such that / N becomes 1 / (2400 * 64) is input to the variable frequency divider 16.

If the frequency f3 of the output signal of the oscillation circuit 26, which is the local oscillation frequency, is accurately held at the local oscillation frequency of 150 MHz when receiving ch1, the frequency f4 of the output signal of the variable frequency divider 16 becomes , "150 × 10
^ 6 × (1/64) × (1/2400) ≈976.56
Hz ”(“ ^ ”indicates exponentiation), and the phase comparator 1
It becomes equal to the frequency f2 of the reference signal having a constant frequency applied to the signal 8. The phase comparator 18 outputs a comparison output (detection output) of a reference value (eg, “0”) when f2 and f4 are equal to each other, and a value smaller than the reference value (eg, negative) when f2> f4. In this case, the output voltage V0 is larger than the reference value (for example, positive), and the output voltage V0 is applied to the loop filter circuit 30.

The loop filter circuit 30 includes the phase comparator 1
The voltage signal V0 from 8 is smoothed, and this smoothed voltage signal V1 is input to one frequency control input terminal 22 of the frequency controller 27. For example, when V0 is larger than the reference value, it drops below the reference voltage VS in proportion to its magnitude, and when V0 is smaller than the reference value, it rises above the reference voltage VS in proportion to its magnitude. The voltage signal V1 is input to the frequency control input terminal 22 as a frequency control signal. Therefore, the local oscillation frequency f3 is exactly 150M.
In the case of Hz, the voltage applied to the frequency control input terminal 22 becomes the voltage of the reference voltage VS (for example, 5V constant) so that the oscillation frequency becomes 150 MHz.
When the frequency is higher than MHz, the voltage applied to the frequency control input terminal 22 is reduced and the negative feedback operation is performed so as to reduce the oscillation frequency of the oscillation circuit 26.

As a result, a signal of a constant 150 MHz corresponding to ch1 as the local oscillation frequency f3 is input to the mixer section 72 from the oscillation circuit 26. Therefore, from the mixer section 72, the frequency f5 (VHF band; 90-
222 MHz, UHF band; 470 to 770 MHz) and the oscillation frequency f3 of the oscillation circuit 26
The 57 MHz intermediate frequency signal for 1 is output, and the digital signal demodulation IC 82 can stably decode the ch1 digital television signal.

Next, when the channel button is pressed "0" or "3", the CPU 84 causes the frequency division ratio 1 / N to be 1 / (259).
Variable frequency divider 1 for tuning control data such that 2 * 64)
Enter in 6. Since the oscillation frequency f3 immediately before is 150 MHz, the frequency f4 of the output signal of the variable frequency divider 16 is "1.
50 × 10 ^ 6 × (1/64) × (1/2592) ≈9
Since 04 Hz ″ and f2> f4, the comparison output (detection output) of the phase comparator 18 becomes smaller than the reference value.

Therefore, the voltage applied to the frequency control input terminal 22 rises, and the local oscillation frequency operates so that the frequency is 162 MHz for receiving ch3. As a result, the frequency f5 (V
HF band: 90-222 MHz, UHF band: 470-77
0 MHz) and 57 MHz of the difference frequency between the oscillation frequency f3 of the oscillation circuit 26 for ch3 instead of ch1.
Intermediate frequency signal is output, and the digital signal demodulation IC 82
Can stably decode the ch3 digital television signal.

In the preceding example, ch1 and ch3 have been described, but not limited to this, ch1 to ch1 in the VHF band.
2 (190-222 MHz), ch1 for UHF band
3 to ch 62 (470 to 770 MHz). As described above, the television system 3 outputs the video and audio of the channel desired by the user by switching the local oscillation frequency, that is, the oscillation frequency of the oscillation circuit 26 over a wide band according to the pressed channel button. .

As described above, the loop filter circuit 30 includes, in addition to the LPF 32, a first-order lag-lead filter having a phase characteristic such that the phase temporarily delays and then advances as the frequency increases. 50 are provided. Therefore, even if the cutoff frequencies of the first and second low pass filter sections are close to each other, the group delay characteristic does not deteriorate. Thus, even if the oscillation frequency of the oscillator circuit 26 is switched over a wide band, low reference leak and low phase noise can be achieved over the wide band tuning frequency band. This allows digital TV
It becomes possible to easily and surely solve the problem of deterioration of phase noise, which is the most important characteristic among the characteristics.

Although the present invention has been described with reference to the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be added to the above-described embodiment, and a mode in which such changes or improvements are added is also included in the technical scope of the present invention. Also,
The above embodiments do not limit the claimed invention, and all combinations of the features described in the embodiments are not necessarily essential to the solution of the invention.

For example, in the above embodiment, a second low-pass filter is provided after the first low-pass filter as a second low-pass filter.
Although the primary lag-lead filter of the passive structure is provided, the primary lag-lead filter may be of the active structure. Further, the second low-pass filter may have at least a phase characteristic that the phase temporarily delays and then advances with the increase of the frequency. It is not limited.

In the above embodiment, the second low-pass filter is connected to the rear side of the first low-pass filter. On the contrary, on the contrary, the front stage of the first low-pass filter is connected. A second low pass filter may be connected on the side. Which is to be arranged on the front stage / rear stage side depends on the relationship between the output impedance of the phase comparator 18 and the input impedance of each low pass filter, and the input impedance of the control input terminal of the VCO 20 and the output impedance of each low pass filter. The arrangement may be determined based on the (matching characteristic) so that a good filter characteristic can be obtained. For example, in general, the output impedance of the phase comparator 18 is low and the input impedance of the control input terminal of the VCO 20 is set high, so in this case, one of the first and second low pass filters is set. If the active configuration is used and the other is the passive configuration, it is preferable to arrange the active configuration in the front stage and the passive configuration in the rear stage. If both have the same format, either one may be used.

In the embodiment shown in FIG. 5, a television system provided with a PLL frequency synthesizer type tuning mechanism (tuning mechanism) using a phase locked loop has been described as an example, but it is not limited to the television system. Alternatively, the present invention can be applied to a communication device for reception or transmission provided with a phase synchronization circuit such as a radio, a radio device, or a mobile phone (for example, a W-CDMA system that requires wideband transmission / reception characteristics). Further, the present invention is not limited to communication equipment, and can be applied to other devices that use a phase-locked loop and are used over a predetermined frequency range (two frequencies relatively separated may be used). For example, the present invention can be applied to general angle modulation circuits, angle demodulation circuits, and devices equipped with these circuits.

[0037]

As described above, according to the present invention, as a loop filter circuit, in addition to the first low-pass filter, a primary lag lead filter or the like is used, and the phase is delayed once with an increase in frequency. Since a low-pass filter with a phase characteristic that goes to the above is added, the group delay characteristic and the gain characteristic do not show a tendency to push up the noise power in a stable manner. Thus, the reference leak can be surely suppressed, and good phase noise characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a phase locked loop circuit according to the present invention.

FIG. 2 is a diagram showing gain-phase characteristics of the loop filter circuit shown in FIG.

FIG. 3 is a diagram showing second and third embodiments of a loop filter circuit.

FIG. 4 is a diagram showing fourth to sixth embodiments of a loop filter circuit.

FIG. 5 is a block diagram showing an example of a television system including a tuner having a phase synchronization circuit.

FIG. 6 is a diagram showing a conventional technique, which is a block diagram (A) showing a basic configuration of a phase-locked loop circuit, a diagram (B) showing an example of a low-pass filter provided in a loop filter circuit, and It is a figure (C) which shows the other example of a loop filter circuit.

7 is a diagram showing an example of gain-phase characteristics of the loop filter circuit shown in FIG. 6 (C).

[Explanation of symbols]

1 ... Phase synchronization circuit, 3 ... Television system, 10 ...
PLLIC, 12 ... Reference oscillator, 14, 16 ... Variable frequency divider, 18 ... Phase comparator, 20 ... VCO, 30 ... Loop filter circuit, 32 ... LPF, 50 ... Primary lag lead filter, 70 ... Tuner IC, 72 … Mixer section, 74… I
F amplifier, 80 ... High frequency signal receiving circuit, 82 ... Digital signal demodulation IC, 84 ... CPU

Claims (8)

[Claims] 1. An oscillator having a control input terminal for generating a signal of a first frequency corresponding to a control signal input to the control input terminal; a reference signal of a second frequency serving as a reference; A phase comparator for comparing the phase with the compared signal corresponding to the frequency of 1 and the output of the phase comparator are smoothed, and the smoothed signal is applied as the control signal to the control input terminal of the oscillator. A phase-locked loop circuit including a loop filter unit, wherein the loop filter unit has a first low-pass filter unit in which at least one cutoff frequency is set, and a phase is delayed once with an increase in frequency. And a second low-pass filter section in which a phase characteristic that the phase shifts next is set. 2. The phase-locked loop circuit according to claim 1, wherein the second low-pass filter unit is a first-order lag lead filter circuit including two resistance elements and one capacitance element. . 3. The phase locked loop circuit according to claim 1, wherein the second low pass filter section is connected to a stage subsequent to the first low pass filter section. 4. The first low pass filter section includes one resistance element and one capacitance element, and one cutoff frequency is set. The phase locked loop circuit according to any one of the above. 5. The first low-pass filter unit includes two resistance elements and one capacitance element, and two cut-off frequencies are set. The phase locked loop circuit according to any one of the above. 6. A first low-pass filter section in which at least one cut-off frequency is set and a second low-pass filter section in which a phase characteristic is set such that the phase temporarily delays and then advances as the frequency increases. A tuning apparatus comprising a phase-locked loop circuit having a loop filter unit including a band-pass filter unit. 7. A receiving unit for receiving a communication signal, wherein the phase synchronization circuit compares the phase of a received wave received by the receiving unit with an output signal output from the oscillator. 6. The tuning device according to 6. 8. The tuning device according to claim 7, wherein the receiving unit receives a television signal as the communication signal.