JP2003179142A - Semiconductor device equipped with jitter test circuit, and the jitter test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a jitter decision circuit of a PLL circuit of a semiconductor device and to provide a method of deciding. <P>SOLUTION: The jitter decision circuit is composed of a window clock generator 4, a delay-generating circuit 5 for delaying the trailing of window clock signals, a multiplexer 6 for selecting window clock signals or delayed window clock signals by a command bus [0], a NAND 7 for taking multiplied clock signals while the sampling signal is at a high level, a binary n-bit counter 8 for counting the multiplied clock in the PLL circuit, a flip-flop 9 for storing the counter value, a flip-flop 10 which stores the measured value when the command bus [0] is at a high level as a reference value for deciding the jitter, a command bus 10 for providing a normal mode, a jitter test mode and jitter allowance decision expected value from the outside and a jitter decision circuit 12 for comparing the allowance decision expected value as the selected value of jitter which is inputted from the command bus 10 and the result of measurement. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a jitter inspection circuit and a jitter inspection method thereof.
PLL (Phase Locked Lo)
op), a clock frequency dividing circuit, and a semiconductor device equipped with a jitter inspection circuit improved in the method of inspecting jitter of a reference clock signal, and a jitter inspection method thereof.

[0002]

2. Description of the Related Art In recent years, with the progress of miniaturization technology of semiconductor elements, a semiconductor device (LSI) composed of the semiconductor elements
Is also becoming larger. For example, in recent microprocessors, in order to generate a stable clock signal at high speed,
The L circuit is built in. This is an analog circuit, which is rare in microprocessors, along with a sense amplifier such as a cache. This PLL circuit not only generates a high-speed clock signal with a sharp waveform inside the chip, but also serves to match the phase with an external low-speed clock.

Since this PLL circuit is a feedback circuit, the clock frequency may fluctuate depending on the stability. There is jitter as a fluctuation range of a clock, that is, a fluctuation range when a clock waveform changes with time.

An example of an integrated circuit including this type of PLL circuit is described in Japanese Patent Laid-Open No. 10-267999. Referring to FIG. 14 showing the configuration of an integrated circuit including the PLL circuit described in the publication and FIG. 15 showing a timing chart for explaining the operation thereof, this integrated circuit 40 has a reception clock for sampling an input signal. The first PLL circuit 41 for generating rclk and the second PLL circuit 42 for generating the output signal synchronizing transmission clock tclk are provided, and the first PLL circuit 41 and the second PLL circuit are provided.
The circuit 42 is given a first clock pulse CK1 and a second clock pulse CK2 from the outside of the integrated circuit, respectively.

The PLL jitter measuring function circuit 43 receives the received data given as the input signal IN and the received clock rclk, and receives the received data from the received clock rcl.
A sampling section 44 for sampling by k to obtain a sampling signal, a delay circuit 45 for sequentially storing the sampling signal and delaying the delayed sampling signal for a predetermined time, and a delay sampling signal and a transmission function circuit 48. A selection circuit 46 for selectively transmitting the transmission data to be transmitted as transmission data, and a transmission clock tc
The output section 47 outputs the output data as an output signal OUT in synchronization with lk.

When measuring the jitter of the first PLL circuit 41, an IC tester is connected to the integrated circuit 40, and the IC
A test signal is given as an input signal IN from the tester. In this case, the selection circuit 46 is set so that the delayed sample signal of the delay circuit 45 is used as the transmission data and is output from the output unit 47 as the output signal OUT.

In order to measure the jitter of the reception clock rclk, the IC tester intentionally shifts the phase of the input signal IN and measures the number of expected value errors appearing in the output signal OUT.

First, as shown in FIG. 15, when the position of the timing edge of the input signal IN is slightly ahead of the position of the reference clock RC, the output signal OUT.
There is no expected value error. On the other hand, as shown in FIG. 15, when the timing edge position of the input signal IN coincides with the timing edge position of the reference clock signal RC, two expected value errors occur in the output signal OUT. There is. Furthermore, when the timing edge position of the input signal IN is delayed by a half cycle of the reference clock, the output signal OU
Six expected value errors have occurred in T.

As described above, the jitter can be measured by sequentially shifting the phase of the input signal IN and measuring the relationship with the number of expected value errors appearing in the output signal OUT in each phase.

On the other hand, in addition to the conventional technique for measuring the jitter by varying the sampling signal as described above, Japanese Patent Laid-Open No. 62-13
Japanese Patent No. 1637 also discloses a technique for measuring jitter by varying a timing signal. In this prior art, jitter information is obtained by spectrally decomposing the jitter of the measurement result using a CPU, for example, by a digital signal processing algorithm.

[0011]

As one of the conventional transfer systems in the field of data transfer systems, there is a Rambus system for bidirectional data transfer between a master device and a slave device. In this Rambus system, it is necessary to prevent the clock skew and the like from being deteriorated by the jitter of the transmission clock and the reception clock.

In particular, as the frequencies of the transmission clock and the reception clock become higher, it becomes essential to monitor and prevent the adverse effects of jitter in constructing an integrated circuit.

In the above-mentioned transfer system, the jitter of the PLL circuit for generating the transmission clock can be indirectly measured by monitoring and testing the transmission data output to the outside of each device.

However, the jitter of the received clock generated inside each device to receive the transmitted data cannot be measured from outside the device because the clock is not output outside the device. .

To solve this problem, in the above-mentioned Japanese Patent Laid-Open No. 10-267999, a PLL measuring function circuit for outputting jitter information to the outside is provided in an integrated circuit, and an output signal is output to the outside. The jitter of the PLL circuit is measured.

However, the first problem of this conventional PLL jitter measuring technique is that the sampling signal IN input to the sampling unit inside the PLL measuring function circuit is given from an external tester, which adversely affects the jitter measurement. Is to give.

That is, when a sampling signal is given by an external tester or the like, the sampling signal contains jitter depending on the accuracy of the tester input driver. Although it depends on the tester model, the 200 MHz tester contains a jitter of about 0.2 nS in the driver signal.

Further, deterioration of jitter is expected due to wiring resistance and wiring capacitance between the wiring from the tester input driver to the sampling terminal of the integrated circuit arranged on the test board.

This means that the measured jitter value includes the jitter value of the tester driver, the wiring resistance between the test board wirings, and the value of the deterioration of the jitter characteristic in the wiring capacitance.

The second problem is that as described in the prior art, the input edge timing position is forcibly changed from the outside, the number of errors at this time is counted externally, and the number of changes is calculated for statistical processing. Thus, the jitter of the reception clock rclk sampled by the input signal IN is measured.

Therefore, control processing for changing the position of the input edge timing from the outside of the integrated circuit,
Processing for storing the error count number in the register,
This means that there is a problem in the operability of determining whether the measured value is good or bad because the stored statistical count of the change in the error count is required.

That is, in the conventional technique, the jitter measurement value is obtained only after the input change of the sampling signal input from the outside, the register storage of the count value from the external count processing, and the count change number statistical processing are performed. This is because it is necessary to perform quality determination processing in 100% inspection in the semiconductor device production process, and therefore improvement in operability cannot be expected when performing quality determination of the PLL circuit.

Also, in the case of Japanese Patent Laid-Open No. 62-131637, it is a step of performing the spectrum decomposition of the jitter on the measurement result by the digital signal processing algorithm using the CPU to judge the quality of the jitter. There is overhead, and improvement of operability cannot be expected when making a pass / fail judgment of a circuit.

The present invention focuses on the process for judging the quality of PLL jitter and solves it by a new technique.

An object of the present invention is not only to open a PLL circuit for generating an internal clock that is not output to the outside of the semiconductor device but also to divide a frequency divider and jitter of a reference clock without opening the package of the semiconductor device. An object of the present invention is to provide a jitter judgment method capable of judging quality.

Another object of the present invention is to provide a method for judging the quality of jitter of a PLL circuit, a frequency divider or a reference clock suitable for a semiconductor device which constitutes a general transfer system which constitutes a master device and a slave device. Is.

Still another object of the present invention is to provide a semiconductor device with a PL as an allowance determination expected value from outside via a command bus.
Provide a jitter judgment method that can judge whether the jitter of the PLL circuit, the frequency divider or the reference clock to be generated is good by inputting the jitter tolerance judgment expected value of the L circuit, the frequency divider or the reference clock, and improve the operability. It is to plan.

[0028]

A semiconductor device equipped with a jitter inspection circuit of the present invention comprises a phase locked loop (PLL) means for generating an internal clock signal, an oscillating means for generating the internal clock signal, and the PLL.
It has a jitter inspection means for measuring the jitter of the circuit, and the jitter inspection means has a function of making a pass / fail judgment based on a result of comparison between an allowable judgment expected value of a command format given from the outside and the measurement result of the jitter. Characterize.

Further, it is possible to internally generate a sampling signal for incorporating the multiplied clock signal of the PLL circuit into the jitter measurement reference value and the binary n-bit counter for generating the measurement value in the jitter inspecting means.

Further, delay means for generating a plurality of delay signals in which the falling timings of the sampling signals are changed based on different delay amounts respectively, and the sampling signals and the multiplied clock signals having different delay amounts are subjected to jitter. And a jitter detecting means for detecting the presence or absence of jitter.

Another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is that the phase locked loop (PLL) means for generating a multiplied clock signal for the clock signal of the internal logic circuit and the jitter of the PLL circuit are measured. The jitter inspecting means samples the multiplied clock signal of the PLL means after lock-in with a sampling signal generated internally, and uses the sampled measured value as a reference value for judging whether the jitter is good or not. To have the function of performing.

Further, the jitter inspecting means compares the measured value obtained by measuring the multiplied clock signal with a plurality of delayed sampling signals obtained by delaying the sampling signal and the reference value for each predetermined period, and thus the jitter is compared. Which one of the delayed sampling signals affected by the above is detected, and the value of the detection result is compared with the allowable judgment expected value input from the outside via the external signal bus terminal to perform the jitter check. Have the function to do.

Further, the jitter inspection means has a function of outputting the jitter inspection result obtained by the comparison calculation processing to the outside through the jitter quality judgment terminal and displaying it.

Another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is that the phase locked loop (PLL) means for generating a multiplied clock signal for the clock signal of the internal logic circuit and the jitter of the PLL means are provided. Jitter inspecting means for measuring is provided, and the jitter inspecting means makes a pass / fail decision based on a result of comparison between a command format allowable decision expected value given from outside the semiconductor device and a jitter measurement result, and a multiplied clock of the PLL means. It has a function of judging whether the jitter of the signal or the jitter of the frequency-divided clock signal is good or bad.

Still another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is that it divides the reference clock signal and outputs the divided clock signal to the internal logic circuit. Jitter inspection of the divided clock signal is performed in synchronization with the command signal input from the outside,
In addition, a frequency division clock jitter inspection circuit is provided which outputs a jitter quality determination signal of the inspection result in an inactive state when the inspection result is defective and outputs it in an active state when the inspection result is a non-defective product.

Still another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is phase locked loop (PLL) means for generating a multiplied clock signal for the clock signal of the internal logic circuit, and jitter of the PLL means. And a jitter inspecting means for measuring the signal, wherein the jitter inspecting means samples a multiplied clock signal of the PLL means after lock-in or a reference clock signal input to the PLL means with a sampling signal internally generated,
It has a function of performing a jitter inspection by using a sampled measured value as a reference value for judging whether the jitter is good or bad.

Another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is that a phase locked loop (P) for outputting a multiplied clock signal in synchronization with a reference clock signal is provided.
LL) and the jitter inspection of the reference clock signal in synchronization with a command signal input from the outside, and when the inspection result is defective, the jitter pass / fail judgment signal of the inspection result is output in the inactive state. If there is, a reference clock jitter inspection circuit that outputs in an active state is provided.

Still another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is that a plurality of phase locked loop (PLL) means for generating a multiplied clock signal for the clock signal of the internal logic circuit and a selector bus from the outside. Selecting means for selecting one from a plurality of the PLL means in synchronization with a selector signal given via
There is a jitter checking means for measuring the jitter of the L means, and the jitter checking means internally generates a multiplied clock signal of the PLL means selected by the selecting means among the plurality of PLL means after lock-in. It has a function of performing a jitter inspection by sampling with the sampled signal and using the sampled measured value as a reference value for determining the quality of jitter.

Still another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is that the first and second phase lock outputs the first and second multiplied clock signals in synchronization with the reference clock signal. Droop (PL
L) and one of the first and second multiplied clock signals are selected in synchronism with a selector signal input from the outside via a selector bus or a signal of the selector bus, and then selected to an internal logic circuit. A jitter check of the output multiplexer and the first or the second multiplied clock signal input from the multiplexer is performed in synchronization with a command signal input from the outside, and when the check result is defective, And a jitter inspection circuit of a PLL means that outputs a jitter quality determination signal in an inactive state and outputs a jitter quality determination signal in an active state when it is a non-defective product.

Another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is a plurality of phase locked loop (PLL) means for generating a multiplied clock signal for the clock signal of the internal logic circuit, and the respective PLL means. One of a plurality of internal logic circuits provided corresponding to the above, a selector signal externally applied via a selector bus or a multiplied bi-clock signal output from the plurality of PLL means in synchronization with a signal of the selector bus. A jitter inspecting unit for selecting a signal and a jitter inspecting unit for measuring the jitter of the PLL unit;
After the lock-in, the multiplying clock signal of the PLL means selected by the selecting means of the plurality of PLL means is sampled by a sampling signal generated internally, and the sampled measured value is used as a reference value for judging whether the jitter is good or not. To have the function of performing.

Still another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is to output the first multiplied clock signal to the corresponding first internal logic circuit in synchronization with the first reference clock signal. The first phase-locked loop (PLL) and the second reference clock signal are synchronized with the second phase locked loop (PLL).
Second phase-locked loop (PLL) that outputs the multiplied clock signal of the second to the corresponding second internal logic circuit
And a multiplexer for selecting and outputting one of the first and second multiplied clock signals in synchronization with a selector signal input from the outside via a selector bus, and the first multiplexer input from the multiplexer. Alternatively, the jitter inspection of the second multiplied clock signal is performed in synchronization with the command signal input from the outside, and when the inspection result is defective, the jitter pass / fail judgment signal of the inspection result is output in the inactive state. If there is, the jitter check circuit of the PLL means for outputting in the active state is provided.

Still another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is a phase locked loop (PLL) means for generating an internal clock signal, a multiplied clock signal from the PLL or an external high speed signal. It has a selecting means for selecting a clock signal, an oscillating means for generating the internal clock signal, and a jitter inspecting means. The jitter inspecting means performs a jitter inspection of the multiplied clock signal of the PLL means, and the inspection result is not good. In that case, it has a function of controlling the selecting means by the jitter quality determination signal of the inspection result and selectively outputting the external high speed clock signal.

Another feature of the semiconductor device equipped with the jitter inspection circuit of the present invention is that a phase locked loop (P) that outputs a multiplied clock signal in synchronization with a reference clock signal is used.
LL) and the multiplied clock signal input from the PLL means are inspected in synchronization with an externally input command signal, and when the inspection result is defective, a jitter quality determination signal of the inspection result is output. The jitter checking circuit of the PLL means, or one of the multiplied clock signal and the external high-speed clock signal to be input is selected in synchronization with the jitter quality determination signal input to the control terminal and output to the internal logic circuit. And a multiplexer.

Further, the jitter inspection circuit has a command bus for transmitting a command signal for giving a normal mode, a jitter inspection mode, and a jitter tolerance judgment expected value from the outside, and a window clock signal for generating a sampling signal. A window clock oscillator for generating, a delay generation circuit for delaying a falling timing of the window clock signal, the window clock signal and the delayed delayed window clock signal in synchronization with the mode switching signal of the command bus. Multiplexer for switching output and the PLL
A binary n-bit counter which counts the multiplied clock signal of the means and outputs it as a measured value of the count result, and the P signal during the high level period when the sampling signal is at the logical level.
A logic circuit for fetching the multiplied clock signal of the LL means into the binary n-bit counter, a first flip-flop for storing the measurement value output by the binary bit counter, and the mode switching signal to a high level. Second flip-flop that stores the measured value stored in the first flip-flop as a reference value when determining whether or not to allow jitter, and the jitter that is a selection value of jitter given from the command bus. A jitter pass / fail judgment circuit for comparing the allowable judgment expected value with the measured value is provided.

Further, the command bus has a low level of a logic level in the normal mode and a high level of a logic level in the jitter checking mode of the PLL means, and a logic level indicating a jitter tolerance judgment expected value. Are configured in advance with the second to nth buses.

Furthermore, the delay generation circuit inputs the window clock signal, repeats counting immediately after resetting the count value, and shares the window clock signal with the first n-ary ring counter set by the reset signal. A first window clock signal with delay, which is input with a signal obtained by delaying the window clock signal by a different delay amount and delays the falling timing of the window clock signal. ~ The n-th OR circuit and the count values output from the n-ary ring counter are synchronized with the first to n-th selector signals, respectively, and the corresponding first to n-th
And a multiplexer that selectively outputs the window clock signal with delay.

Further, the jitter quality determination circuit includes a reference value comparing section for comparing a measured value of the jitter extracted for each of the first to nth sampling signals having different delay times with a reference value, and the reference value comparing section. A measurement result for detecting a sampling signal affected by jitter by comparing with a reference value for each of the first to nth sampling signals and for each of the first to nth sampling signals based on the comparison result of the value comparison unit. Comprised of an averaging processing unit and a jitter tolerance value determination processing unit that compares the sampling signal affected by the jitter with the jitter tolerance determination value set from the command bus and outputs the comparison result as a jitter quality determination signal. To be done.

Further, the reference value comparison unit includes an exclusive NOR circuit for comparing the reference value with the measured value, first to nth selectors synchronized with an external command signal and the sampling signal. A reference comparison circuit including an AND circuit that takes a logic with a signal and a flip-flop that stores the signal of the comparison result of the exclusive NOR circuit in synchronization with the selector signal output from the AND circuit Have a pair.

Further, the measurement result averaging processing unit counts a ring counter in synchronization with the nth selector signal among the first to nth selector signals, and the first to nth ring counters. First to n-th storing the corresponding output of the reference value comparison circuit in synchronization with each output
N flip-flops are compared with the outputs of the first to n-th flip-flops, and the result of the comparison is output to the jitter pass / fail judgment processing section.

Further, the jitter quality determination processing section synchronizes with the polarity inversion signal of the least significant bit output of the ring counter in the measurement result averaging processing section, for each of the n sets of exclusive NOR circuits. N flip-flops that store the respective outputs, and n OR circuits that take the logic of the respective outputs of the n flip-flops and the corresponding signals of the command buses, respectively.
A logical product circuit that outputs a logical product of the outputs of the n logical sum circuits as a jitter pass / fail signal.

A jitter inspection method for a semiconductor device equipped with a jitter inspection circuit of the present invention is a phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and the jitter of the PLL means is measured. It is characterized in that it has a jitter inspecting means, and judges whether or not the jitter inspecting means is acceptable based on a result of comparison between an externally-applied command-type allowable determination expected value and a jitter measurement value of the multiplied clock signal.

A sampling operation in which self-oscillation is internally performed and a falling edge of the multiplied clock signal is taken into a binary n-bit counter for generating an internal jitter measurement reference value and measurement value in synchronization with the oscillation clock signal Thus, it is possible to inspect the quality of the jitter of the multiplied clock signal by generating the reference value and the measured value and comparing them.

Further, the delay means generates a plurality of delay signals in which the falling timing of the sampling signal is changed based on different delay amounts, and the sampling signal with the changed delay amount is multiplied by the jitter detecting means. The presence or absence of jitter may be detected by comparing with the jitter of the clock. 27. Another feature of the jitter inspection method for a semiconductor device equipped with the jitter inspection circuit of the present invention is that the phase locked loop (PLL) means for generating a multiplied clock signal for the clock signal of the internal logic circuit, and the jitter of the PLL means. Has a jitter inspecting means for measuring the jitter, and the jitter inspecting means samples the multiplied clock of the PLL means after the lock-in by a sampling signal generated internally, and the sampled measured value is used as a reference value for judging whether the jitter is good or not. It is about conducting an inspection.

Further, the jitter inspection means can output the jitter inspection result obtained from the comparison operation processing to the outside through the jitter quality determination terminal and display it.

Another feature of the jitter inspection method for a semiconductor device having the jitter inspection circuit according to the present invention is phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and the PLL. Means for measuring the jitter of the means, and the jitter checking means judges the quality based on the result of comparison between the jitter measurement result and the allowable judgment expected value in the command format given from the outside of the semiconductor device, and the PLL. The quality of the jitter of the multiplied clock signal of the means or the jitter of the divided clock signal of the frequency divider is determined.

Still another feature of the jitter inspection method for a semiconductor device equipped with the jitter inspection circuit of the present invention is a phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and the PLL.
A jitter inspecting means for measuring the jitter of the means, and the jitter inspecting means samples the PLL multiplied clock after lock-in or the reference clock signal input to the PLL means with a sampling signal generated internally, and performs sampling. The jitter inspection is performed by using the measured value as a reference value for determining the quality of jitter.

Still another feature of the jitter inspection method for a semiconductor device equipped with the jitter inspection circuit of the present invention is that a plurality of phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, It has a selecting means for selecting one from a plurality of the PLL means in synchronization with a selector signal given from the outside via a selector bus, and a jitter inspecting means for measuring the jitter of the PLL means. , The multiplying clock signal of the PLL means selected by the selecting means among the plurality of PLL means after lock-in is sampled by a sampling signal generated internally, and the sampled measured value is used as a reference value for judging whether the jitter is good or bad. It is to perform a jitter inspection.

Still another feature of the jitter inspection method for a semiconductor device equipped with the jitter inspection circuit of the present invention is that a plurality of phase locked loop (PLL) means for generating a multiplied clock signal for the clock signal of the internal logic circuit, respectively. A plurality of internal logic circuits provided corresponding to the PLL means, and one of the step-up bi-clock signals output from the plurality of PLL means in synchronization with a selector signal externally applied via a selector bus. Of the PLL means selected by the selecting means of the plurality of PLL means after lock-in by the jitter inspecting means. Measurement value obtained by sampling the multiplied clock signal with the sampling signal generated internally and sampling In performing the jitter test as a reference value of the jitter quality determination.

Still another feature of the jitter inspection method for a semiconductor device equipped with the jitter inspection circuit of the present invention is a phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and the PLL means. And a jitter checking means for measuring the jitter of the PLL means. The jitter checking means checks the jitter of the multiplied clock signal of the PLL means. If the inspection result is bad and the inspection result is not good, the selection means is controlled by the jitter quality determination signal of the inspection result to selectively output the external high speed clock signal.

[0060]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the outline of the present invention will be described.
According to the configuration of the semiconductor device equipped with the jitter inspection circuit according to the present invention shown in FIG. 1, the window clock oscillator 4 self-oscillates inside the semiconductor device, and the falling edge of the multiplied clock signal of the PLL means is set to 2 An operation (action) called sampling that is taken into the base n-bit counter is executed.

Therefore, it is not necessary to receive the sampling signal from the tester input driver connected to the outside of the semiconductor device, and therefore, the effect that the sampling can be performed without being influenced by the jitter from the tester input driver is obtained.

The delay generation circuit 5 gives a delay (action) to the falling edge of the window clock signal. Therefore, the falling timing of the window clock signal, which is the sampling signal, is changed, that is, delayed, to match the jitter and obtain the measured value at the time of judging the quality of the jitter.

Further, since it is not necessary to change the sampling signal from the outside as in the conventional case, the operability of the quality judgment in the manufacturing process of the semiconductor device is improved.

Furthermore, the jitter pass / fail judgment circuit 12 executes an operation (action) of comparing the allowable judgment expected value, which is the selected value of jitter given from the command bus, with the inspection result. It is not necessary to measure the jitter by counting the number of errors and performing statistical processing in. That is, since the quality of the jitter can be determined internally, the operability of the quality determination in the manufacturing process of the semiconductor device is improved.

Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1 showing the configuration of the first embodiment of a semiconductor device equipped with the jitter inspection circuit of the present invention, a semiconductor device equipped with the jitter inspection circuit of the present invention is
Input a reference clock signal of nMHz from the outside, n × 2
A PLL circuit 1 which generates and outputs a multiplied clock signal of × T MHz, a logic circuit 2 inside the semiconductor device which operates in synchronization with the multiplied clock signal output from the PLL circuit 1 as a reference clock signal, and a multiplied clock output from the PLL circuit 1. It is composed of a jitter inspection circuit 3 which inputs a signal and inspects the quality of the jitter, and outputs a jitter quality determination signal.

The jitter inspection circuit 3 of the present invention comprises a window clock oscillator 4 for generating a window clock signal which is the basis of a sampling signal, a window clock signal with a delay and a built-in ring counter for delaying the falling timing of the window clock signal. Of the delay generation circuit 5 for outputting the count value Q [1: a] output by the above, the window clock signal and the window clock signal with delay are input, and one of them is selected in synchronization with the command bus [0]. Output multiplexer 6
And a negative logic for the sampling signal input from the multiplexer 6 to take in the multiplied clock signal during the high level period of the logic level and output it to the binary n (n is an integer) bit counter 8 connected to the next stage for counting. Product circuit NAND7.

Further, the jitter inspection circuit 3 is reset at the rising timing of the sampling signal, and the NAND circuit NA is set during the high level period of the sampling signal.
A binary n-bit counter 8 that counts the multiplied clock signal of the PLL circuit 1 output by the ND 7 and outputs a measured value A [0: k], and a measured value A that is a binary n-bit counter value.
The command bus [0] stores a flip-flop (FF) 9 that stores [0: k] and outputs it as a measurement value B [0: k], and a measurement value B [0: k] output from the flip-flop 9. It has a flip-flop (FF) 10 which stores when it becomes a high level and outputs it as a reference value A [0: k] at the time of jitter tolerance judgment. [0: k] here
Indicates the range of the bit width of the counter. Further, the measured value A [0: k], the measured value B [0: k], and the reference value A [0:
k of k] and n of binary n bits are the same integers. Further, the count value Q output by the ring counter
The a of [1: a] has a relationship with k such that a (bus of ring counter) = a (delay and number of ORs) = k−1.

Further, in the jitter inspection circuit 3, a command bus [0: m] (m is an integer) for giving a normal mode, a jitter inspection mode, and a jitter tolerance judgment expected value from the outside is connected to the input terminal, and the normal mode is set. And a command bus block 11 for connecting a command bus [0] for giving a jitter inspection mode and a command bus [1: m] for giving a jitter tolerance expected value to output terminals, and a command bus block 1
1, the command buses [0] and [1: m] are applied, the measured value B [0: k] is applied from FF9, and the reference value A [0: k] is applied from FF10. From the first to the count value Q [1: a]
~ The a-th selector signal is given, and the command bus [1:
The allowable judgment value [1: m], which is the jitter selection value of [m], and the measured value, which is the comparison result of the reference value A [0: k] and the measured value B [0: k], are compared to judge whether the jitter is good or bad. It has a jitter quality judgment circuit 12 for outputting a signal.

Referring to FIG. 2 showing the structure of the command bus, the command bus block 11 has a command bus [0] and a command bus [1: m], and the command bus [0] is a mode setting bus. When the signal level of the bus is “0”, the normal mode is shown, and when the signal level is “1”, the jitter inspection mode is shown. The command bus [1: m] is a bus for setting the jitter tolerance judgment expected value, which represents the command buses 1, 2, 3, ..., M-1, m, and specifies the jitter pass / fail range.

Note that the command bus [0: m] here has a relationship of m = a = k−1 from the expected value [1: m].

Referring to FIG. 3 showing the circuit diagram of the delay generating circuit 5, the delay generating circuit 5 repeats counting immediately after resetting the count value when the window clock signal is input, and is set by the next reset signal. 1 n-ary ring counter 13 and a window clock signal are commonly input to one of the input terminals, and the window clock signal is input to the other input terminal of the delay circuits 1 to a (a is an integer).
1 of the signals delayed by different delays
1 to a-OR circuits OR1 to OR1 for generating the first to a-th delayed window clock signals by delaying the fall timings of the window clock signals ORa and a
The count value Q [1: output from the advance ring counter 13
a] and a multiplexer 14 that selectively outputs the corresponding first to a-th delayed window clock signals 1 to a in synchronization with the first to a-th selector signals.

Referring to FIG. 4 which is a circuit diagram of the jitter quality determination circuit 12, the jitter quality determination circuit 12 measures the jitter extracted for each of the first to kth sampling signals having different delay times. Based on the comparison result of the reference value comparison unit 14 that compares the value B [0: k] with the reference value A [0: k], the measurement results from the first cycle to the b-th cycle are A measurement result averaging processing unit 15 that detects the sampling signal affected by the jitter by performing the exclusive NOR operation EXNOR processing for each of the 1st to a-th sampling signals, and the sampling signal affected by the jitter. The reference value comparison unit 14 configured with a jitter quality determination processing unit 16 that compares the jitter tolerance determination value set from the command bus and outputs the comparison result as a jitter quality determination signal, uses a reference value A 0: k] and the measured value B [0: k] and respectively comparing separately the exclusive NOT OR circuit EXNO
R17 is individually ANDed with each of the first to ath selector signals, which are the count value Q [1: a] of the a-adic ring counter 13 synchronized with the external test command [0] signal and the sampling signal. AND circuit AND18,
There are a set of reference comparison circuits each including a flip-flop FF19 that stores the signal of the comparison result of the exclusive NOR circuit EXNOR17 in synchronization with the selector signal output from the AND circuit AND18.

The measurement result averaging processing section 15 is arranged to
B-ary ring counter 20 that counts in synchronization with the a-th selector signal among the selector signals of the above, and the corresponding outputs of reference value comparison circuit 14 in synchronization with the first to b-th outputs of b-ary ring counter 20, respectively. An exclusive-NOR circuit EXNOR22 that compares the stored outputs of the first to b-th flip-flops FF211 to FF21b and the first to b-th flip-flops FF211 to FF21b and outputs the comparison result to the jitter quality determination processing unit 16. And a set of averaging processing circuits.

The b of the b-ary ring counter 20 is an integer and indicates how many cycles are averaged. The greater the number, the higher the accuracy of the average value.

The jitter quality determination processing unit 16 synchronizes with the polarity inversion signal of the least significant bit output Q1 of the b-ary ring counter 20 in the measurement result averaging processing unit 15 and sets a sets of exclusive NOR circuits EXNOR22. A flip-flops FF23 for storing the respective corresponding outputs,
For each of the a flip-flops FF23, there are a logical OR circuits OR24 that take the logic of the corresponding outputs and the polarity inversion signals of the corresponding signals of the command buses [1: m], and these a logics. AND circuit AND25 which outputs the logical product of the outputs of the sum circuit OR24 as a jitter pass / fail judgment signal.

Next, the operation of the first embodiment having the above configuration will be described. Referring again to FIG. 1, the PLL
If the reference clock frequency of the circuit 1 is n MHz, P
In the LL circuit 1, the multiplied output clock frequency after being multiplied by T is a frequency of n × 2 × T.

Here, as an example, the operation in the case of inspecting the PLL circuit operating at the frequency of the reference clock signal of 25 MHz and the multiplied clock signal of 100 MHz will be described.

Immediately after resetting and initializing this semiconductor device, the PLL circuit 1 starts the multiplied clock oscillation.
At the same time as initialization, command input is performed via the command bus block 11.

Referring again to FIG. 2, at this time, the command bus [0] is in the normal operation mode at the low level and in the jitter inspection mode at the high level, and the allowable judgment expected value is input from the command bus [1: m]. The meaning of the allowable determination expected value means the determination result of each of delay 1 to delay a from 1 bit to m bits, and it is determined that each bit is at a high level and is not affected by jitter.

That is, PA is not affected by jitter.
SS, receive and fail. Also, each bit is not judged at the low level. That is, PASS is performed regardless of the influence of jitter.

With this combination, the allowable range of jitter can be set. The command bus [0] is set to low level immediately after reset. At the same time, the window clock oscillator 4 starts oscillating and the window clock signal is output.

The oscillation frequency of the window clock oscillator 4 at this time needs to be equal to or lower than the reference clock frequency and the multiplied clock signal frequency of the PLL circuit. Therefore, the description of the window clock signal frequency at this time is 12.5 MHz.

Since the command bus [0] is at the low level (normal operation mode), the multiplexer 6 selects the window clock signal and outputs it as the sampling signal. At this time, it is assumed that the binary n-bit counter 8 has 8 bits.

The binary n-bit counter 8 starts counting after being reset by the rising signal of the sampling signal. The signal to be counted is a signal obtained by performing NAND operation on the multiplied clock signal of the rising period of the sampling signal by the NAND 7.

The value counted by the binary n-bit counter 8 is written in the FF 9 at the falling timing of the sampling signal.

On the other hand, in the PLL circuit 1, the multiplied clock signal of the PLL circuit immediately after the semiconductor device is initialized is stable in both frequency and jitter during the lock-in time (also referred to as pull-in time or PLL circuit stabilization time). Therefore, after the lock-in time has elapsed, the PLL circuit jitter tolerance judgment test is performed.

After the lock-in time has elapsed, the command bus [0] is set to the high level (jitter quality judgment mode).
At this time, the count measurement value of the multiplied clock signal of the PLL circuit 1 stored in the FF 9 is taken in by the FF 10 and output as the reference value A [0: k].

That is, referring to FIG. 5 which shows a timing chart for explaining the operation, the reference value A [0: k] of the jitter pass / fail judgment circuit 12, such as [04: ] Becomes.

Further, by raising the command bus [0] to a high level, the output of the delay generation circuit 5 is output.
The window clock signal with falling delay is selected by the multiplexer 6 and output as a sampling signal.

Referring now to FIG. 3, the delay generation circuit 5
First, when the window clock signal is input, the a-adic ring counter 13 starts from 000 ... 001 (left upper bit, right lower bit) 000 ... 010000 ... 100, immediately after resetting the count value Q.
Then, 010 ... 000, 100 ... 000, and return to the beginning to 000 ... 001, and this is repeated.

The reset signal causes a-adic ring counter 1
3 is set to 000 ... 001. OR circuit OR
The window clock signal is input to one of the inputs 1 to ORa,
By inputting a signal in which the window clock signal is delayed to each of the other inputs, the delayed window clock signals 1 to a which are signals in which the falling timing of the window clock signal is delayed are input. To generate.

The multiplexer 14 inputs the output Q [1: a] of the a-ary ring counter 13 as a selector signal, and when the Q1 signal is at a high level, outputs the delayed window clock signal 1 to the delayed window clock signal. , When the Q2 signal is at the high level, the delayed window clock signal 2 is output to the delayed window clock signal, and when the QC signal is at the high level, the delayed window clock signal a is output to the delayed window clock signal a. Output as is.

In the delay generation circuit 5, for example, when the a-adic ring counter 13 is constituted by octal and the delays A1 to Aa are constituted by eight delays, the operation will be described assuming the following.

Each delay A1 to A8 is a type value, and the delay A1
= 2nS, delay A2 = 3nS, delay A3 = 4nS, delay A4 = 5nS, delay A5 = 6nS, delay A6 = 7nS,
It is assumed that the delay A7 = 8 nS and the delay A8 = 9 nS, and the ability of the multiplied clock jitter of the PLL circuit 1 is 4 nS.

Referring to FIG. 6, which shows a timing chart of counter measurement values for sampling signals (delay 1 to delay 8), sampling signals (delay 1 to delay 8)
The measurement result of is measured value B
It is input through the input terminal of [0: k].

Referring again to FIG. 4, the inside of the jitter quality determination circuit 12 is composed of the reference value comparison unit 14, the measurement result averaging processing unit 15, and the jitter quality determination processing unit 16 as described above, and the sampling signal (delay The measured value B in 1 to delay 8) is the exclusive NOR circuit EXN of the reference value comparison unit 14.
It is compared with the reference value A by OR17.

Referring to FIG. 7, which is a block diagram for explaining the processing in the reference value comparison unit 14, the value of the FF 10 of the reference value A in FIG. 1 is 04h, the first measured value is 04h,
The second measured value is 04h, the third measured value is 04h, 4
The process when the 5th measured value is 05h, the 5th measured value is 05h, the 6th measured value is 05h, the 7th measured value is 05h, and the 8th measured value is 05h is shown.

For example, when the value of the FF 10 of the reference value A = 04h is compared with the measured value of the first time = 04h, since they match, the 0th bit FF 19 = 1, and similarly the FF of the reference value A is FF.
When the value of 10 = 04h is compared with the measured value of the second time = 04h and the measured value of the third time = 04h, they match each other. Therefore, the FF19 of the second bit is FF19 = 1, the FF19 of the third bit is 1, and the reference Comparing the value A of FF10 of the value A = 04h with the measured value of the fourth time = 05h, the values of FF19 of the 4th bit are 0 because they do not match, and the values of the FF19 from the fifth time to the eighth time are 0 respectively.

As described above, when the multiplied clock signal of the PLL circuit 1 becomes stable, the command bus [0] that enters the jitter pass / fail judgment mode becomes high level, and the value of the binary n-bit counter at that time, for example, 04h It is stored in the FF 10 as a reference value and remains unchanged as long as it is in the jitter inspection mode.

On the other hand, the FF 9 stores the value of the binary n-bit counter at that time one after another as the sampling signal using the window clock signal with delay as the sampling signal, and as the measured value, the jitter pass / fail judgment circuit 12 respectively.
Supply to.

Therefore, the falling delay clock (delay 1
~ When the falling timing of delay 8) exceeds the falling timing of the measurement clock (multiplied clock signal),
The compared value of the reference value A of the reference value FF10 and the measured value B do not match.

Since the reference value comparison unit 14 uses the delayed window clock signals 1 to 8 as the sampling signal, the FF of the measurement results of 8 times and the reference value A is FF.
The value is compared with the value of 10 and stored in the flip-flop FF19 of the reference value comparison unit 15 for each bit.

FIG. 8 shows a block for explaining the pass / fail judgment processing in the case where the cycle of the sampling signal from delay 1 to delay 8 is set as one cycle and the multiplied clock signal is measured and judged for a total of 8 cycles. is there. Referring to FIG. 8, in the measurement result averaging processing unit 15, the results measured from the first cycle to the eighth cycle are stored in the register (F
It is written in F211 to FF21b).

Here, the exclusive NOR circuit EXNOR processing is performed on each bit of the measurement results from the first cycle to the eighth cycle, so that the counter value is within the jitter 1 to delay 8 of the sampling signal. It can be detected which sampling fall delay has been affected.

The jitter quality judgment processing section 16 judges the detection result and the value of the command bus [1: m]. If the judgment result is less than the jitter tolerance judgment expected value of the PLL circuit 1, it is PASS, and if the PLL circuit 1 jitter is more than the tolerance judgment expected value, it is FAIL.

The processing at this time is performed by the command bus [1: m].
The polarity inversion signal and the processing result average value [1: a] of the measurement result averaging processing unit 15 are taken as a logical sum circuit OR24, and the result is subjected to a logical product circuit AND25 to determine pass / fail.

Here, it is assumed that the allowable determination expected value is input as 11000011 (left upper bit, right lower bit) from the command bus [1: 8].

The result of the measurement result averaging processing unit 15 is 110.
It is 00001. An allowable judgment expected value of 1 determines that the influence of jitter is not exerted, and a value of 0 determines that the influence of jitter may be exerted. Therefore, when the result of the measurement result averaging processing unit 15 is compared with 11000011, the result of the measurement result averaging processing unit 15 is not 0 in the bit where the allowable determination expected value is 1, so the jitter of the PLL circuit 1 is equal to the allowable determination expected value. The value is less than or equal to the value, and the jitter pass / fail signal outputs a high level of PASS.

According to the above-described first embodiment of the present invention, the window clock oscillator circuit 4 performs self-oscillation inside the semiconductor device, and the falling edge of the PLL circuit is taken into the binary n-bit counter. Since the operation described above is performed, it is not necessary to input a sampling signal from a tester input driver connected to the outside of the semiconductor device, and sampling can be performed without being affected by the jitter.

Further, the delay generating circuit 5 gives a delay (action) to the falling edge of the window clock signal. Therefore, it is possible to obtain the measured value at the time of judging the quality of the jitter by matching the jitter while changing the falling position of the window clock signal which is the sampling signal.

Further, since it is not necessary to change the sampling signal from the outside as in the conventional case, the operability of the quality judgment in the manufacturing process of the semiconductor device is improved.

Further, the jitter pass / fail judgment circuit 12 executes the operation of comparing the allowable judgment expected value, which is the selected value of the jitter given from the command bus [1: m], with the measurement result. In addition, it is possible to improve the operability of the quality determination in the semiconductor device production process by performing the quality determination of the jitter without counting the number of errors and measuring the jitter by performing the statistical processing on the outside.

Next, a second embodiment of the present invention will be described. 9 is a block diagram showing the configuration of the second embodiment.
Referring to FIG. 2, the difference from the first embodiment is that the PLL
Divider 3 that divides the reference clock signal without the circuit
The difference is that it has 0.

That is, the frequency divider 30 and the frequency-divided clock signal divided by the frequency divider 30 are applied to the internal logic circuit 2 which operates in synchronization with the frequency-divided clock signal. And the jitter inspection circuit 3 of the present invention for inspecting the jitter of the frequency divider 30 in response to the command bus and outputting a quality determination signal of the inspection result. The jitter inspection circuit 3 has the same configuration as that of the first embodiment described above.

In the above configuration, the jitter inspection circuit 3
, The command bus [0] is at a low level (normal operation mode), so that the multiplexer 6 selects the window clock signal and outputs it as the sampling signal. In this example as well, the number of bits of the binary n-bit counter 8 is 8.
Described as a bit.

The binary n-bit counter 8 starts counting after being reset by the rising signal of the sampling signal. The signal to be counted is a signal obtained by subjecting the divided clock signal in the high level period of the sampling signal to the NAND operation in the NAND 7.

The value counted by the binary n-bit counter 8 is written in the FF 9 at the falling timing of the sampling signal.

After initialization, the command bus [0] is set to a high level (jitter quality judgment mode). At this time, the count measurement value of the divided clock signal of FF9 is taken into FF10.

Referring to FIG. 5, the reference value A [0: k] of the jitter quality determination circuit 12, which is [04] in this example, is set as in the write timing to the FF 10 and thereafter during the jitter quality determination mode period. Is the standard value A [0
4].

Further, by raising the command bus [0] to a high level, the output of the delay generation circuit 5 is output.
The window clock signal with falling delay is selected by the multiplexer 6 and output as a sampling signal.

That is, delayed window clock signals 1 to a, which are signals obtained by delaying the fall timing of the window clock signal, are generated as sampling signals.

Each of the delays A1 to A8 is a typ value, and the delay A1
= 2nS, delay A2 = 3nS, delay A3 = 4nS, delay A4 = 5nS, delay A5 = 6nS, delay A6 = 7nS,
It is assumed that the delay A7 = 8 nS and the delay A8 = 9 nS, and the ability of the divided clock jitter is 4 nS.

Referring again to FIG. 6 showing the timing chart of the counter measurement values for the sampling signals (delay 1 to delay 8), the measurement results up to the sampling signals (delay 1 to delay 8) are determined by the jitter pass / fail judgment circuit. The measured value B [0: k] is input to 12 via the input terminal.

The measured value B of the sampling signal (delay 1 to delay 8) is the exclusive NOR circuit E of the reference value comparison unit 14.
It is compared with the reference value A [04] by the XNOR 17.

Referring to FIG. 7, for example, the FF having the reference value A
When the value of 10 = 04h is compared with the measured value of the first time = 04h, they match, so the FF19 of the 0th bit is 1, and similarly, the value of FF10 of the reference value A = 04h and the measured value of the second time = 04h. Comparing with the third measurement value = 04h, they match each other, so the FF19 of the second bit
= 1, 3rd bit FF19 = 1, reference value A FF10
Comparing the value of 0 = 04h with the measured value of the 4th time = 05h, the value of FF19 of the 4th bit becomes 0, and similarly, the value of FF19 at the 5th time to the 8th time becomes 0, because they do not match.

As described above, when the falling timing of the falling delay clock (delay 1 to delay 8) exceeds the falling timing of the measurement clock (multiplied clock signal), the value of the reference value A of the reference value FF10 becomes The compared values of the measured values B do not match.

Since the reference value comparison unit 14 uses the delayed window clock signals 1 to 8 as the sampling signal, the FF of the measurement result of eight times and the reference value A is FF.
The value is compared with the value of 10 and stored in the flip-flop of the reference value comparison unit 15 for each bit.

Referring to FIG. 8, in the measurement result averaging processing section 15, the results measured from the first cycle to the eighth cycle are stored in the registers (FF211 to FF2) of the measurement result averaging processing section.
1b).

By performing the EXNOR processing for each bit on the measurement results from the first cycle to the eighth cycle, which of the delays 1 to 8 of the sampling signal is the counter value influenced by the jitter? It is possible to detect whether the sampling delay has fallen.

The detection result and the value of the command bus [1: m] are judged by the jitter quality judgment processing section 16. If the judgment result is equal to or smaller than the jitter tolerance judgment expected value, PASS,
If the jitter of the PLL circuit 1 is equal to or larger than the allowable judgment expected value, then F
It becomes AIL.

The processing at this time is performed by the command bus [1: m].
The polarity inversion signal and the processing result average value [1: a] of the measurement result averaging processing unit 15 are taken as a logical sum circuit OR24, and the result is subjected to a logical product circuit AND25 to determine pass / fail.

Here, it is assumed that the allowable determination expected value is input as 11000011 (left upper bit, right lower bit) from the command bus [1: 8].

The result of the measurement result averaging unit 15 is 110
It is 00001. The allowable judgment expected value 1 determines that the influence of jitter is not received, and 0 determines that the influence of jitter may be received. Therefore, the measurement result averaging processor 15
Compared with 11000011, the result of the measurement result averaging processing unit 15 is not 0 in the bit having the allowable judgment expected value of 1, so the jitter of the PLL circuit 1 becomes less than the allowable judgment expected value, and therefore the jitter pass / fail signal Outputs a high level which is PASS.

Furthermore, as a third embodiment of the present invention,
It is also possible to inspect the reference clock signal instead of the PLL (multiplication circuit) jitter. FIG. 10 showing the configuration.
Referring to FIG. 2, the difference from the first embodiment is that the PLL
The difference is that the circuit 1 inspects the jitter of the reference clock signal input from the outside.

That is, the PLL circuit 1 and the PLL circuit 1
The internal logic circuit 2 which is supplied with the multiplied clock signal multiplied by and is operated in synchronization with this multiplied clock signal, and the reference clock signal input from the outside are given, and the jitter of the reference clock signal is inspected in response to the command bus. In addition, the jitter inspection circuit 3 of the present invention which outputs a pass / fail judgment signal of the inspection result is provided. The jitter inspection circuit 3 has the same configuration as that of the first embodiment described above.

In the configuration described above, the jitter inspection circuit 3
, The command bus [0] is at a low level (normal operation mode), so that the multiplexer 6 selects the window clock signal and outputs it as the sampling signal. In this example as well, the number of bits of the binary n-bit counter 8 is 8.
Described as a bit.

The binary n-bit counter 8 starts counting after being reset by the rising signal of the sampling signal. The signal to be counted is a signal obtained by performing NAND operation on the reference clock signal in the rising period of the sampling signal by the NAND 7.

The value counted by the binary n-bit counter 8 is written in the FF 9 at the falling timing of the sampling signal.

After initialization, the command bus [0] is set to a high level (jitter quality judgment mode). At this time, the reference clock signal count measurement value of the FF 9 is taken into the FF 10. Referring to FIG. 5, like the write timing to the FF 10, the reference value A [0: k] of the jitter pass / fail judgment circuit 12, which is [04] in this example, becomes that value during the jitter pass / fail judgment mode period thereafter. Is the reference value A [04]
Hold as.

Further, by raising the command bus [0] to a high level, the output of the delay generation circuit 5 is output.
The window clock signal with falling delay is selected by the multiplexer 6 and output as a sampling signal.

That is, the delayed window clock signals 1 to a which are signals obtained by delaying the fall timing of the window clock signal are generated as sampling signals. The subsequent operation is also the second operation described above.
The embodiment is the same as that of Embodiment 1, and the description thereof is omitted here.

Next, as a fourth embodiment of the present invention,
Inside the semiconductor device, a plurality of P's are provided for one logic circuit.
This is an example in the case of including the LL circuit and inspecting the jitter of these PLL circuits.

Referring to FIG. 11 showing its configuration, the difference from the first embodiment is that a plurality of PLL circuits and a multiplexer for selecting one of them are provided.

That is, the PLL circuit 1a, the PLL circuit 1b (circuit having the same function as 1a), and the PLL circuit 1
a multiplexer 32 that selects either a or 1b by a selector signal or a selector bus signal; an internal logic circuit 2 that is supplied with the multiplied clock signal selected by the multiplexer 32 and operates in synchronization with this multiplied clock signal; The multiplied clock signal selected by 32 is provided, the jitter of the multiplied clock signal is inspected in response to the signal of the command bus, and the jitter inspection circuit 3 of the present invention is provided for outputting a pass / fail judgment signal of the inspection result.
The jitter inspection circuit 3 has the same configuration as that of the first and second embodiments described above.

In the configuration described above, the jitter inspection circuit 3
, The command bus [0] is at a low level (normal operation mode), so that the multiplexer 6 selects the window clock signal and outputs it as the sampling signal. In this example as well, the number of bits of the binary n-bit counter 8 is 8.
Described as a bit.

The binary n-bit counter 8 starts counting after being reset by the rising signal of the sampling signal. The signal to be counted is the PLL circuit 1 selected by the multiplexer 32 during the rising period of the sampling signal.
The multiplied clock signal of a or 1b is a signal subjected to the NAND operation by the NAND 7.

The value counted by the binary n-bit counter 8 is written in the FF 9 at the falling timing of the sampling signal.

After the initialization, the command bus [0] is set to the high level (jitter quality judgment mode). At this time, the reference clock signal count measurement value of the FF 9 is taken into the FF 10. The operation thereafter is the same as that of the second embodiment described above, and the description thereof is omitted here, but the PLL circuit 1a is omitted.
When the jitter inspection of 1 is completed, the signal of the selector bus is switched and the above-described operation is repeated to continue the jitter inspection of the PLL circuit 1b.

Next, as a fifth embodiment of the present invention, a plurality of logic circuits and a plurality of P circuits are provided inside the semiconductor device.
This is an example in which an LL circuit is provided.

That is, referring to FIG. 12 showing the configuration of the fifth embodiment, the PLL circuit 1a, the PLL circuit 1b, and the multiplied clock signals of these PLL circuits 1a and 1b are individually supplied, respectively. Internal logic circuits 2a and 2b (circuits having the same function as 2a) that operate in synchronization with the multiplied clock signal of, and a multiplexer 32 that selects one of these PLL circuits 1a and 1b by a selector signal or a signal of a selector bus, The multiplied clock signal selected by the multiplexer 32 is provided, and the jitter of the multiplied clock signal is inspected in response to the signal of the command bus, and the jitter inspection circuit 3 of the present invention is provided for outputting a quality determination signal of the inspection result. . The jitter inspection circuit 3 has the same configuration as that of the first embodiment described above.

In the configuration described above, the jitter inspection circuit 3
, The command bus [0] is at a low level (normal operation mode), so that the multiplexer 6 selects the window clock signal and outputs it as the sampling signal. In this example as well, the number of bits of the binary n-bit counter 8 is 8.
Described as a bit.

The binary n-bit counter 8 starts counting after being reset by the rising signal of the sampling signal. The signal to be counted is a signal obtained by NANDing the multiplied clock signal of the PLL circuit 1a or 1b selected by the multiplexer 32 in the rising period of the sampling signal and in response to the signal of the selector bus by the NAND 7.

The value counted by the binary n-bit counter 8 is written in the FF 9 at the falling timing of the sampling signal.

After initialization, the command bus [0] is set to a high level (jitter quality judgment mode). At this time, the reference clock signal count measurement value of the FF 9 is taken into the FF 10. The operation thereafter is similar to that of the above-described second embodiment, and the description thereof is omitted here, but the PLL circuit 1
When the jitter inspection of a is completed, the signal of the selector bus is switched and the above-described operation is repeated to continue the jitter inspection of the PLL circuit 1b.

Next explained is the sixth embodiment of the invention. FIG. 1 is a block diagram showing the configuration of the sixth embodiment.
With reference to FIG. 3, the difference from the first embodiment is that the multiplied clock signal output from the PLL circuit inside the semiconductor device and the external high-speed clock signal provided from the outside are detected by the jitter inspection circuit. The point of switching depends on the pass / fail judgment signal.

That is, the PLL circuit 1 and the multiplexer 32 which inputs the multiplied clock signal and the external high speed clock signal output from the PLL circuit 1 and selects one of them by the jitter pass / fail judgment signal are selected by the multiplexer 32. An internal logic circuit 2 that receives a multiplied clock signal or a high-speed clock signal and operates in synchronization with any of the supplied clock signals, and a multiplexer 32.
The jitter inspection circuit 3 according to the present invention is provided with which the jitter clock signal selected in step 1 is applied, the jitter of the multiplied clock signal is inspected in response to the signal of the command bus, and a jitter quality determination signal of the inspection result is output. The jitter inspection circuit 3 has the same configuration as that of the first embodiment described above.

In the configuration described above, the jitter inspection circuit 3
, The command bus [0] is at a low level (normal operation mode), so that the multiplexer 6 selects the window clock signal and outputs it as the sampling signal. In this example as well, the number of bits of the binary n-bit counter 8 is 8.
Described as a bit.

The binary n-bit counter 8 starts counting after being reset by the rising signal of the sampling signal. The signal to be counted is a signal obtained by NANDing the multiplied clock signal of the PLL circuit 1 selected by the multiplexer 32 in the NAND 7 in the rising period of the sampling signal.

The value counted by the binary n-bit counter 8 is written in the FF 9 at the falling timing of the sampling signal.

After the initialization, the command bus [0] is set to the high level (jitter quality judgment mode). At this time, the multiplied clock signal count measurement value of the FF 9 is fetched by the FF 10. The subsequent operation is the same as that of the second embodiment described above, and the description thereof is omitted here.

This embodiment is an example in which a high-speed clock is supplied from an external input terminal when the inspection result of the internal PLL circuit is defective.
By providing the multiplexer for selecting the external high speed clock signal, the multiplied clock signal of the PLL circuit and the high speed clock signal from the external input terminal can be switched based on the jitter inspection result of the PLL circuit.

Also in the above-described second to sixth embodiments, the window clock oscillator circuit 4 self-oscillates inside the semiconductor device, and the PL clock is generated in the same manner as in the first embodiment.
The delay generating circuit 5 delays (falls) the falling edge of the window clock signal by performing an operation called sampling in which the falling edge of the L circuit, the frequency divider or the basic clock is taken into the binary n-bit counter. By matching the jitter while changing the falling position of the window clock signal, which is the sampling signal, to obtain the measured value at the time of judging the quality of the jitter, there is no need to change the sampling signal from the outside as in the past, The pass / fail judgment circuit 12 is connected to the outside of the semiconductor device because it performs an operation of comparing an allowable judgment expected value, which is a selected value of jitter given from the command bus [1: m], with a measurement result. Sampler that does not need to input sampling signal from tester and is not affected by input driver jitter Grayed can, operability of the quality determination in the production process of the semiconductor device is improved.

[0164]

As described above, according to the present invention, the jitter tolerance value determining circuit is provided inside and the jitter quality determining method is performed from the outside through the command bus.
The quality of the LL circuit, the frequency divider, or the reference clock signal can be determined without opening the package of the semiconductor device.

Further, a window clock oscillator for generating a window clock signal which is a source of a sampling signal, a delay generating circuit for delaying the falling edge of the window clock signal, a window clock signal and a window clock signal with delay are provided on a command bus [ [0], the multiplexer switches the output signal, and the sampling signal is a NAND circuit for taking the multiplied clock signal into the binary n-bit counter during the high level period.
The binary n-bit counter that counts the multiplied clock signal of the PLL circuit, the divided clock signal of the frequency divider, or the basic clock signal, the flip-flop that stores the binary bit counter value, and the command bus [0] are set to the high level. Flip-flop that stores the measured value as the reference value when judging the quality of jitter, the normal mode and the jitter inspection mode, the command bus for giving the expected value of the jitter tolerance judgment from the outside, and the jitter given from the command bus It consists of a jitter pass / fail judgment circuit that compares the allowable judgment expected value, which is the selected value, with the measurement result, so the judgment can be made only by operating the command bus and checking the jitter pass / fail signal. Judgment of jitter of clock signal or basic clock signal can be judged by simple command input and operation

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a semiconductor device equipped with a jitter inspection circuit according to the present invention.

FIG. 2 is a conceptual diagram of a command bus for transmitting a command supplied from the outside to control a jitter inspection circuit according to the present invention.

FIG. 3 is a circuit diagram of a delay generation circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a jitter quality determination circuit according to the first embodiment of the present invention.

FIG. 5 is a timing chart for explaining the first embodiment of the present invention.

FIG. 6 is a timing chart for explaining counter measurement with a sampling signal (delay 1 to delay 8).

FIG. 7 is a block diagram for explaining processing of the reference value comparison unit 14 in the jitter quality determination circuit 12 according to the first embodiment of the present invention.

FIG. 8 is a block diagram for explaining processing of the measurement result averaging processing unit 15 and the jitter quality determination processing unit 16 in the jitter quality determination circuit 12 according to the first embodiment of the present invention.

FIG. 9 is a block diagram of a second embodiment in which a jitter inspection circuit according to the present invention is applied to jitter inspection of a frequency divider.

FIG. 10 is a block diagram of a third embodiment in which a jitter inspection circuit according to the present invention is applied to a reference clock of external input.

FIG. 11 shows a plurality of PLLs for a jitter inspection circuit according to the present invention.
It is a block diagram of a fourth embodiment applied to the jitter inspection of the circuit.

FIG. 12 shows a jitter inspection circuit according to the present invention including a plurality of PLLs.
It is a block diagram of a fifth embodiment applied to the jitter inspection of the circuit.

FIG. 13 is a block diagram of a sixth embodiment in which the jitter inspection circuit according to the present invention is applied to a control signal for selecting either a PLL circuit or an external high-speed clock signal supplied from the outside.

FIG. 14 is a diagram showing a configuration of an integrated circuit including a conventional PLL circuit.

15 is a timing chart for explaining the operation of FIG.

[Explanation of symbols]

1 PLL circuit 2,2a, 2b logic circuit 3 Jitter inspection circuit 4 Window clock oscillator 5 Delay generation circuit 6,14 multiplexer 7 NAND 8 binary n-bit counter 9,10 FF 11 Command bus block 12 Jitter quality judgment circuit 13a-adic ring counter 14 Reference value comparison unit 15 Measurement result averaging processor 16 Jitter quality judgment processing unit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03L 7/08 H01L 27/04 F H03L 7/08 HF term (reference) 2G132 AA01 AA03 AA11 AB04 AB07 AC03 AE14 AE16 AG08 AG11 AK07 AK08 AK12 AK15 AK18 AK21 AL11 AL12 AL29 5F038 CD06 CD09 DF01 DF11 DT02 DT08 DT17 DT18 EZ20 5J106 AA04 EE11 FF05 FF07 JJ09 KK25 KK32

Claims (33)

[Claims] 1. A phase locked loop (P) for generating a multiplied clock signal for a clock signal of an internal logic circuit.
LL) means and jitter inspecting means for measuring the jitter of the PLL means, and the jitter inspecting means compares the allowable judgment expected value in the command format given from the outside with the jitter measured value of the multiplied clock signal. A semiconductor device equipped with a jitter inspection circuit, which has a function of performing pass / fail judgment with. 2. A function for internally generating a sampling signal for incorporating the multiplied clock signal of the PLL means into a jitter measurement reference value and a binary n-bit counter for generating a measurement value in the jitter inspecting means. A semiconductor device equipped with the jitter inspection circuit according to 1. 3. A delay means for generating a plurality of delay signals in which the falling timing of the sampling signal is changed based on different delay amounts, and a jitter of the sampling signal and the multiplied clock signal in which the delay amount is changed. 3. A semiconductor device equipped with the jitter inspecting circuit according to claim 2, further comprising: a jitter detecting unit that detects the presence or absence of jitter. 4. A phase locked loop (P) for generating a multiplied clock signal for a clock signal of an internal logic circuit.
LL) means and jitter inspecting means for measuring the jitter of the PLL means. The jitter inspecting means samples and samples the multiplying clock signal of the PLL means after lock-in with a sampling signal generated inside. A semiconductor device equipped with a jitter inspection circuit, which has a function of performing a jitter inspection using a measured value as a reference value for judging whether the jitter is good or bad. 5. The jitter inspecting means compares the measured value obtained by measuring the multiplied clock signal with a plurality of delayed sampling signals obtained by delaying the sampling signal, and the reference value for each predetermined period, and thereby jitters. Which one of the delayed sampling signals affected by the above is detected, and the value of the detection result is compared with the allowable judgment expected value input from the outside via the external signal bus terminal to perform the jitter check. A semiconductor device equipped with the jitter inspection circuit according to claim 4, which has a function of performing. 6. The jitter inspecting circuit according to claim 5, wherein the jitter inspecting means has a function of outputting the jitter inspecting result obtained by the comparison calculation processing to the outside through a jitter quality determining terminal and displaying the result. Semiconductor device. 7. A phase locked loop (P) for generating a multiplied clock signal for a clock signal of an internal logic circuit.
LL) means and a jitter inspecting means for measuring the jitter of the PLL means, and the jitter inspecting means compares an allowable judgment expected value of a command format given from the outside of the semiconductor device with a value of the jitter inspection result. A semiconductor device equipped with a jitter inspection circuit, which has a function of performing quality judgment based on the result and also having a function of judging quality of the jitter of the multiplied clock signal of the PLL means or the jitter of the frequency divider divided clock signal. 8. A frequency divider which divides a reference clock signal and outputs the divided divided clock signal to an internal logic circuit, and a jitter test of the divided clock signal is synchronized with a command signal input from the outside. And a divided clock jitter inspection circuit that outputs a jitter pass / fail judgment signal of the inspection result in the inactive state when the inspection result is defective and outputs it in the active state when the inspection result is good. A semiconductor device equipped with a characteristic jitter inspection circuit. 9. A phase locked loop (P) for generating a multiplied clock signal for a clock signal of an internal logic circuit.
LL) means and jitter inspecting means for measuring the jitter of the PLL means, wherein the jitter inspecting means is the multiplied clock signal of the PLL means after lock-in or the P
A jitter inspection circuit having a function of sampling a reference clock signal input to the LL means with a sampling signal generated internally and performing a jitter inspection using the sampled measured value as a reference value for judging whether the jitter is good or bad is mounted. Semiconductor device. 10. A phase locked loop (PLL) which outputs a multiplied clock signal in synchronization with a reference clock signal.
And the jitter inspection of the reference clock signal is performed in synchronization with the command signal input from the outside, and when the inspection result is defective, the jitter quality determination signal of the inspection result is output in the inactive state and it is a good product. A semiconductor device equipped with a jitter inspection circuit, comprising a reference clock jitter inspection circuit for outputting in an active state in some cases. 11. A plurality of phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and a plurality of the PLL means in synchronization with a selector signal externally given through a selector bus. Selecting means for selecting one from among the plurality of PLL means after lock-in, and the jitter checking means for measuring the jitter of the PLL means. A semiconductor device equipped with a jitter inspecting circuit, which has a function of sampling a multiplied clock signal of a PLL means by a sampling signal generated internally and performing a jitter inspection using the sampled measured value as a reference value for judging whether the jitter is good or bad. 12. A first and a second phase-locked loop (PLL) which respectively output a first and a second multiplied clock signal in synchronization with a reference clock signal, and the first and the second multiplied clock signal. One of the two is selected in synchronization with a selector signal input from the outside via a selector bus or a signal of the selector bus, and is output to an internal logic circuit; and the first or the first input from the multiplexer. The jitter inspection of the second multiplied clock signal is performed in synchronization with the command signal input from the outside, and when the inspection result is defective, the jitter quality determination signal of the inspection result is output in the inactive state and it is a good product. In this case, a jitter inspection circuit of a PLL means for outputting in an active state is provided. Mounted semiconductor device. 13. A plurality of phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, a plurality of internal logic circuits provided corresponding to each of the PLL means, and a selector bus from the outside. Selecting means for selecting one of the multiplied clock signals output from the plurality of PLL means in synchronism with the selector signal or the signal of the selector bus given via the selector and the jitter test for measuring the jitter of the PLL means. The jitter inspecting means samples the multiplied clock signal of the PLL means selected by the selecting means of the plurality of PLL means after lock-in with a sampling signal internally generated, and performs the sampled measurement. It has a function to perform the jitter inspection by using the value as the reference value for judging the quality of jitter. A jitter inspection circuit for a semiconductor device equipped with a jitter inspection circuit characterized by the above. 14. A first phase-locked loop (PL) for outputting a first multiplied clock signal to a corresponding internal first logic circuit in synchronization with a first reference clock signal.
L), a second phase-locked loop (PLL) that outputs the second multiplied clock signal to a corresponding internal second logic circuit in synchronization with the second reference clock signal, and the first and the second A multiplexer that selects and outputs one of the two multiplied clock signals in synchronization with a selector signal that is input from the outside via a selector bus, and the first or the second input that is input from the multiplexer.
When the jitter test of the multiplied clock signal is performed in synchronization with the command signal input from the outside, and if the test result is defective, the jitter quality judgment signal of the test result is output in the inactive state A semiconductor device equipped with a jitter inspection circuit, comprising the jitter inspection circuit of the PLL means for outputting in an active state. 15. A phase locked loop (PLL) means for generating an internal clock signal, a selecting means for selecting a multiplied clock signal from the PLL means or an external high speed clock signal, and an oscillation for generating the internal clock signal. Means and jitter inspecting means, wherein the jitter inspecting means performs the jitter inspection of the multiplied clock signal of the PLL means, and if the inspection result is defective, the selecting means is the jitter pass / fail judgment signal of the inspection result. A semiconductor device equipped with a jitter inspection circuit, which has a function of controlling the external high-speed clock signal to selectively output the external high-speed clock signal. 16. A phase locked loop (PLL) which outputs a multiplied clock signal in synchronization with a reference clock signal.
And a PLL that outputs a jitter quality determination signal of the inspection result when the jitter inspection of the multiplied clock signal input from the PLL means is performed in synchronization with a command signal input from the outside and when the inspection result is defective. And a multiplexer for selecting one of the multiplied clock signal and the external high-speed clock signal to be input in synchronism with the jitter quality determination signal to be input to a control terminal, and outputting the signal to an internal logic circuit. A semiconductor device equipped with a jitter inspection circuit comprising: 17. The jitter inspection circuit includes a command bus for transmitting a command signal for giving a normal mode, a jitter inspection mode and a jitter tolerance judgment expected value from the outside, and a window clock signal for generating a sampling signal. A window clock oscillator for generating, a delay generation circuit for delaying a falling timing of the window clock signal, the window clock signal and the delayed delayed window clock signal in synchronization with the mode switching signal of the command bus. A multiplexer for switching and outputting, a binary n-bit counter for counting the multiplied clock signal of the PLL means and outputting it as a measured value of the count result, and the PL during the high level period of the sampling signal at the logical level.
An AND circuit for fetching the multiplied clock signal of the L means into the binary n-bit counter, a first flip-flop for storing the measured value output by the binary bit counter, and the mode switching signal having a high level A second flip-flop for storing the measured value stored in the first flip-flop as a reference value when determining whether or not to allow jitter, and a selected value of jitter given from the command bus. 18. A semiconductor device equipped with the jitter inspection circuit according to claim 1, further comprising a jitter quality determination circuit that compares an expected jitter determination value with the measured value. 18. The command bus is at a low level of a logic level in a normal mode and is at a high level of a logic level in a jitter checking mode of the PLL means, and a logic level indicating a jitter tolerance judgment expected value. 18. The second to nth buses are set in advance.
A semiconductor device equipped with the described jitter inspection circuit. 19. The delay generating circuit inputs the window clock signal in common with the first n-ary ring counter set by a reset signal, repeating counting immediately after resetting the count value by inputting the window clock signal. And inputting signals obtained by delaying the window clock signals by different delay amounts, and generating first to nth delayed window clock signals with respective falling timings of the window clock signals being delayed. The count values output from the nth logical sum circuit and the n-ary ring counter are respectively synchronized with the first to nth selector signals to selectively select the corresponding first to nth delayed window clock signals. 18. A semiconductor device equipped with the jitter inspection circuit according to claim 17, further comprising: 20. The jitter pass / fail judgment circuit includes a reference value comparison unit that compares a measured value of jitter extracted for each of the first to nth sampling signals having different delay times with a reference value, and the reference value comparison unit. A measurement result for detecting a sampling signal affected by jitter by comparing with a reference value for each of the first to nth sampling signals and for each of the first to nth sampling signals based on the comparison result of the value comparison unit. Consists of an averaging processing section and a jitter quality determination processing section that compares the sampling signal affected by the jitter with an expected jitter determination value set from the command bus and outputs the comparison result as a jitter quality determination signal. A semiconductor device equipped with the jitter inspection circuit according to claim 17. 21. The reference value comparing section includes an exclusive NOR circuit for comparing the reference value with the measured value, and first to nth selectors synchronized with an external command signal and the sampling signal. An AND circuit that takes the logic of the signal,
21. The jitter checking circuit according to claim 20, further comprising n sets of reference comparing circuits each including a flip-flop that stores a signal of a comparison result of the exclusive NOR circuit in synchronization with the selector signal output from the AND circuit. Equipped semiconductor device. 22. A ring counter that counts in synchronization with the nth selector signal among the first to nth selector signals, and the first to nth outputs of the ring counter. The outputs of the first to nth flip-flops that store the corresponding outputs of the reference value comparison circuit and the outputs of the first to nth flip-flops are synchronized with each other, and the comparison result is the jitter quality determination processing unit. 21. A semiconductor device equipped with the jitter inspection circuit according to claim 20, having n sets of averaging processing circuits each including an exclusive NOR circuit output to 23. The jitter quality determination processing unit synchronizes with the polarity inversion signal of the least significant bit output of the ring counter in the measurement result averaging processing unit, and for each of the n sets of exclusive NOR circuits. Store each corresponding output n
Number of flip-flops, n OR circuits that take the logic of the corresponding outputs of each of these n flip-flops and the corresponding signals of the command bus, and the outputs of the n OR circuits. 18. A semiconductor device equipped with the jitter inspection circuit according to claim 17, further comprising a logical product circuit that outputs a logical product as a jitter quality signal. 24. A phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and a jitter inspection means for measuring the jitter of the PLL means are provided, and the jitter inspection means externally A method for inspecting a semiconductor device equipped with a jitter inspecting circuit, characterized in that a pass / fail decision is made based on a result of comparison between an allowable decision expected value in a command format given by the above and a measured jitter value of the multiplied clock signal. 25. A sampling operation in which self-oscillation is internally performed, and a falling edge of the multiplied clock signal is taken into an internal jitter measurement reference value and a binary n-bit counter for generating a measurement value in synchronization with the oscillation clock signal. 25. A jitter inspection method for a semiconductor device equipped with a jitter inspection circuit according to claim 24, wherein the reference value and the measured value are generated, and the two are compared to inspect whether or not the jitter of the multiplied clock signal is good. 26. The delay means generates a plurality of delay signals in which the falling timing of the sampling signal is changed based on different delay amounts, and the jitter detection means multiplies the sampling signal with the changed delay amount. 26. The jitter inspection method for a semiconductor device equipped with the jitter inspection circuit according to claim 25, wherein the presence or absence of jitter is detected by comparing with the jitter of the clock. 27. A phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and a jitter inspection means for measuring the jitter of the PLL means are provided, and the jitter inspection means locks the signal. The jitter of a semiconductor device equipped with a jitter inspection circuit characterized in that the multiplied clock of the PLL means after input is sampled with a sampling signal generated internally, and the sampled measured value is used as a reference value for judging whether the jitter is good or bad. Inspection method. 28. A semiconductor device equipped with a jitter inspection circuit according to claim 27, wherein the jitter inspection means outputs the jitter inspection result obtained from the comparison operation processing to the outside through a jitter quality determination terminal and displays the result. Jitter inspection method. 29. A phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and a jitter inspecting means for measuring the jitter of the PLL means are provided. A quality judgment is made based on a result of comparison between an allowable judgment expected value in the form of a command given from the outside of the apparatus and a jitter measurement result, and the jitter of the multiplied clock signal of the PLL means or the jitter of the frequency divider divided clock signal is judged good or bad A method for inspecting jitter in a semiconductor device having a jitter inspecting circuit. 30. A phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and a jitter inspection means for measuring the jitter of the PLL means, the jitter inspection means comprising:
It is characterized in that the PLL multiplied clock after lock-in or the reference clock signal input to the PLL means is sampled by a sampling signal generated internally, and the sampled measured value is used as a reference value for judging whether the jitter is good or not, and a jitter inspection is performed. A jitter inspection method for a semiconductor device equipped with a jitter inspection circuit. 31. A plurality of phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, and a plurality of the PLL means in synchronization with a selector signal given from the outside via a selector bus. It has a selection means for selecting one and a jitter inspection means for measuring the jitter of the PLL means, and the jitter inspection means selects one of the plurality of PLL means after lock-in by the selection means. A jitter inspection method for a semiconductor device equipped with a jitter inspection circuit, characterized in that the multiplied clock signal of the PLL means is sampled by a sampling signal generated internally, and the sampled measured value is used as a reference value for determining the quality of jitter. . 32. A plurality of phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, a plurality of internal logic circuits provided corresponding to each of the PLL means, and a selector bus from the outside. Selecting means for selecting one of the multiplied bi-clock signals output from the plurality of PLL means in synchronism with a selector signal given via
The LL means has a jitter inspecting means for measuring the jitter, and the jitter inspecting means allows the plurality of Ps after the lock-in.
The PLL selected by the selection means of the LL means
A jitter inspection method for a semiconductor device equipped with a jitter inspection circuit, wherein the multiplied clock signal of the means is sampled by a sampling signal generated internally, and the sampled measured value is used as a reference value for determining the quality of jitter. 33. A phase locked loop (PLL) means for generating a multiplied clock signal for a clock signal of an internal logic circuit, a selecting means for selecting the multiplied clock signal from the PLL means or an external high speed clock signal, and the PLL. A jitter inspecting means for measuring the jitter of the means, and the jitter inspecting means performs the jitter inspecting of the multiplied clock signal of the PLL means, and when the inspecting result is defective, the jitter quality judging signal of the inspecting result A method for inspecting a semiconductor device having a jitter inspecting circuit, wherein the selecting means is controlled to selectively output the external high speed clock signal.