JP2002217356A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2002217356A JP2002217356A JP2001010893A JP2001010893A JP2002217356A JP 2002217356 A JP2002217356 A JP 2002217356A JP 2001010893 A JP2001010893 A JP 2001010893A JP 2001010893 A JP2001010893 A JP 2001010893A JP 2002217356 A JP2002217356 A JP 2002217356A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- bonding pads
- stacked
- bonding
- lower semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は基板上に複数の半導体チ
ップを積層して実装する半導体装置に関する。特に、本
発明は、サイズが等しい半導体チップを積層する時に下
層の半導体チップのワイヤボンディングを可能にする半
導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a plurality of semiconductor chips are stacked and mounted on a substrate. In particular, the present invention relates to a semiconductor device that enables wire bonding of a lower semiconductor chip when stacking semiconductor chips of the same size, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来の高密度実装技術の１つとして、プ
リント配線基板上に複数の半導体チップを積層実装する
スタック実装という技術がある。スタック実装では、通
常、プリント配線基板と積層される半導体チップとの接
続が、ワイヤボンディングにより行われる。2. Description of the Related Art As one of conventional high-density mounting techniques, there is a technique called stack mounting in which a plurality of semiconductor chips are stacked and mounted on a printed wiring board. In the stack mounting, the connection between the printed wiring board and the semiconductor chip to be laminated is usually performed by wire bonding.
【０００３】このため、ボンディングパッドを上向きに
したフェースアップ（Ｆａｃｅ Ｕｐ）の状態で、チッ
プサイズの大きな順に半導体チップが積層される。すな
わち、積層される半導体チップでは、大きいサイズの下
層の半導体チップの面のうち、小さいサイズの上層の半
導体チップと接触しない面に、ボンディングパッドが設
けられる。[0005] For this reason, semiconductor chips are stacked in order of chip size in a face-up state in which bonding pads are directed upward. That is, in the stacked semiconductor chips, the bonding pads are provided on the surface of the large-sized lower-layer semiconductor chip that does not contact the small-sized upper-layer semiconductor chip.
【０００４】ところで、サイズが等しい半導体チップを
積層する場合には、下層の半導体チップの全面が上層の
半導体チップにより覆われるので、下層の半導体チップ
にはボンディングパッドを設ける場所が無くなる。従来
技術として、サイズが等しい半導体チップの積層実装に
ついて以下に説明する。図１６は本発明の前提となる半
導体装置の概略を示す断面図である。本図に示すよう
に、半導体装置は、プリント配線基板１に半導体チップ
２００、２１０が積層実装されることにより製造され
る。When stacking semiconductor chips of the same size, the entire surface of the lower semiconductor chip is covered by the upper semiconductor chip, so that there is no place to provide bonding pads on the lower semiconductor chip. As a conventional technique, a stacked mounting of semiconductor chips having the same size will be described below. FIG. 16 is a sectional view schematically showing a semiconductor device which is a premise of the present invention. As shown in the figure, the semiconductor device is manufactured by stacking semiconductor chips 200 and 210 on a printed wiring board 1.
【０００５】プリント配線基板１にはボンディングパッ
ド２１１ａ、２１１ｂ、ボンディングパッド２３１ａ、
２３１ｂが設けられる。半導体チップ２００、２１０の
サイズは等しく、半導体チップ２０１が上層に位置し、
半導体２００が下層に位置する。上層の半導体チップ２
１０の両サイドには、通常とおりフェースアップの状態
で、ボンディングパッド２４１ａ、２４１ｂが設けられ
る。On the printed wiring board 1, bonding pads 211a and 211b, bonding pads 231a,
231b is provided. The sizes of the semiconductor chips 200 and 210 are equal, the semiconductor chip 201 is located in an upper layer,
The semiconductor 200 is located in a lower layer. Upper semiconductor chip 2
Bonding pads 241a and 241b are provided on both sides of the device 10 in a face-up state as usual.
【０００６】下層の半導体チップ２００の両サイドに
は、フェースダウン（Ｆａｃｅ Ｄｏｗｎ）の状態で、
ボンディングパッド２２１ａ、２２１ｂが設けられる。
通常とおり、上層の半導体チップ２１０のボンディング
パッド２４１ａ、２４１ｂとプリント配線基板１のボン
ディングパッド２１１ａ、２１１ｂとがワイヤ２０１
ａ、２０１ｂを用いてワイヤボンディングにより電気的
に接続される。下層の半導体チップ２００のボンディン
グパッド２２１ａ、２２１ｂとプリント配線基板１のボ
ンディングパッド２３１ａ、２３１ｂとが金バンプ２２
０ａ、２２０ｂを用いて熱圧着により電気的に接続され
る。[0006] Both sides of the lower semiconductor chip 200 are face-down (face down).
Bonding pads 221a and 221b are provided.
As usual, the bonding pads 241a and 241b of the upper semiconductor chip 210 and the bonding pads 211a and 211b of the printed wiring board 1
a and 201b are electrically connected by wire bonding. The bonding pads 221a and 221b of the lower semiconductor chip 200 and the bonding pads 231a and 231b of the printed wiring board 1
0a and 220b to be electrically connected by thermocompression bonding.
【０００７】このように、金バンプ２２０ａ、２２０ｂ
の熱圧着を用いて、下層の半導体チップ２００とプリン
ト配線基板１とのボンディングパッド２２０ａ、２２０
ｂ、ボンディングパッド２３１ａ、２３１ｂを電気的に
接続することは、特開平７−３２６７１０号公報に開示
されている。上層の半導体チップ２１０の面と下層の半
導体チップ２００の面は接着剤２０６ｂにより相互に接
着固定される。さらに、下層の半導体２００の面とプリ
ント配線基板１の面は接着剤２０６ａにより相互に接着
固定される。As described above, the gold bumps 220a, 220b
Bonding pads 220a, 220 between lower semiconductor chip 200 and printed wiring board 1 using thermocompression bonding.
b, electrically connecting the bonding pads 231a and 231b is disclosed in Japanese Patent Application Laid-Open No. 7-326710. The surface of the upper semiconductor chip 210 and the surface of the lower semiconductor chip 200 are bonded and fixed to each other by an adhesive 206b. Further, the surface of the lower semiconductor 200 and the surface of the printed wiring board 1 are bonded and fixed to each other by an adhesive 206a.
【０００８】[0008]
【発明が解決しょうとする課題】しかしながら、上記半
導体装置の製造では、下層の半導体チップ２００がフェ
ースダウンでプリント配線基板１に電気的に接続される
ため、下層の半導体チップ２００を熱圧着する際に、下
層の半導体チップ２００が破損したり、フェースダウン
に起因して接続部位の目視確認ができず、歩留りが低下
するという問題がある。However, in the manufacture of the semiconductor device, since the lower semiconductor chip 200 is electrically connected to the printed wiring board 1 face down, the lower semiconductor chip 200 is thermally compressed. In addition, there is a problem that the lower semiconductor chip 200 is damaged, or the connection portion cannot be visually confirmed due to face-down, and the yield decreases.
【０００９】このため、後工程に対する負荷が増大する
という問題が発生する。したがって、本発明は上記問題
点に鑑みて、サイズが等しい半導体チップを積層する際
に、下層の半導体チップとプリント配線基板との熱圧着
による破損防止を可能にし、接続部位の目視確認を可能
にする半導体装置及びその製造方法を提供することを目
的とする。For this reason, there is a problem that the load on the post-process increases. Accordingly, the present invention has been made in view of the above problems, and when laminating semiconductor chips having the same size, it is possible to prevent damage due to thermocompression bonding between a lower semiconductor chip and a printed wiring board, and to visually check a connection portion. And a method of manufacturing the same.
【００１０】[0010]
【課題を解決するための手段】本発明は前記問題点を解
決するために、サイズの等しい半導体チップがプリント
配線基板に積層される半導体装置において、下層の前記
半導体チップと上層の前記半導体チップをずらして積層
することにより積層されない周辺端部にボンディングパ
ッドを形成するためのボンディングパッド用周辺端部
と、下層の前記半導体チップの前記ボンディングパッド
用周辺部に下層の前記半導体チップのボンディングパッ
ドを配置する配線層とを備えることを特徴とする半導体
装置を提供する。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a semiconductor device in which semiconductor chips having the same size are stacked on a printed wiring board, wherein the lower semiconductor chip and the upper semiconductor chip are combined. A bonding pad peripheral end for forming a bonding pad at a peripheral end that is not stacked by being shifted and stacked, and a bonding pad of the lower semiconductor chip are arranged at the bonding pad peripheral part of the lower semiconductor chip. And a wiring layer for the semiconductor device.
【００１１】この手段により、サイズが等しい半導体チ
ップを積層する際に、下層の半導体チップとプリント配
線基板とを熱圧着する必要がなくなり、熱圧着による下
層の半導体チップの破損防止が可能になり、さらに接続
部位の目視確認を可能にでき、歩留まりを向上させるこ
とが可能になる。さらに、本発明は、サイズの等しい半
導体チップがプリント配線基板に積層される半導体装置
において、下層の前記半導体チップと上層の前記半導体
チップをずらして積層することにより積層されない周辺
端部にボンディングパッドを形成するためのボンディン
グパッド用周辺端部と、下層の前記半導体チップの前記
ボンディングパッド用周辺部にボンディングパッドを配
置する配線層とを備えることを特徴とする半導体装置を
提供する。この手段により、通常、上層の半導体チップ
のボンディングパッドはワイヤボンディングが可能であ
るので、配置の必要が無い場合には、下層の半導体チッ
プだけ配置を行うようにできる。好ましくは、前記周辺
部は、それぞれが矩形である下層の前記半導体チップと
上層の前記半導体チップとが積層された状態から上層の
前記半導体チップを１つの辺方向にずらすることによ
り、下層の前記半導体チップに形成される。According to this means, when stacking semiconductor chips of the same size, it is not necessary to thermocompress the lower semiconductor chip and the printed wiring board, and it is possible to prevent the lower semiconductor chip from being damaged by thermocompression. Further, it is possible to visually check the connection portion, and it is possible to improve the yield. Further, in the present invention, in a semiconductor device in which semiconductor chips of the same size are stacked on a printed wiring board, bonding pads are formed on peripheral edges that are not stacked by shifting the lower semiconductor chip and the upper semiconductor chip so as to be stacked. A semiconductor device comprising: a bonding pad peripheral end portion to be formed; and a wiring layer for arranging a bonding pad on the bonding pad peripheral portion of the lower semiconductor chip. By this means, the bonding pads of the upper semiconductor chip can usually be wire-bonded. Therefore, when there is no need to arrange, only the lower semiconductor chip can be arranged. Preferably, the peripheral portion shifts the upper semiconductor chip in one side direction from a state in which the lower semiconductor chip and the upper semiconductor chip each having a rectangular shape are stacked, whereby the lower layer It is formed on a semiconductor chip.
【００１２】この手段により、下層の半導体チップの１
つの辺にボンディングパッドを形成するための周辺端部
が形成可能になる。好ましくは、前記周辺部は、それぞ
れが矩形である下層の前記半導体チップと上層の前記半
導体チップとが積層された状態から上層の前記半導体チ
ップを、例えば、４５度回転してずらすことにより、下
層の前記半導体チップに形成される。By this means, one of the lower semiconductor chips is
A peripheral edge for forming a bonding pad on one side can be formed. Preferably, the peripheral portion is formed by rotating the upper semiconductor chip from a state in which the lower semiconductor chip and the upper semiconductor chip each having a rectangular shape are stacked, for example, by rotating the semiconductor chip by 45 degrees to shift the lower semiconductor chip. Of the semiconductor chip.
【００１３】この手段により、下層の半導体チップの４
つの隅にボンディングパッドを形成するための周辺端部
が形成可能になる。また下層の半導体チップ２上層の半
導体チップの中心が同軸上に積層できるため、半導体チ
ップを積層する際の安定性が増し、各ワイヤが半導体チ
ップの方向に引き出せるので、ワイヤ配線の自由度が増
すという効果が発生する。好ましくは、前記周辺部は、
それぞれが矩形である下層の前記半導体チップと上層の
前記半導体チップとが積層された状態から上層の前記半
導体チップを２つの辺方向にずらすことにより、下層の
前記半導体チップに形成される。By this means, the lower semiconductor chip 4
A peripheral edge for forming a bonding pad can be formed at one corner. Further, since the center of the upper semiconductor chip can be coaxially stacked on the lower semiconductor chip 2, the stability when the semiconductor chips are stacked increases, and each wire can be pulled out in the direction of the semiconductor chip, so that the degree of freedom of wire wiring increases. This produces the effect. Preferably, the peripheral portion is
The lower semiconductor chip is formed on the lower semiconductor chip by shifting the upper semiconductor chip in two side directions from a state in which the lower semiconductor chip and the upper semiconductor chip each having a rectangular shape are stacked.
【００１４】この手段により、下層の半導体チップの２
つの辺にボンディングパッドを形成するための周辺端部
が形成可能になる。好ましくは、前記配線層はポリイミ
ド、アルミニウムにより構成される。この手段により、
配線層の内部に接続線の形成が可能になり、半導体チッ
プのボンディングパッドの位置を、半導体チップ上の任
意の位置に配置しなおすことが可能になる。By this means, the lower semiconductor chip 2
A peripheral edge for forming a bonding pad on one side can be formed. Preferably, the wiring layer is made of polyimide or aluminum. By this means,
The connection lines can be formed inside the wiring layer, and the positions of the bonding pads of the semiconductor chip can be rearranged at any positions on the semiconductor chip.
【００１５】好ましくは、下層の前記半導体チップと上
層の前記半導体チップをずらして半導体チップを２層又
は３層に積層する。この手段により、積層されるサイズ
が等しい半導体チップのワイヤボンディングが可能にな
り、歩留まりを向上しつつ高密度実装が可能になる。好
ましくは、ずらして積層された下層の前記半導体チップ
と上層の前記半導体チップとについて配置されたボンデ
ィングパッドに対応して、プリント配線基板のボンディ
ングパッドを配置する。Preferably, the lower semiconductor chip and the upper semiconductor chip are shifted from each other, and the semiconductor chips are stacked in two or three layers. By this means, wire bonding of semiconductor chips having the same size to be stacked can be performed, and high-density mounting can be performed while improving the yield. Preferably, the bonding pads of the printed wiring board are arranged corresponding to the bonding pads arranged for the lower semiconductor chip and the upper semiconductor chip stacked in a staggered manner.
【００１６】この手段により、積層される半導体チップ
の全てとプリント配線基板とのワイヤボンディングが可
能になる。さらに、本発明は、サイズの等しい半導体チ
ップがプリント配線基板に積層される半導体装置の製造
方法において、下層の前記半導体チップ、上層の前記半
導体チップの周辺部にボンディングパッドを配線層によ
り配置する工程と、下層の前記半導体チップ、上層の半
導体チップの周辺部に配置される前記ボンディングパッ
ドと重ならないように下層の半導体チップと上層の半導
体チップをずらして積層する工程と、下層の前記半導体
チップと上層の前記半導体チップのボンディングパッド
と前記プリント配線基板のボンディングパッドをワイヤ
ボンディングにより電気的に接続することを特徴とする
半導体装置の製造方法を提供する。By this means, it becomes possible to wire-bond all of the stacked semiconductor chips to the printed wiring board. Further, in the present invention, in a method of manufacturing a semiconductor device in which semiconductor chips having the same size are stacked on a printed wiring board, a step of arranging bonding pads in a peripheral portion of the lower semiconductor chip and the upper semiconductor chip by a wiring layer. A step of laminating the lower semiconductor chip and the upper semiconductor chip so as not to overlap with the bonding pads arranged in the peripheral portion of the lower semiconductor chip, and the lower semiconductor chip; A method of manufacturing a semiconductor device, wherein a bonding pad of the upper semiconductor chip and a bonding pad of the printed wiring board are electrically connected by wire bonding.
【００１７】この手段により、上記発明と同様に、サイ
ズが等しい半導体チップを積層する際に、下層の半導体
チップとプリント配線基板とを熱圧着する必要がなくな
り、熱圧着による破損防止が可能になり、接続部位の目
視確認を可能にでき、歩留まりを向上することが可能に
なる。By this means, it is not necessary to thermocompression-bond the lower semiconductor chip and the printed wiring board when stacking semiconductor chips of the same size as in the above invention, and it is possible to prevent damage due to thermocompression. Thus, it is possible to visually check the connection portion, and it is possible to improve the yield.
【００１８】[0018]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。図１は、本発明に係る半導
体装置の概略を示す斜視図である。本図に示すように、
プリント配線基板１には、矩形でありサイズが等しい下
層、上層の半導体チップ２、４がフェースアップ状態
で、重なった状態から相互に平行な辺の方向にずらして
積層実装される。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view schematically showing a semiconductor device according to the present invention. As shown in this figure,
Lower and upper semiconductor chips 2 and 4 which are rectangular and have the same size are stacked and mounted on the printed wiring board 1 in a face-up state while being shifted from the overlapping state in the direction of sides parallel to each other.
【００１９】プリント配線基板１は樹脂を基材として銅
配線による電気回路を内蔵し、半導体チップ２、４は集
積回路を内蔵する。なお、半導体チップ２、４には、複
数のボンディングパッドがそれぞれ設けられ、ボンディ
ングパッドの各々は、半導体チップに内蔵する回路の入
出力端子をそれぞれの表面に引き出す。The printed circuit board 1 has a built-in electric circuit formed by copper wiring using a resin as a base material, and the semiconductor chips 2 and 4 have a built-in integrated circuit. The semiconductor chips 2 and 4 are provided with a plurality of bonding pads, respectively, and each of the bonding pads draws out an input / output terminal of a circuit built in the semiconductor chip to each surface.
【００２０】半導体チップ２、４の表面には配線層３、
５がそれぞれ形成される。配線層３、５は半導体チップ
２、４と等しいサイズに形成され、ポリイミドとアルミ
ニウムの層で積層され、内部に接続線、周辺端部に複数
のボンディングパッドを有し、半導体チップのボンディ
ングパッドを任意の位置に配置することを可能にする。Wiring layers 3 are provided on the surfaces of the semiconductor chips 2 and 4.
5 are formed respectively. The wiring layers 3 and 5 are formed to have the same size as the semiconductor chips 2 and 4 and are laminated with a layer of polyimide and aluminum. The wiring layers 3 and 5 have connection lines inside and a plurality of bonding pads at peripheral edges. It can be arranged at any position.
【００２１】一例として、本図に示すように、配線層３
の左側周辺端部３０に設けられる複数のボンディングパ
ッド３１は、配線層３の内部の接続線で、下層の半導体
チップ２のボンディングパッドと接続することにより、
半導体チップ２のボンディングパッドを左側周辺端部３
０に配置する。同様に、配線層５の右側周辺端部５０に
設けられる複数のボンディングパッド５１は、配線層５
の内部の接続線で、上層の半導体チップ４のボンディン
グパッドと接続することにより、上層の半導体チップ４
のボンディングパッドを右側周辺端部５０に配置する。As an example, as shown in FIG.
A plurality of bonding pads 31 provided at the left peripheral end 30 of the semiconductor chip 2 are connected to the bonding pads of the lower semiconductor chip 2 by connection lines inside the wiring layer 3.
Connect the bonding pad of the semiconductor chip 2 to the left peripheral end 3
Place at 0. Similarly, the plurality of bonding pads 51 provided at the right peripheral edge 50 of the wiring layer 5
Are connected to the bonding pads of the upper semiconductor chip 4 by connection lines inside the upper semiconductor chip 4.
Are arranged at the right peripheral edge 50.
【００２２】上層の半導体チップ４と下層の半導体チッ
プ２とが完全に積層した状態から上層の半導体チップ４
を右側にずらして、下層の半導体チップ２に積層し、接
着剤６ｂで接着固定することにより、下層の半導体チッ
プ２の左周辺端部３０にボンディングパッドが形成され
るようにする。なお、下層の半導体チップ２の表面がプ
リント配線基板１と接着剤６ａで接着固定される。From the state in which the upper semiconductor chip 4 and the lower semiconductor chip 2 are completely stacked, the upper semiconductor chip 4
Are shifted to the right side, and are stacked on the lower semiconductor chip 2 and fixed by bonding with an adhesive 6b, so that a bonding pad is formed at the left peripheral end 30 of the lower semiconductor chip 2. The surface of the lower semiconductor chip 2 is bonded and fixed to the printed wiring board 1 with an adhesive 6a.
【００２３】プリント配線基板１には、配置された複数
のボンディングパッド３１、５１に対応して、複数のボ
ンディングパッド１１ａ、１１ｂがそれぞれ設けられ
る。下層の半導体チップ２、上層の半導体チップ４に配
置された複数のボンディングパッド３１、５１は、複数
のワイヤ１０１ａ、１０１ｂを用いてワイヤボンディン
グにより、プリント配線基板１の複数のボンディングパ
ッド１１ａ、１１ｂにそれぞれ電気的に接続される。The printed wiring board 1 is provided with a plurality of bonding pads 11a and 11b corresponding to the plurality of bonding pads 31 and 51 arranged. The plurality of bonding pads 31 and 51 arranged on the lower semiconductor chip 2 and the upper semiconductor chip 4 are connected to the plurality of bonding pads 11a and 11b of the printed wiring board 1 by wire bonding using a plurality of wires 101a and 101b. Each is electrically connected.
【００２４】なお、半導体チップ２、４とプリント配線
基板１との間の電気配線を行うワイヤ１０１ａ、１０１
ｂは、金、アルミニウム等の極細ワイヤからなる。この
ようして、下層の半導体チップ２と上層の半導体チップ
４をずらして得られる領域に配線層３によりボンディン
グパッド３１を設けるようにしたので、下層の半導体チ
ップ２のワイヤボンディングが可能になる。Wires 101a, 101 for performing electric wiring between the semiconductor chips 2, 4 and the printed wiring board 1.
b is made of an ultrafine wire such as gold or aluminum. In this way, the bonding pads 31 are provided by the wiring layer 3 in the region obtained by shifting the lower semiconductor chip 2 and the upper semiconductor chip 4, so that the lower semiconductor chip 2 can be wire-bonded.
【００２５】すなわち、半導体チップ２、半導体チップ
４に配置されたボンディングパッド３１、５１を全てワ
イヤボンディングすることが可能になる。上層の半導体
チップ４のボンディングパッド５１は、下層の半導体チ
ップ２のボンディングパッド３１と反対側になるように
配置されるので、ワイヤボンディングされるワイヤ１０
１ａと１０１ｂとの干渉を回避することが可能になる。That is, it is possible to wire bond all the bonding pads 31 and 51 arranged on the semiconductor chip 2 and the semiconductor chip 4. Since the bonding pads 51 of the upper semiconductor chip 4 are arranged on the opposite side to the bonding pads 31 of the lower semiconductor chip 2, the wires 10 to be wire-bonded
Interference between 1a and 101b can be avoided.
【００２６】したがって、本発明によれば、従来のよう
に、熱圧着による下層の半導体チップの破損が無くな
り、接続状態の目視確認が可能になり、後工程に対する
負荷が無くなる。図２は図１の線Ａ−Ａについての断面
を示す図である。本図に示すように、下層の半導体チッ
プ２の表側にはボンディングパッド２１ａ、２１ｂ等が
設けられている。配線層３には複数の接続配線３１ａが
設けられ、接続配線３１ａの各々により、配線層３の複
数のボンディングパッド３１と半導体チップ２の複数の
ボンディングパッド２１ａ、２１ｂ等がそれぞれ接続さ
れる。Therefore, according to the present invention, unlike the prior art, damage to the lower semiconductor chip due to thermocompression bonding is eliminated, the connection state can be visually checked, and the load on subsequent steps is eliminated. FIG. 2 is a diagram showing a cross section taken along line AA of FIG. As shown in the figure, bonding pads 21a and 21b are provided on the front side of the lower semiconductor chip 2. A plurality of connection wirings 31a are provided on the wiring layer 3, and the plurality of bonding pads 31 of the wiring layer 3 and the plurality of bonding pads 21a and 21b of the semiconductor chip 2 are connected to each of the connection wirings 31a.
【００２７】配線層５には複数の接続配線５１ａが設け
られ、接続配線５１ａの各々により、配線層５の複数の
ボンディングパッド５１と半導体チップ５の複数のボン
ディングパッド４１ａ、４１ｂ等がそれぞれ接続され
る。なお、通常、上層の半導体チップ４のボンディング
パッドはワイヤボンディングが可能であるので、上層の
半導体チップ４のボンディングパッドを配置しなおす必
要が無い場合には、下層の半導体チップだけ配置しなお
すようにしてもよい。図３は配線層３により下層の半導
体チップ２のボンディングパッドを配置する例を示す図
である。本図（ａ）に示すように、下層の半導体チップ
２の表面周辺端部には、複数のボンディングパッド２１
ａ、２１ｂ、２１ｃ、２１ｄが設けられているとする。A plurality of connection wirings 51a are provided on the wiring layer 5, and each of the connection wirings 51a connects a plurality of bonding pads 51 of the wiring layer 5 and a plurality of bonding pads 41a, 41b of the semiconductor chip 5, respectively. You. In general, since the bonding pads of the upper semiconductor chip 4 can be wire-bonded, if there is no need to rearrange the bonding pads of the upper semiconductor chip 4, only the lower semiconductor chip should be rearranged. You may. FIG. 3 is a diagram showing an example in which bonding pads of the lower semiconductor chip 2 are arranged by the wiring layer 3. As shown in FIG. 3A, a plurality of bonding pads 21 are provided at the peripheral edge of the surface of the lower semiconductor chip 2.
a, 21b, 21c, and 21d are provided.
【００２８】本図（ｂ）に示すように、下層の半導体チ
ップ２とサイズが等しくこれに積層する配線層３の一方
の周辺端部３０、例えば、図中の左側周辺端部３０に複
数のボンディングパッド３１が配置される。周辺端部３
０は下層の半導体チップ２と上層の半導体チップ４（図
１、２参照）により積層されない周辺端部である。配線
層３の複数の配線３１ａにより、配線層３における複数
のボンディングパッド３１と下層の半導体チップ２にお
ける複数のボンディングパッド２１ａ、２１ｂ、２１
ｃ、２１ｄとがそれぞれ接続される。As shown in FIG. 3B, a plurality of wiring layers 3 having the same size as the underlying semiconductor chip 2 and having a plurality of wiring layers 3 stacked thereon are provided at one peripheral end 30, for example, the left peripheral end 30 in the figure. A bonding pad 31 is arranged. Peripheral end 3
Reference numeral 0 denotes a peripheral end portion that is not stacked by the lower semiconductor chip 2 and the upper semiconductor chip 4 (see FIGS. 1 and 2). A plurality of bonding pads 31 in the wiring layer 3 and a plurality of bonding pads 21a, 21b, 21 in the underlying semiconductor chip 2 are formed by the plurality of wirings 31a in the wiring layer 3.
c and 21d are respectively connected.
【００２９】図４は配線層５により上層の半導体チップ
４のボンディングパッドを配置する例を示す図である。
本図（ａ）に示すように、上層の半導体チップ４の表面
周辺端部には、複数のボンディングパッド４１ａ、４１
ｂ、４１ｃ、４１ｄが設けられているとする。本図
（ｂ）に示すように、下層の半導体チップ４とサイズが
等しくこれに積層する配線層５の一方の周辺端部５０、
例えば、図中の右側周辺端部５０に複数のボンディング
パッド５１が配置される。周辺端部５０は下層の半導体
チップ２と上層の半導体チップ４により積層されない周
辺端部である。FIG. 4 is a diagram showing an example in which bonding pads of the upper semiconductor chip 4 are arranged by the wiring layer 5.
As shown in FIG. 3A, a plurality of bonding pads 41a and 41 are provided on the peripheral edge of the surface of the upper semiconductor chip 4.
Assume that b, 41c, and 41d are provided. As shown in FIG. 2B, one peripheral end 50 of the wiring layer 5 which is equal in size to the lower semiconductor chip 4 and stacked thereover,
For example, a plurality of bonding pads 51 are arranged at the right peripheral edge 50 in the drawing. The peripheral end 50 is a peripheral end that is not stacked by the lower semiconductor chip 2 and the upper semiconductor chip 4.
【００３０】配線層５の複数の配線５１ａにより、配線
層５における複数のボンディングパッド５１と上層の半
導体チップ４における複数のボンディングパッド４１
ａ、４１ｂ、４１ｃ、４１ｄとがそれぞれ接続される。
図５は図１におけるプリント配線基板１のボンディング
パッド１１ａ、１１ｂを示す図である。A plurality of bonding pads 51 in the wiring layer 5 and a plurality of bonding pads 41 in the upper semiconductor chip 4 are formed by the plurality of wirings 51 a of the wiring layer 5.
a, 41b, 41c, and 41d are respectively connected.
FIG. 5 is a view showing the bonding pads 11a and 11b of the printed wiring board 1 in FIG.
【００３１】本図に示すように、プリント配線基板１に
は、接着固定される下層の半導体チップ２のボンディン
グパッド３１の位置に対応してボンディングパッド１１
ａが設けられる。これに対して、下層の半導体チップ２
に積層される上層の半導体チップ４のずれを考慮して、
上層の半導体チップ４のボンディングパッド５１に対応
するボンディングパッド１１ｂがプリント配線基板１に
設けられる。As shown in FIG. 1, the printed wiring board 1 has bonding pads 11 corresponding to the positions of the bonding pads 31 of the lower semiconductor chip 2 to be bonded and fixed.
a is provided. On the other hand, the lower semiconductor chip 2
In consideration of the displacement of the upper semiconductor chip 4 laminated on
Bonding pads 11 b corresponding to bonding pads 51 of upper semiconductor chip 4 are provided on printed wiring board 1.
【００３２】なお、上記の説明では、上層の半導体チッ
プ４のボンディングパッド５１は、下層の半導体チップ
２のボンディングパッド３１と対向する側に設けたが、
分散して、積層されている非対向の周辺端部に設けても
よい。配置の柔軟性を確保するためである。図６は図１
の半導体装置の製造方法の概略を説明するフローチャー
トである。In the above description, the bonding pads 51 of the upper semiconductor chip 4 are provided on the side facing the bonding pads 31 of the lower semiconductor chip 2.
They may be dispersed and provided at the non-opposite peripheral edges that are stacked. This is to ensure the flexibility of arrangement. FIG. 6 shows FIG.
4 is a flowchart illustrating an outline of a method for manufacturing a semiconductor device according to the first embodiment.
【００３３】Ｓ４０１：下層、上層の各半導体チップ
２、４のウェハ上に、配線層３、５を形成し、ボンディ
ングパッドの再配置を行う。 Ｓ４０２：各半導体チップをダイシングし、チップ化す
る。S401: Wiring layers 3 and 5 are formed on the wafers of the lower and upper semiconductor chips 2 and 4, and the bonding pads are rearranged. S402: Dicing each semiconductor chip into chips.
【００３４】ステップＳ４０３において、下層の半導体
チップ２をフェースアップ状態でプリント配線基板１に
接着固定する。ステップＳ４０４において、上層の半導
体チップ４をフェースアップ状態で下層の半導体チップ
２にずらして積層し、接着固定する。ステップＳ４０５
において、下層、上層の半導体チップ２、４とプリント
配線基板１とをワイヤボンディングパッドで電気的に接
続する。In step S403, the lower semiconductor chip 2 is bonded and fixed to the printed wiring board 1 in a face-up state. In step S404, the upper semiconductor chip 4 is shifted and stacked on the lower semiconductor chip 2 in a face-up state, and is adhesively fixed. Step S405
, The lower and upper semiconductor chips 2 and 4 and the printed wiring board 1 are electrically connected by wire bonding pads.
【００３５】図７は図１の変形例であり、半導体チップ
を３層に積層する例を示す図である。本図に示すよう
に、半導体チップ４の上にさらにサイズが等しい半導体
チップ３０２が積層される。積層される半導体チップ３
０２は、半導体チップ４のボンディングパッド５１と反
対側にずらして、接着剤３０６ａにより、半導体チップ
４に接着固定される。これにより、下層の半導体チップ
４と重ならない周辺端部３００が半導体チップ表側に形
成される。FIG. 7 is a modification of FIG. 1 and shows an example in which semiconductor chips are stacked in three layers. As shown in the figure, a semiconductor chip 302 having a further equal size is stacked on the semiconductor chip 4. Semiconductor chips 3 to be stacked
Numeral 02 is shifted to the side opposite to the bonding pads 51 of the semiconductor chip 4 and is bonded and fixed to the semiconductor chip 4 with an adhesive 306a. Thus, a peripheral end portion 300 that does not overlap with the lower semiconductor chip 4 is formed on the front side of the semiconductor chip.
【００３６】半導体チップ３０２には配線層３０３が設
けられ、配線層３０３は、周辺端部３００にボンディン
グパッド３３１を形成し、配線３０３ａにより半導体チ
ップ３０２の複数のボンディングパッド３２１ａ、３２
１ｂをボンディングパッド３３１に配列する。配線層３
０３の複数のボンディングパッド３３１は配線層５のボ
ンディングパッド５１とは反対側に位置する。The semiconductor chip 302 is provided with a wiring layer 303. The wiring layer 303 has a bonding pad 331 formed at a peripheral end portion 300, and a plurality of bonding pads 321a, 32 of the semiconductor chip 302 are formed by the wiring 303a.
1b is arranged on the bonding pad 331. Wiring layer 3
The plurality of bonding pads 331 of 03 are located on the opposite side of the wiring layer 5 from the bonding pads 51.
【００３７】これにより、半導体チップ３０２のワイヤ
３０１ａと半導体チップ４のワイヤ１０１ｂが干渉しな
いようになる。このように、サイズが同じ半導体チップ
を３層に積層することにより、さらに、高密度実装が可
能になる。図８は図１の変形例であり、下層の半導体チ
ップ２に対して、中心を共通にして、上層の半導体チッ
プ４を４５度回転して積層し、重ならない４隅の領域に
ボンディングパッドを設置する例を示す図である。Thus, the wires 301a of the semiconductor chip 302 and the wires 101b of the semiconductor chip 4 do not interfere with each other. In this way, by stacking semiconductor chips of the same size in three layers, higher-density mounting is possible. FIG. 8 shows a modification of FIG. 1, in which the upper semiconductor chip 4 is stacked by rotating the upper semiconductor chip 4 by 45 degrees with the center being common to the lower semiconductor chip 2, and bonding pads are formed in the four corner regions where they do not overlap. It is a figure showing the example of installation.
【００３８】本図に示すように、プリント配線基板１に
接着固定された半導体チップ２に対して、半導体チップ
４を４５度回転して積層すると、半導体チップ２、半導
体チップ４にはそれぞれ重ならない４つの隅の周辺端部
７１、７２、７３、７４、周辺端部８１、８２、８３、
８４が形成される。半導体チップ２の４つの隅の周辺端
部７１、７２、７３、７４にそれぞれ設けられた複数の
ボンディングパッドと対応するプリント配線基板１の複
数のボンディングパッドとが、複数のワイヤ７１ｃ、７
２ｃ、７３ｃ、７４ｃを用いて、ワイヤボンディングに
よりそれぞれ電気的に接続される。As shown in this figure, when the semiconductor chip 4 is rotated by 45 degrees with respect to the semiconductor chip 2 bonded and fixed to the printed wiring board 1, the semiconductor chip 2 and the semiconductor chip 4 do not overlap each other. The peripheral edges 71, 72, 73, 74 of the four corners, the peripheral edges 81, 82, 83,
84 is formed. The plurality of bonding pads provided on the peripheral ends 71, 72, 73, and 74 of the four corners of the semiconductor chip 2 and the plurality of bonding pads of the printed wiring board 1 correspond to the plurality of wires 71c and 7 respectively.
Using 2c, 73c, 74c, they are electrically connected by wire bonding.
【００３９】同様に、半導体チップ４の４つの隅の周辺
端部８１、８２、８３、８４にそれぞれ設けられた複数
のボンディングパッドと対応するプリント配線基板１の
複数のボンディングパッドとが、複数のワイヤ８１ｃ、
８２ｃ、８３ｃ、８４ｃを用いてワイヤボンディングに
よりそれぞれ電気的に接続される。図９は図８の半導体
チップ２、配線層３を説明する図である。本図（ａ）に
示すように、下層の半導体チップ２のフェースアップ側
周辺端部には、複数のボンディングパッド２１ａ、２１
ｂ、２１ｃ、２１ｄが設けられているとする。Similarly, a plurality of bonding pads provided on the peripheral edges 81, 82, 83, 84 of the four corners of the semiconductor chip 4 and a plurality of bonding pads of the printed wiring board 1 correspond to a plurality of bonding pads. Wire 81c,
The wires 82c, 83c, and 84c are electrically connected by wire bonding. FIG. 9 is a diagram illustrating the semiconductor chip 2 and the wiring layer 3 of FIG. As shown in FIG. 3A, a plurality of bonding pads 21a and 21
b, 21c, and 21d are provided.
【００４０】本図（ｂ）に示すように、下層の半導体チ
ップ２とサイズが等しくこれに積層する配線層３の４つ
の隅の周辺端部７１、７２、７３、７４には複数のボン
ディングパッド７１ａ、７２ａ、７３ａ、７４ａがそれ
ぞれ配置される。配線層３の複数の配線３１ａにより、
配線層３における複数のボンディングパッド７１ａ、７
２ａ、７３ａ、７４ａと下層の半導体チップ２における
複数のボンディングパッド２１ａ、２１ｂ、２１ｃ、２
１ｄとがそれぞれ接続される。As shown in FIG. 4B, a plurality of bonding pads are provided at the peripheral edges 71, 72, 73, and 74 of the four corners of the wiring layer 3 which are equal in size to the lower semiconductor chip 2 and are stacked thereon. 71a, 72a, 73a and 74a are respectively arranged. By the plurality of wirings 31a of the wiring layer 3,
A plurality of bonding pads 71a, 7 in the wiring layer 3
2a, 73a, 74a and a plurality of bonding pads 21a, 21b, 21c, 2
1d are connected respectively.
【００４１】図１０は図８の半導体チップ４、配線層５
を説明する図である。半導体チップ４、配線層５は中心
を共通にして半導体チップ２、配線層３に対して４５度
回転した状態にある。本図（ａ）に示すように、下層の
半導体チップ２のフェースアップ側周辺端部には、複数
のボンディングパッド４１ａ、４１ｂ、４１ｃ、４１ｄ
が設けられているとする。FIG. 10 shows the semiconductor chip 4 and the wiring layer 5 of FIG.
FIG. The semiconductor chip 4 and the wiring layer 5 are rotated by 45 degrees with respect to the semiconductor chip 2 and the wiring layer 3 with the center in common. As shown in FIG. 3A, a plurality of bonding pads 41a, 41b, 41c, 41d are provided at the peripheral edge of the lower semiconductor chip 2 on the face-up side.
Is provided.
【００４２】本図（ｂ）に示すように、下層の半導体チ
ップ２とサイズが等しくこれに積層する配線層３の４つ
の隅の周辺端部８１、８２、８３、８４には複数のボン
ディングパッド８１ａ、８２ａ、８３ａ、８４ａがそれ
ぞれ配置される。配線層５の複数の配線５１ａにより、
配線層５における複数の８１ａ、８２ａ、８３ａ、８４
ａボンディングパッドと下層の半導体チップ２における
複数のボンディングパッド４１ａ、４１ｂ、４１ｃ、４
１ｄとがそれぞれ接続される。As shown in FIG. 4B, a plurality of bonding pads are provided at the peripheral edges 81, 82, 83 and 84 of the four corners of the wiring layer 3 which are equal in size to the lower semiconductor chip 2 and are stacked thereover. 81a, 82a, 83a and 84a are respectively arranged. By the plurality of wirings 51a of the wiring layer 5,
A plurality of 81a, 82a, 83a, 84 in the wiring layer 5
a bonding pads and a plurality of bonding pads 41a, 41b, 41c, 4 in the lower semiconductor chip 2
1d are connected respectively.
【００４３】図１１は図８におけるプリント配線基板１
のボンディングパッドを示す図である。本図に示すよう
に、プリント配線基板１には、接着固定される下層の半
導体チップ２の４つ隅の周辺端部７１、７２、７３、７
４ではボンディングパッド７１ａ、７２ａ、７３ａ、７
４ａに対応してボンディングパッド７１ｂ、７２ｂ、７
３ｂ、７４ｂがそれぞれ設けられる。FIG. 11 shows the printed wiring board 1 shown in FIG.
FIG. 4 is a view showing a bonding pad of FIG. As shown in the figure, the printed wiring board 1 has peripheral edges 71, 72, 73, 7 at four corners of a lower semiconductor chip 2 to be bonded and fixed.
4, the bonding pads 71a, 72a, 73a, 7
4a, the bonding pads 71b, 72b, 7
3b and 74b are provided respectively.
【００４４】これに対して、プリント配線基板１には、
下層の半導体チップ２に回転して積層される上層の半導
体チップ４の隅の周辺端部８１、８２、８３、８４では
８１ａ、８２ａ、８３ａ、８４ａボンディングパッドに
対応してボンディングパッド８１ｂ、８２ｂ、８３ｂ、
８４ｂがそれぞれ設けられる。このようにして、下層の
半導体チップ２と上層の半導体チップ４を、それらの中
心が同軸上になるように、積層できるため、半導体チッ
プを積層する際の安定性が増し、各ワイヤ７１ｃ、７２
ｃ、７３ｃ、７４ｃ、８１ｃ、８２ｃ、８３ｃ、８４ｃ
が半導体チップの４方向に引き出せるので、ワイヤ配線
の自由度が増すという効果が発生する。On the other hand, the printed wiring board 1 has
At the peripheral edge portions 81, 82, 83, 84 of the corners of the upper semiconductor chip 4 which is rotated and stacked on the lower semiconductor chip 2, bonding pads 81b, 82b, 81a, 82a, 83a, 84a correspond to the bonding pads 81a, 82a, 83a, 84a. 83b,
84b are provided respectively. In this way, the lower semiconductor chip 2 and the upper semiconductor chip 4 can be stacked so that their centers are coaxial, so that the stability in stacking the semiconductor chips increases, and the wires 71c, 72
c, 73c, 74c, 81c, 82c, 83c, 84c
Can be drawn out in four directions of the semiconductor chip, so that the effect of increasing the degree of freedom of wire wiring is produced.
【００４５】図１２は図１の変形例であり、下層の半導
体チップ２と上層の半導体チップ４を完全に積層した状
態から直交する辺の方向にずらして積層し、重ならない
周辺端部３０、５０にボンディングパッドを設置する例
を示す図である。本図に示すように、プリント配線基板
１に接着固定された半導体チップ２に対して、半導体チ
ップ４を完全に積層した状態から直交する辺の方向にず
らして積層することにより、例えば、半導体チップ２に
重ならない領域が図中の参照番号３０で示す左側周辺端
部と上側周辺端部に形成され、半導体チップ４に重なら
ない領域が図中の参照番号５０で示す右側周辺端部と下
側周辺端部に形成される。FIG. 12 is a modification of FIG. 1, in which the lower semiconductor chip 2 and the upper semiconductor chip 4 are stacked in a direction of the orthogonal side from the state of being completely stacked, and the peripheral end portions 30 which do not overlap each other. FIG. 5 is a diagram showing an example in which a bonding pad is provided at 50. As shown in this figure, by laminating semiconductor chips 4 on a semiconductor chip 2 bonded and fixed to a printed wiring board 1 in a direction of an orthogonal side from a state in which the semiconductor chips 4 are completely laminated, for example, 2 are formed at the left peripheral edge and the upper peripheral edge indicated by reference numeral 30 in the figure, and the area not overlapping the semiconductor chip 4 is defined by the right peripheral edge and the lower side indicated by reference numeral 50 in the figure. It is formed at the peripheral end.
【００４６】半導体チップ２の左側及び上側周辺端部３
０にそれぞれ設けられた複数のボンディングパッドと対
応するプリント配線基板１の複数のボンディングパッド
とが、複数のワイヤ１０１ａ、１０１ｃを用いてワイヤ
ボンディングによりそれぞれ電気的に接続される。同様
に、半導体チップ４の右側及び下側周辺端部５０にそれ
ぞれ設けられた複数のボンディングパッドと対応するプ
リント配線基板１の複数のボンディングパッドとが、複
数のワイヤ１０１ｂ、１０１ｄを用いてワイヤボンディ
ングによりそれぞれ電気的に接続される。The left and upper peripheral edges 3 of the semiconductor chip 2
The plurality of bonding pads of the printed wiring board 1 are electrically connected to the plurality of bonding pads of the printed wiring board 1 by wire bonding using the plurality of wires 101a and 101c. Similarly, a plurality of bonding pads provided on the right and lower peripheral ends 50 of the semiconductor chip 4 and a plurality of bonding pads of the printed wiring board 1 are wire-bonded using a plurality of wires 101b and 101d. Are electrically connected to each other.
【００４７】図１３は図１２の半導体チップ２、配線層
３を説明する図である。本図（ａ）に示すように、下層
の半導体チップ２の表面周辺端部には、複数のボンディ
ングパッド２１ａ、２１ｂ、２１ｃ、２１ｄが設けられ
ているとする。本図（ｂ）に示すように、下層の半導体
チップ２とサイズが等しくこれに積層する配線層３の左
側及び上側周辺端部３０に複数のボンディングパッド３
１、３２が配置される。FIG. 13 is a diagram for explaining the semiconductor chip 2 and the wiring layer 3 of FIG. As shown in FIG. 2A, it is assumed that a plurality of bonding pads 21a, 21b, 21c, and 21d are provided at the peripheral edge of the surface of the lower semiconductor chip 2. As shown in FIG. 2B, a plurality of bonding pads 3 are provided on the left and upper peripheral edges 30 of the wiring layer 3 which is equal in size to the lower semiconductor chip 2 and is stacked thereon.
1, 32 are arranged.
【００４８】配線層３の複数の配線３１ａにより、配線
層３における複数のボンディングパッド３１、３２と下
層の半導体チップ２における複数のボンディングパッド
２１ａ、２１ｂ、２１ｃ、２１ｄとがそれぞれ接続され
る。図１４は図１２の半導体チップ４、配線層５を説明
する図である。本図（ａ）に示すように、上層の半導体
チップ４の表面周辺端部には、複数のボンディングパッ
ド４１ａ、４１ｂ、４１ｃ、４１ｄが設けられていると
する。The plurality of wires 31a of the wiring layer 3 connect the plurality of bonding pads 31 and 32 of the wiring layer 3 to the plurality of bonding pads 21a, 21b, 21c and 21d of the lower semiconductor chip 2, respectively. FIG. 14 is a diagram illustrating the semiconductor chip 4 and the wiring layer 5 of FIG. As shown in FIG. 2A, it is assumed that a plurality of bonding pads 41a, 41b, 41c, and 41d are provided at the peripheral edge of the surface of the upper semiconductor chip 4.
【００４９】本図（ｂ）に示すように、下層の半導体チ
ップ２とサイズが等しくこれに積層する配線層３の右側
及び下側周辺端部５０には複数のボンディングパッド５
１、５２が配置される。配線層５の複数の配線５１ａに
より、配線層５における複数の５１、５２ボンディング
パッドと下層の半導体チップ２における複数のボンディ
ングパッド４１ａ、４１ｂ、４１ｃ、４１ｄとがそれぞ
れ接続される。As shown in FIG. 4B, a plurality of bonding pads 5 are provided on the right and lower peripheral ends 50 of the wiring layer 3 which is equal in size to the lower semiconductor chip 2 and is laminated thereon.
1, 52 are arranged. The plurality of wirings 51a of the wiring layer 5 connect the plurality of bonding pads 51 and 52 of the wiring layer 5 and the plurality of bonding pads 41a, 41b, 41c and 41d of the underlying semiconductor chip 2, respectively.
【００５０】図１５は図１２におけるプリント配線基板
１のボンディングパッドを示す図である。本図に示すよ
うに、プリント配線基板１には、接着固定される下層の
半導体チップ２の左側及び上側周辺端部３０のボンディ
ングパッド３１、３２に対応してボンディングパッド１
１ａ、１１ｃがそれぞれ設けられる。FIG. 15 is a view showing the bonding pads of the printed wiring board 1 in FIG. As shown in the figure, the printed wiring board 1 has bonding pads 1 corresponding to the bonding pads 31 and 32 of the left and upper peripheral edges 30 of the lower semiconductor chip 2 to be bonded and fixed.
1a and 11c are provided respectively.
【００５１】これに対して、プリント配線基板１には、
上層の半導体チップ４の右側及び下側周辺端部５０の５
１、５２ボンディングパッドに対応してボンディングパ
ッド１１ｂ、１１ｄがそれぞれ設けられる。On the other hand, the printed wiring board 1 has
5 of the right and lower peripheral edges 50 of the upper semiconductor chip 4
Bonding pads 11b and 11d are provided corresponding to the 1 and 52 bonding pads, respectively.
【００５２】[0052]
【発明の効果】以上説明したように、本発明によれば、
下層の半導体チップ、上層の半導体チップの周辺部にボ
ンディングパッドを配線層により配置し、下層の半導体
チップ、上層の半導体チップの周辺部に配置されるボン
ディングパッドと重ならないように下層の半導体チッ
プ、上層の半導体チップをずらして積層し、下層の半導
体チップ、上層の半導体チップのボンディングパッドと
プリント配線基板のボンディングパッドをワイヤボンデ
ィングにより電気的に接続するようにしたので、サイズ
が等しい半導体チップを積層する際に、下層の半導体チ
ップとプリント配線基板とを熱圧着にする必要がなくな
り、熱圧着による破損防止が可能になり、接続部位の目
視確認を可能にでき、歩留まりを向上させることが可能
になる。As described above, according to the present invention,
A lower semiconductor chip, a bonding pad arranged in a peripheral portion of the upper semiconductor chip by a wiring layer, a lower semiconductor chip, a lower semiconductor chip so as not to overlap with a bonding pad arranged in a peripheral portion of the upper semiconductor chip, The upper semiconductor chip is shifted and stacked, and the lower semiconductor chip, the bonding pad of the upper semiconductor chip and the bonding pad of the printed wiring board are electrically connected by wire bonding, so that semiconductor chips of the same size are stacked. In this case, there is no need to apply thermocompression bonding between the lower semiconductor chip and the printed wiring board, preventing damage due to thermocompression bonding, enabling visual confirmation of connection sites, and improving yield. Become.
【図１】本発明に係る半導体装置の概略を示す斜視図で
ある。FIG. 1 is a perspective view schematically showing a semiconductor device according to the present invention.
【図２】図１の線Ａ−Ａについての断面を示す図であ
る。FIG. 2 is a diagram showing a cross section taken along line AA of FIG. 1;
【図３】配線層３により下層の半導体チップ２のボンデ
ィングパッドを配置する例を示す図である。FIG. 3 is a diagram showing an example in which bonding pads of a lower semiconductor chip 2 are arranged by a wiring layer 3;
【図４】配線層５により上層の半導体チップ４のボンデ
ィングパッドを配置する例を示す図である。FIG. 4 is a diagram showing an example in which bonding pads of an upper semiconductor chip 4 are arranged by a wiring layer 5;
【図５】図１におけるプリント配線基板１のボンディン
グパッド１１ａ、１１ｂを示す図である。FIG. 5 is a view showing bonding pads 11a and 11b of the printed wiring board 1 in FIG.
【図６】図１の半導体装置の製造方法の概略を説明する
フローチャートである。FIG. 6 is a flowchart illustrating an outline of a method of manufacturing the semiconductor device of FIG. 1;
【図7】図１の変形例であり、半導体チップを３層に積
層する例を示す図である。FIG. 7 is a modification of FIG. 1 and shows an example in which semiconductor chips are stacked in three layers.
【図８】図１の変形例であり、下層の半導体チップ２に
対して、中心を共通にして、上層の半導体チップ４を４
５度回転して積層し、重ならない４隅の領域にボンディ
ングパッドを設置する例を示す図である。FIG. 8 is a modification of FIG. 1, in which the upper semiconductor chip 4 is connected to the lower semiconductor chip 2 with a common center.
It is a figure which shows the example which rotates 5 degrees, laminates, and installs a bonding pad in the area | region of four corners which do not overlap.
【図９】図８の半導体チップ２、配線層３を説明する図
である。9 is a diagram illustrating a semiconductor chip 2 and a wiring layer 3 of FIG.
【図１０】図８の半導体チップ４、配線層５を説明する
図である。FIG. 10 is a diagram illustrating a semiconductor chip 4 and a wiring layer 5 of FIG.
【図１１】図８におけるプリント配線基板１のボンディ
ングパッドを示す図である。11 is a diagram showing bonding pads of the printed wiring board 1 in FIG.
【図１２】図１の変形例であり、下層の半導体チップ２
と上層の半導体チップ４を完全に積層した状態から２方
向にずらして積層し、重ならない領域にボンディングパ
ッドを設置する例を示す図である。FIG. 12 is a modification of FIG. 1 and shows a lower semiconductor chip 2;
FIG. 11 is a diagram showing an example in which the semiconductor chip 4 and the upper semiconductor chip 4 are stacked while being shifted in two directions from a state in which the semiconductor chips 4 are completely stacked, and bonding pads are provided in non-overlapping regions.
【図１３】図１２の半導体チップ２、配線層３を説明す
る図である。FIG. 13 is a diagram illustrating a semiconductor chip 2 and a wiring layer 3 of FIG.
【図１４】図１２の半導体チップ４、配線層５を説明す
る図である。FIG. 14 is a diagram illustrating a semiconductor chip 4 and a wiring layer 5 of FIG.
【図１５】図１２におけるプリント配線基板１のボンデ
ィングパッドを示す図である。15 is a diagram showing bonding pads of the printed wiring board 1 in FIG.
【図１６】本発明の前提となる半導体装置の概略を示す
断面図である。FIG. 16 is a sectional view schematically showing a semiconductor device which is a premise of the present invention.
１…プリント配線基板 ２、４、３０２…半導体チップ ３、５、３０３…配線層 ６ａ、６ｂ、３０６ａ…接着剤 １１ａ、１１ｂ、１１ｃ、１１ｄ、２１ａ、２１ｂ、２
１ｃ、２１ｄ、４１ａ、４１ｂ、４１ｃ、４１ｄ、３
１、３２、５１、５２、７１ａ、７２ａ、７３ａ、７４
ａ、７１ｂ、７２ｂ、７３ｂ、７４ｂ、８１ａ、８２
ａ、８３ａ、８４ａ、８１ｂ、８２ｂ、８３ｂ、８４
ｂ、３１１ａ、３２１ａ、３２１ｂ、３３１、…ボンデ
ィングパッド ３０、５０、７１、７２、７３、７４、８１、８２、８
３、８４、３００…周辺端部 ３１ａ、５１ａ、３０３ａ…接続線 １０１ａ、１０１ｂ、１０１ｃ、１０１ｄ、３０１ａ、
７１ｃ、７２ｃ、７３ｃ、７４ｃ、８１ｃ、８２ｃ、８
３ｃ、８４ｃ…ワイヤDESCRIPTION OF SYMBOLS 1 ... Printed wiring board 2, 4, 302 ... Semiconductor chip 3, 5, 303 ... Wiring layer 6a, 6b, 306a ... Adhesive 11a, 11b, 11c, 11d, 21a, 21b, 2
1c, 21d, 41a, 41b, 41c, 41d, 3
1, 32, 51, 52, 71a, 72a, 73a, 74
a, 71b, 72b, 73b, 74b, 81a, 82
a, 83a, 84a, 81b, 82b, 83b, 84
b, 311a, 321a, 321b, 331,... bonding pads 30, 50, 71, 72, 73, 74, 81, 82, 8
3, 84, 300 ... peripheral end portions 31a, 51a, 303a ... connection lines 101a, 101b, 101c, 101d, 301a,
71c, 72c, 73c, 74c, 81c, 82c, 8
3c, 84c ... wire
Claims (9)
配線基板に積層される半導体装置において、 下層の前記半導体チップと上層の前記半導体チップをず
らして積層することにより積層されない周辺端部にボン
ディングパッドを形成するためのボンディングパッド用
周辺端部と、 前記ボンディングパッド用周辺部に下層の前記半導体チ
ップ、上層の半導体チップのボンディングパッドを配置
する配線層とを備えることを特徴とする半導体装置。In a semiconductor device in which semiconductor chips having the same size are stacked on a printed wiring board, bonding pads are formed on peripheral edges that are not stacked by shifting the lower semiconductor chip and the upper semiconductor chip so as to be stacked. And a wiring layer for arranging bonding pads of the lower semiconductor chip and the upper semiconductor chip in the peripheral portion of the bonding pad.
配線基板に積層される半導体装置において、 下層の前記半導体チップと上層の前記半導体チップをず
らして積層することにより積層されない周辺端部にボン
ディングパッドを形成するためのボンディングパッド用
周辺端部と、 下層の前記半導体チップの前記ボンディングパッド用周
辺部にボンディングパッドを配置する配線層とを備える
ことを特徴とする半導体装置。2. A semiconductor device in which semiconductor chips having the same size are stacked on a printed wiring board, wherein a bonding pad is formed at a peripheral end portion where the lower semiconductor chip and the upper semiconductor chip are displaced from each other and are not stacked. And a wiring layer for arranging a bonding pad in a peripheral portion of the lower semiconductor chip for the bonding pad.
層の前記半導体チップと上層の前記半導体チップとが積
層された状態から上層の前記半導体チップを平行な辺の
方向にずらすることにより、下層の前記半導体チップに
形成されることを特徴とする、請求項１又は請求項２に
記載の半導体装置。3. The peripheral portion, by shifting the upper semiconductor chip in a direction of parallel sides from a state in which the lower semiconductor chip and the upper semiconductor chip each having a rectangular shape are stacked, 3. The semiconductor device according to claim 1, wherein the semiconductor device is formed on a lower semiconductor chip.
層の前記半導体チップと上層の前記半導体チップとが積
層された状態から上層の前記半導体チップを回転してず
らすことにより、下層の前記半導体チップに形成される
ことを特徴とする、請求項１又は請求項２に記載の半導
体装置。4. The semiconductor device according to claim 1, wherein the peripheral portion is formed by rotating and shifting the upper semiconductor chip from a state where the lower semiconductor chip and the upper semiconductor chip each having a rectangular shape are stacked. The semiconductor device according to claim 1, wherein the semiconductor device is formed on a chip.
層の前記半導体チップと上層の前記半導体チップとが積
層された状態から上層の前記半導体チップを直交する辺
の方向にずらすることにより、下層の前記半導体チップ
に形成されることを特徴とする、請求項１又は請求項２
に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the peripheral portion is shifted from a state in which the lower semiconductor chip and the upper semiconductor chip each having a rectangular shape are stacked, in a direction of a side orthogonal to the upper semiconductor chip. 3. The semiconductor device according to claim 1, wherein the semiconductor chip is formed on the lower semiconductor chip.
3. The semiconductor device according to claim 1.
により構成されることを特徴とする、請求項１又は請求
項２に記載の半導体装置。6. The semiconductor device according to claim 1, wherein said wiring layer is made of polyimide or aluminum.
導体チップをずらして半導体チップを２層又は３層に積
層することを特徴とする、請求項１に記載の半導体装
置。7. The semiconductor device according to claim 1, wherein the lower semiconductor chip and the upper semiconductor chip are displaced from each other and the semiconductor chips are stacked in two or three layers.
ップと上層の前記半導体チップとについて配置されたボ
ンディングパッドに対応して、プリント配線基板のボン
ディングパッドを配置することを特徴とする、請求項１
又は請求項２に記載の半導体装置。8. The printed wiring board according to claim 1, wherein bonding pads arranged on the lower semiconductor chip and the upper semiconductor chip stacked in a staggered manner are arranged. 1
Alternatively, the semiconductor device according to claim 2.
配線基板に積層される半導体装置の製造方法において、 下層の前記半導体チップ、上層の前記半導体チップの周
辺部にボンディングパッドを配線層により配置する工程
と、 下層の前記半導体チップ、上層の半導体チップの周辺部
に配置される前記ボンディングパッドと重ならないよう
に下層の半導体チップと上層の半導体チップをずらして
積層する工程と、 下層の前記半導体チップと上層の前記半導体チップのボ
ンディングパッドと前記プリント配線基板のボンディン
グパッドをワイヤボンディングにより電気的に接続する
ことを特徴とする半導体装置の製造方法。9. A method for manufacturing a semiconductor device in which semiconductor chips having the same size are stacked on a printed wiring board, wherein a bonding pad is arranged by a wiring layer around the lower semiconductor chip and the upper semiconductor chip. Stacking the lower semiconductor chip and the upper semiconductor chip so as not to overlap with the bonding pads arranged in the peripheral portion of the lower semiconductor chip and the upper semiconductor chip; and stacking the lower semiconductor chip and the upper layer Wherein the bonding pad of the semiconductor chip and the bonding pad of the printed wiring board are electrically connected by wire bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001010893A JP2002217356A (en) | 2001-01-19 | 2001-01-19 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001010893A JP2002217356A (en) | 2001-01-19 | 2001-01-19 | Semiconductor device and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002217356A true JP2002217356A (en) | 2002-08-02 |
Family
ID=18878119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001010893A Pending JP2002217356A (en) | 2001-01-19 | 2001-01-19 | Semiconductor device and method of manufacturing the same |
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| Country | Link |
|---|---|
| JP (1) | JP2002217356A (en) |
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| US7989960B2 (en) | 2008-02-08 | 2011-08-02 | Renesas Electronics Corporation | Semiconductor device |
| US8754534B2 (en) | 2008-02-08 | 2014-06-17 | Renesas Electronics Corporation | Semiconductor device |
| TWI453889B (en) * | 2008-02-08 | 2014-09-21 | Renesas Electronics Corp | Semiconductor device |
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| US9377825B2 (en) | 2008-02-08 | 2016-06-28 | Renesas Electronics Corporation | Semiconductor device |
| JP2013128019A (en) * | 2011-12-16 | 2013-06-27 | Renesas Electronics Corp | Semiconductor device |
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