JP2002158289A - On-chip trim-link sensing latch circuit for fuse-link - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit comprising a pulse generator which generates a pulse that continues for a prescribed period. SOLUTION: A first switch 26 controlled by the pulse transmits a current to a fuse-like 30 if the pulse takes a first logical level. The first switch 26 prevents the current from entering the pulse-link 30 if the pulse takes a second logical level. A latch 16 is connected to the fuse-link 30 and sense the logical level generated between the pulses. The latch 16 may be cleared by the leading edge of the pulse. The logical level generated at the fuse-link 30 by the current transmitted is latched in the latch 16 by the trailing edge of the pulse, thereby representing whether the fuse-link 30 is blown out or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to integrated circuits, and more particularly, to an on-chip trim link sense latch circuit for a fuse link.

[0002]

2. Description of the Related Art Integrated circuits that require trimming of critical circuit parameters often perform the trimming using fuse links. The fuse link is a low-impedance material, and can be blown like a fuse by sending a large current through the fuse link, or can be left as it is, that is, it can not be blown. Blowing or leaving a fuse link is known as programming and typically occurs when an integrated circuit is tested after manufacture. During testing, the fuse link is programmed to trim parameters such as current, voltage, or frequency to overcome manufacturing variations and generate based on the correct parameters.

[0003] Metal fuse links have a low impedance in the unblown state, and are "blown" or "open" by passing a current large enough to destroy the fuse link, resulting in a high impedance. Thus, an unblown fuse link assumes a first logic state and a blown fuse link assumes a second, opposite logic state. Fusing the fuse link reduces the fuse link impedance, typically 10-5.
Change from a relatively low impedance in the range of 00 ohms to a relatively high impedance, ideally in the megaohm range. When a fuse link is blown, the resulting impedance can be significantly different, with some blown fuse links exhibiting impedances as low as 3-5 kilo-ohms.

[0004] Determining whether a fuse link is blown or not has been typically performed using an analog sense amplifier. However, analog sense amplifiers have the disadvantage that there is a threshold level of sensitivity within the range of impedance that a blown fuse link may have and cannot sense an impedance less than the threshold or minimum impedance. I have. As a result, if an analog sense amplifier is used to determine whether a fuse link is blown or not, even if the fuse link is actually blown,
A false indication that the fuse link is not blown can result. In addition, sense amplifiers require biasing to operate properly.

[0005]

SUMMARY OF THE INVENTION The threshold level of sensitivity is
It would be desirable to have an improved technique for sensing whether a fuse link is blown or not blown without having the disadvantage of being within the range of impedances that a blown fuse link may have.

[0006]

According to the present invention, an integrated circuit includes a pulse generator that generates pulses of a predetermined duration. The first switch is controlled by a pulse and sends a current through the fuse link when the pulse assumes a first logic level. The first switch switches the pulse to the second
To prevent the current from flowing into the fuse link. The latch is coupled to the fuse link,
The logic level generated during the pulse is sensed. The latch may be cleared by the leading edge of the pulse. The logic level generated at the fuse link by the delivered current is latched into the latch by the trailing edge of the pulse and indicates whether the fuse link has been blown or not blown.

[0007]

FIG. 1 is a block diagram of a portion of an integrated circuit 10 including an on-chip trim link sense latch circuit 12, according to an exemplary embodiment of the present invention. Input signal 14 transitioning from logic high to logic low
Initiates the operation of a trim link sensing latch circuit that determines whether a particular fuse link is blown, but the invention is not so limited. The input signal 14 clears the latch 16 at the leading edge or the like, and is supplied to the monostable multivibrator 18 as an input. The monostable multivibrator 18 has a delay of 2
0 and an exclusive OR (XOR) gate 22. The monostable multivibrator 18 has one stable state (here a logic low) that can remain indeterminate and a pseudo-stable state (here a logic high) triggered by the input signal 14. Monostable multivibrator 18, sometimes called a one-shot circuit, remains in a pseudo-stable state for a predetermined period of time equal to the length of delay 20.
After a predetermined period, the monostable multivibrator 1
8 returns to the stable state and stays there, and the other input signal 1
Wait for 4. The monostable multivibrator 18 provides an output 24 which is a pulse, the width of which is determined by the length of the delay 20.

Output 24 drives both first switch 26 and second switch 28. After the period established by delay 20 has elapsed, latch 16 is clocked at the CLK input to latch in the state of node N1. At the same time, monostable 18 transitions to a stable state, changing output 24 from a logic high to a logic low.

When output 24 is a logic low, trim link sense latch circuit 12 does not sense whether fuse link 30 is blown or not blown. If the output 24 is in a logic low state, such as during the stable state of the monostable multivibrator 18, the first switch 26 is opened to disconnect the fuse link 30 from the power / current source 32 and the second switch 28 Closed to couple node N1 to a reference potential 38 such as ground, but the reference potential is not limited to ground. Coupling node N1 to reference potential 38 carries the voltage at node N to prevent the possibility of falsely indicating whether fuse link 30 is blown.

When output 24 is a logic high, trim link sense latch circuit 12 senses whether fuse link 30 is blown or not blown. Output 2 such as during the quasi-stable state of monostable multivibrator 18
When 4 is a logic high state, the first switch 26 is closed to couple the power / current source 32 to the fuse link 30 and the second switch 28 is opened to isolate the node N1 from the reference potential 38.

The fuse link 30 is either blown or not blown. Fuse link 3
If 0 is not blown, the voltage developed at node N1 will be small due to the low impedance of fuse link 30. The small voltage thus generated does not rise to a voltage level sufficient to be recognized as a logic high state. As a result, the voltage generated at node N1 does not set latch 16 to a logic high and latch output 34
Goes to a logic low, indicating that the fuse link 30 is not blown. Latch 16 may provide a complementary latch output.

When the fuse link 30 is blown, the blown fuse link 30 operates as a high impedance. Very little current flows from power / current source 32 to reference potential 38 via node N1.
The voltage developed at node N1 rises to the voltage level of power / current source 32 minus the voltage drop through first switch 26. The voltage developed at node N1 rises to a voltage level sufficient to be recognized as a logic high state at the input to latch 16,
The output of latch 16 is set to a logic high, indicating that fuse link 30 is blown.

In this method, the monostable multivibrator 1
8 drives a first switch 26, which can be switched to supply current to the fuse link 30. Latch 1
6 senses the voltage generated through the fuse link,
It detects whether the generated voltage is a logic low because it does not exceed the logic level threshold or is a logic high because it exceeds the logic level threshold. Node N
The logic state of the voltage generated at 1 is latched by latch 16 and the sensing circuit is powered down when the monostable transitions to a stable state and outputs a logic low at output 24.

FIG. 2 shows a conceptual diagram of the on-chip trim link sensing latch circuit 212. Where the functions of the components are similar, the same reference numbers are used. Simplified circuit symbols have been used for n-channel and p-channel MOS field effect transistors.

A monostable multivibrator 218 provides an output 224 that drives transistors M1 and M2 simultaneously. Transistor M2 is an n-channel MOS field effect transistor (MOSFET) that is turned on when output 224 is a logic low to couple node 2N1 to a reference potential 238, such as ground, and turned off when output 224 is a logic high. Reference potential 2 from node 2N1
The bond to 38 is removed. Transistor M1 is a p-channel MOSFET that turns on when output 224 is a logic high, coupling node 2N1 to the _VDD supply,
When the output 224 is a logic low, it turns off and the node 2
Isolate N1 from the _VDD supply.

When transistor M1 is turned on, current flows through the source and drain paths of transistor M1 to node 2N1, current limiting resistor RL2, and fuse link 230. The magnitude of the current depends on the combined impedance of fuse link 230 and current limiting resistor RL2, and the conduction path impedance of transistor M1.

When transistor M1 turns on, fuse link 230 can be sensed as either unblown or blown. When the fuse link 230 is not blown, the voltage generated at the node 2N1 is the voltage at the transistor M1,
Determined by the current flowing through the current limiting resistor RL2 and the fuse link 230, the fuse link 23
A voltage is generated through an impedance of zero. Because the impedance of the unblown fuse link is relatively low, the voltage at node 2N1 is sufficient to be detected as a logic high at the D input of latch 216 and at the input of inverter 240 if inverter 240 is present. Does not go up to the level. Therefore, the voltage at the D input of latch 216 will
Being within a logic low when clocked at the end of 20. Subsequently, the logic low state is latched in latch 216 and provided to the Q output.

Inverter 240 has a high input impedance so as not to load node 2N1. Node 2N1 can directly drive the D input of latch 216,
Inverters 240 and 242 provide predetermined buffering and driving of latch 216. Although a single inverter can provide buffering and drive functions,
When two inverters are connected, the logic state input to the D input of latch 216 and the logic state of the Q output of latch 216 are:
The logic state becomes the same as the logic state of node 2N1. However, the present invention is not limited to this.

When fuse link 230 is blown, the impedance of fuse link 230 is high and the voltage developed at node 2N1 rises to _VDD minus the voltage drop across transistor M1 and current limiting resistor RL2. . Thus, the voltage level at node 2N1 rises to a level significantly above ground and is sensed by inverter 240 as a logic high,
The output of inverter 240, which is the input to inverter 242, transitions to a logic low. A logic low at the input of inverter 242 causes the output of inverter 242 coupled to the D input of latch 216 to transition to a logic high.
If the number of inverters between node 2N1 and the D input of latch 216 is even, the D input to
The logic state will be the same as that sensed at N1, but the invention is not so limited. Latch 1
6 latches the state of the D input and provides that state at the Q output of latch 16 and also provides the complementary state of the D input to the complementary output of latch 16.

When latch 216 latches the state of node 2N1, output 22 of monostable multivibrator 218
4 changes state, transistor M1 turns off, transistor M2 turns on, and the next input signal 214
Is held at the reference potential 238 until is supplied to the trim link latch circuit 212. Node 2N1
In this case is a logic low in this case, and it is desirable to include a transistor M2 so that the level at which the voltage at node 2N1 is transmitted and detected is not accurate.

The current limiting resistor RL2 is present to limit the current when the impedance of the fuse link 230 and the conduction path impedance of the transistor M1 are small. The current limiting function can be provided by selecting a transistor M1 having a finite conduction path impedance of appropriate magnitude.

The detection of a blown or not blown fuse link occurs within a period established by delay 220. The length of the time delay 220 is such that the logic state is node 2
Must be long enough to be established at N1. Although 10-20 nanoseconds is sufficient, the delay is typically set in the range of 1 microsecond. Latch 216
Holds the state of node 2N1 until the link sensing latch circuit is turned off and the latch is cleared. Those skilled in the art will be able to design complementary circuits that use voltages of opposite polarity to that shown in FIG.

FIG. 3 is a block diagram illustrating the use of a single monostable multivibrator to drive a plurality of trim link sensing latch circuits in which the output of each trim link sensing latch circuit can be used independently. A single monostable multivibrator 318 driven by a single input signal 314
Are N link sense latch circuits 318a, 318b,.
..Drive 318n.

An integrated circuit may have hundreds of trim link sensing latch circuits. Turning on multiple trim-link sensing latch circuits, each drawing current, simultaneously can cause undesirable large currents, so using a state machine as shown in FIG. 4 to implement multiple monostable multivibrators. It is desirable to sequence. N state machine 450 receives start signal 452 and sequences through the N states. Each of the N states is an input signal 414a, 414b,.
, And the input signals initiate monostable multivibrators 418a, 418b,..., 418n, respectively.
Each of the N monostable multivibrators activates a plurality of link sensing latch circuits 412-1-1 to 412-NM. In this manner, the current drawn to sense the state of the fuse link in the integrated circuit is distributed over the time required by the N state machines 450 to sequence through the plurality of monostable multivibrators. You. Subsequently, the current draw is distributed over time and the maximum current drawn is less. Further, not all link sense latch circuits need to have pulses of the same duration. A large number of monostable multivibrators can accommodate pulses of various durations.

FIG. 5 is a conceptual diagram of an alternative embodiment of an on-chip trim link sensing latch circuit in which the latch function is performed by a weak feedback inverter in a circuit complementary to the circuit shown in FIG. . Monostable multivibrator 518 receives input signal 514 transitioning from a logic high to a logic low and initiates operation of trim link sense latch circuit 512. Monostable multivibrator 5
18 is a high impedance inverter that generates a pulse 524 output and does not load node 5N1;
Generate an appropriate voltage level that is above or below the threshold of inverter 560. Inverters 562 and 564
Drives the fuse link 530 with the same logic state as the output from the monostable multivibrator 518.

When fuse link 530 is not blown, the output of inverter 564 is lowered by a low impedance to ground provided by fuse link 530, and the voltage developed at node 5N1 is lower than the threshold of inverter 560. Stay as it is. Subsequently, the voltage at node 5N1 is sensed as a logic low state, indicating that fuse link 530 is not blown.

When the fuse link 530 is blown, the inverters 562 and 564 use the logic state output from the monostable multivibrator 518 to output the fuse link 53.
Drive 0. Fuse link 530 is high impedance to ground and the voltage at node 5N1 rises substantially to the level provided by monostable multivibrator 518 or the output of inverter 516 if inverter 516 is present. . Thus, the voltage level at node 5N1 exceeds the threshold of inverter 560 and is sensed as a logic high state, indicating that fuse link 530 is blown.

[0028] Resistor RL3 is a current limiting resistor, and transistor 566 provides a path to ground for the current passing through RL3. The input signal 514 may provide an erase signal to the latch.

When delay 520 times out and transitions high, the logic state of node 5N1 is latched by the remainder of trim link sense latch circuit 512 and output 534.
Provided to When the output from delay 520 transitions high, transistor 568 turns on and inverter 5
The output from 60 is passed to the latch formed by inverters 570 and 572. Note that the logic level at the output of inverter 560 is the opposite of the logic level at node 5N1. Inverters 570 and 5
The latch formed by 72 is an inverting type latch in that the output is the opposite form of the input. Thus, the logic state at output 534 is
This is the same logical state as the logical state of node 5N1. A logic low is present at output 534 when fuse link 530 is not blown. A logic high is provided at output 534 when fuse link 530 is blown.

Although the embodiment of the invention shown in FIG. 1 has been described as receiving an input signal transitioning from a logic high to a logic low, the invention is not so limited. Transistors other than MOSFET transistors,
It can be used in the present invention.

[Brief description of the drawings]

FIG. 1 is a block diagram of a part of an integrated circuit showing an on-chip trim link sensing latch circuit for a fuse link according to the present invention.

FIG. 2 is a conceptual diagram of a portion of an integrated circuit illustrating an on-chip trim link sensing latch circuit for a fuse link according to the present invention.

FIG. 3 is a block diagram of a portion of an integrated circuit showing a plurality of on-chip trim link sensing latch circuits driven by a single, monostable multivibrator.

FIG. 4 is a block diagram of a portion of an integrated circuit showing a number of monostable multivibrators, each driving one or more trim link sensing latch circuits.

FIG. 5 is a conceptual diagram of an alternative embodiment of an on-chip trim link sensing latch circuit where the latch function is performed by a weak feedback inverter.

[Explanation of symbols]

 Reference Signs List 10 integrated circuit 12 on-chip trim link sensing latch circuit 14 input signal 16 latch 18 monostable multivibrator 20 delay 22 exclusive OR (XOR) gate 24 output 26 first switch 28 second switch 30 fuse link 32 power / current Source 34 Latch output 38 Reference potential

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Mark K. Lesser United States 19541 Pennsylvania, Mooresville, Dale Drive 14 (72) Inventor Douglas Day. Lopata United States 19512 Pennsylvania, Boyertown, Red Shale Drive 84 F-term (reference) 5F038 AV06 AV15 DF01 DT11 DT13 DT19 EZ20

Claims (14)

[Claims] 1. A pulse generator for generating a pulse of a predetermined duration, a fuse link, and a first switch controlled by the pulse, the fuse link being at a first logic level when the pulse takes a first logic level. A first switch for sending current into the fuse link to prevent current flow into the fuse link when the pulse assumes a second logic level; and a logic switch coupled to the fuse link for generating a logic level generated during the pulse. A latch for sensing, wherein the latch is cleared by a leading edge of the pulse, the logic level generated at the fuse link is latched by the latch by a trailing edge of the pulse, and the logic latched by the latch Latch indicating if the fuse link is blown or not blown Integrated circuit comprising a. 2. The system further comprising a second switch, the second switch being controlled by the pulse, the second switch securing the fuse link when the pulse takes the second logic level. The integrated circuit of claim 1, coupled to a reference, wherein the second switch separates the fuse link from the fixed reference when the pulse takes the first logic level. 3. The system of claim 1, further comprising a current limiting impedance in a current path including the first switch and the fuse link, wherein the current limiting impedance limits an amount of current that can be sent to the fuse link. 2. The integrated circuit according to 1. 4. The integrated circuit according to claim 1, wherein said pulse generator is a monostable multivibrator. 5. The integrated circuit according to claim 1, wherein said first logic level is a logic high. 6. The integrated circuit according to claim 1, wherein said pulse generator is a monostable multivibrator. 7. A pulse generator for generating a pulse of a predetermined duration; and a plurality of trim link sensing latch circuits triggered by the pulse, each of the trim link latch circuits comprising: a fuse link; A first switch controlled by the pulse switch to send current to the fuse link when the pulse assumes a first logic level, and to flow current into the fuse link when the pulse assumes a second logic level. And a latch coupled to the fuse link for sensing a logic level generated on the fuse link during the pulse, wherein the logic level generated on the fuse link is controlled by the pulse. The logic level latched in the latch and the logic level latched in the latch Integrated circuit click includes a latch indicating whether not blown or is blown. 8. Each of the plurality of trim link latch circuits further comprises a second switch, each of the second switches being controlled by the pulse, each of the second switches being configured to output the pulse with the pulse. Combine each fuse link to each reference when taking a logic level of 2,
The integrated circuit of claim 7, wherein said respective fuse link is separated from said respective reference when said pulse takes said first logic level. 9. A state machine having a plurality of pulse generators, each generating a respective pulse, and a number of states corresponding to the number of pulse generators in the plurality of pulse generators. And at least one of the plurality of pulse generators in each state.
Starting from one pulse generator, the pulse generators are configured to sequence states, each of which is a state machine that generates a respective pulse; and a plurality of trim link sensing latch circuits, at least one of which Comprises a trim link sensing latch circuit triggered by each of the pulse generators, each of the trim link latch circuits being a fuse link, and a first switch controlled by the pulse, wherein the pulse is the first switch. A first switch that sends current to the fuse link when it takes a logic level of one, and prevents current from flowing into the fuse link when the pulse takes a second logic level; A logic level sensing logic level generated at the fuse link during the pulse. Wherein the logic level generated at the fuse link is latched in the latch by the pulse, and the logic level latched in the latch indicates whether the fuse link is blown or not blown. And an integrated circuit. 10. The integrated circuit according to claim 9, wherein the correspondence between the number of states of the state machine and the number of pulse generators is one-to-one. 11. A method for determining whether a fuse link is blown or not blown, comprising: generating a pulse having a first state and a second state; Sending a current to the fuse link during the first state; detecting a voltage generated through the fuse link during the first state as exceeding a logic device threshold and taking a first logic level. Detecting that the second logical level has not been exceeded without exceeding the threshold value of the logical device; and one of the first logical level and the second logical level.
Storing as a representation of the voltage developed across the fuse link. 12. The method according to claim 11, wherein said first state is a high state. 13. The method of claim 11, wherein sending current to the fuse link is accomplished by supplying the generated pulse to the fuse link. 14. The method of claim 1, further comprising the step of resetting the logic level representing a voltage generated through the fuse link when the pulse is being generated.
2. The method according to 1.