JP2001136142A - Digital transmitter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an OFDM transmission system that can always detect synchronization by accurately estimating a SWEEP symbol start position even under any transmission state without being affected by presence/absence of a reflecting wave or a noise component. SOLUTION: A data transmitter employing an orthogonal frequency division multiplex modulation system revises a threshold value to detect an end part of a non-signal period used to detect frame synchronization for each prescribed period depending on the transmission state, applies trough modulation to main wave when the CN is a prescribed value or over so as to reduce a time required for complete synchronization and aims first at establishing of the synchronization when the CN is low on the other hand thereby realizing a normal synchronization operation to the main wave in a short time under wider condition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an orthogonal frequency division multiplex (OFDM).
ex) It relates to a digital transmission device using a modulation method.

[0002]

2. Description of the Related Art In recent years, digital broadcasting has been studied in Europe, the United States, and Japan, and the adoption of an OFDM modulation system as a modulation system is considered to be promising. This O
The FDM modulation method is a type of multi-carrier modulation method and is a combination of a large number of digitally modulated waves. At this time, QPSK (Q
An uadrature Phase Shift Keying (four-phase phase shift keying) method or the like is used, and an OFDM signal that is a synthetic wave can be obtained. Here, when this OFDM signal is expressed by a mathematical formula,
It looks like this: First, assuming that the QPSK signal of each carrier is α _k (t), this can be expressed by equation (1). α _k (t) = _ak (t) · cos (2πkft) + b _k (t) · sin (2πkft) (1) where k indicates a carrier number and a _k (t) , B _k (t)
Is the data of the k-th carrier and takes a value of [-1] or [1]. Next, assuming that the number of carriers is N, the OFDM signal is a combination of N carriers, and if this is β _k (t), this can be expressed by the following equation (2). β _k (t) = Σα _k (t) (where k = 1 to N) (2) By the way, in the OFDM modulation method, a guard interval is added to a signal in order to reduce the influence of multipath. It is common to add. That is, as shown in FIG. 4, in the effective symbol period Ts, at least one of the waveform of the start portion and the end portion of the effective symbol is used as the guard interval Tg. Here, (a) of FIG.
1 shows an OFDM signal when a guard interval Tg is added to the end of the effective symbol period Ts. FIG. 4B shows the end of the effective symbol period Ts when k = 1 to 544. 2 shows an OFDM signal when a guard interval Tg is added to the OFDM signal. This O
The FDM signal is composed of the above signal unit. The signal unit symbol is, for example, 1010 samples obtained by adding 48 samples of guard interval data to 1024 samples of valid samples.
It consists of repetition of a stream unit called a frame consisting of 900 symbols in which 6 sets of synchronization symbols are added to 894 sets of symbols of 72 samples.

FIG. 5 is a block diagram showing a basic configuration of a modulation / demodulation unit in an OFDM transmission apparatus according to the prior art, which includes a transmission line encoding unit 1T, an encoding unit 2T, and an IFFT (Inv
erseFast Fourier Transform) section 3
A, a transmission side processing unit 1 including a guard addition unit 3B, a synchronization symbol insertion unit 5, a clock oscillator 6, and a quadrature modulation processing unit 8.
01, and a quadrature demodulation processor 9, FFT
(Fast Fourier Transform) section 3C,
The receiving side processing unit 203 including the decoding unit 2R, the transmission line decoding unit 1R, and the voltage controlled clock oscillator 10, and the synchronization detector 4
And the receiving side Rx having
x and the receiving side Rx are connected by, for example, a wireless transmission path L using radio waves. Hereinafter, the modulation / demodulation processing of the OFDM signal will be described with reference to FIG. Data Din that is continuously input to the transmission path encoding unit 1T of the transmission processing unit 10
Is processed for each frame of, for example, 900 symbols, and within this frame period, every 894 information symbols excluding 6 synchronization symbol periods, for a total of 800 sample periods 1 to 400 and 625 to 1024 Is output as the rate-converted data Dii in the intermittent state.

[0004] Further, the transmission path coding section 1T generates a frame control pulse FST on the transmission side for every 900 symbols, which is a frame period, and supplies the frame control pulse FST to other blocks as a frame pulse signal indicating the start of a synchronization symbol period. I do.
The encoding unit 2T encodes the input data Dii,
The data Rf and If mapped to two axes of the axis and the Q axis are output. The IFFT unit 3A regards these data Rf and If as frequency components and converts them into a time axis signal R (real component) and I (imaginary component) consisting of 1024 samples. The guard adding unit 3B adds, for example, the waveform of the first 48 samples after 1024 samples among the waveforms in the start period of the time axis signals R and I consisting of 1024 samples, for a total of 1024 samples.
It outputs information symbols Rg and Ig consisting of a 72-sample time axis waveform. These 48 samples serve as a buffer band when a reflected wave is mixed. The synchronizing symbol insertion unit 5 inserts a synchronizing waveform composed of 6 symbols, which is stored in a memory or the like in advance, into these information symbols Rg and Ig every 894 samples, and converts the frame-structured data Rsg and Isg. create. These data Rsg and Isg are output to the quadrature modulation processing unit 8.
Where the D / A converter 81 and the quadrature modulator 8
2. The local oscillator 83 generates the OFDM modulated wave signal RF by the carrier of the frequency Fc, amplifies it at a high frequency, and sends it out to the transmission line L. As a transmission band, a UHF band or a microwave band is used. The clock CK (frequency 1) required for processing on the transmitting side Tx
6 MHz) is supplied from the clock oscillator 6 to each block as the transmission side clock CKd.

[0005] The OFDM modulated wave signal RF transmitted as described above is input to the quadrature demodulation processing section 9 of the reception side Rx, where the quadrature demodulator 91 outputs the voltage-controlled oscillator 9.
After being multiplied by the local signal of the frequency Fc 'supplied from the base station 3 and orthogonally demodulated into the baseband signal, the A / D converter 9
2 and converted into data R'sg and I'sg. These data R'sg and I'sg are obtained by FFT (Fas
t Fourier Transform) is supplied to the fast Fourier transform section 3C, where a gate signal for determining a data period of 1024 samples to be used as an FFT based on the pulse FSTrc is created, and 48 samples that are a buffer band are excluded. , The time axis waveform signals R′sg and I′sg are converted into frequency component signals R′f and I′f. Then, these frequency component signals R'f and I'f are identified and decoded by the decoding unit 2R, become data D'o, and output as a continuous signal Dout by the transmission line decoding unit 1R. You. On the other hand, the data R ′
The sg and I'sg are also input to the synchronization detector 4, where a synchronization symbol group is detected, and a pulse FSTr serving as a frame pulse is extracted. This pulse FS
Tr becomes a frame control pulse of the receiving side Rx and is supplied to each block of the receiving side Rx. Further, the synchronization detector 4 compares the clock CKr generated from the voltage control clock oscillator 10 with the synchronization components of the data R'sg and I'sg, and generates a control voltage VC according to the comparison result. The voltage-controlled clock oscillator 10 is controlled, and a clock CKr having a correct cycle is generated and supplied to each block on the receiving side.

Next, details of each block shown in FIG. 5 will be described. The transmission line encoding unit 1 is designed to prevent data errors due to various errors that may be mixed during transmission.
It performs interleave processing, energy diffusion processing, error correction code processing, and the like. The encoding unit 2T converts the signal Dii into information of a predetermined point on the I and Q axes using a mapping ROM, and replaces a signal in a period corresponding to an unnecessary carrier with 0 to generate data Rf and If. I do. IFFT converter 3
A sets the input signals Rf and If to the clock CK and the pulse F
The signal is converted into time-domain waveforms R and I of a symbol cycle whose timing is determined by ST. Specifically, it can be realized by using PDSP16510 or the like from Pressy. The guard adding unit 3B includes a delay unit that delays the input signals R and I by 1024 samples, and a first delay unit from the 1025th sample.
A switch for selecting a delay output only for the 072th sample is provided, and the timing of these switches is determined by the clock CK and the pulse FST. Total 1072 obtained here
A symbol composed of samples is added with a time-axis waveform between the first sample and the 48th sample from the 1025th sample to the 1072th sample, and becomes information symbols Rg and Ig. Next, an example of the synchronization symbol insertion unit 5 is shown in FIG. First, the ROMs 5-1 and 5-2 store the controller 5 whose timing is determined by the clock CK and the pulse FST.
-5, thereby generating a synchronization symbol signal at a timing corresponding to the pulse FST. Similarly, SEL5-3 and SEL5 are a clock CK and a pulse FST, respectively.
Is controlled by the controller 5-6 whose timing is determined by the time information symbol signals Rg and Ig with guard.
At this stage, only the period from 1 symbol to 6 symbols, which is a no-signal period, is switched to the synchronous symbol signal read out from the ROMs 5-1 and 5-2 and output. Here, as the synchronization symbol signal, for example, there is no signal during one symbol period, and a null (NULL) symbol for roughly finding the existence of the synchronization symbol group, the signal component is applied to only one carrier during one symbol period. Symbol (hereinafter, referred to as CW symbol) which does not have a symbol, is a waveform that changes from the lower limit frequency of the transmission band to the upper limit frequency in one symbol period, and is a sweep (SWEEP) symbol for accurately determining a symbol switching point. , A reference symbol (hereinafter, referred to as a reference symbol) indicating a phase reference necessary for performing differential detection and demodulation. When there are six sets of synchronization symbols, two additional spare symbols are added to the above.

Next, a supplementary description of the quadrature modulation processing unit 8 will be given with reference to FIG. 5. D / A converter 81 performs D / A conversion on the signal Rsg of the real part and the signal Isg of the imaginary part, and performs quadrature conversion. The modulator 82 modulates the real part signal with the carrier signal of the frequency fc from the oscillator 83 as it is, and shifts the carrier signal of the frequency 83 of the oscillator 83 by 90 ° with respect to the imaginary part signal. Signals are subjected to quadrature modulation, and these signals are combined to form an OFDM signal.
Obtain a modulated wave signal. Next, the configuration operation of the receiving side Rx will be described. On the receiving side Rx, the transmitted signal of the frame configuration is first input to the quadrature demodulation processing unit 9. The processing here is performed by the quadrature demodulator 91 in a manner opposite to the transmitting side.
The output demodulated by the carrier signal of the frequency Fc ′ output from the voltage controlled oscillator 93 is extracted as a real part signal, and the output obtained by shifting the phase of the carrier signal by 90 ° is extracted as an imaginary part signal. Then, the demodulated analog signals of the real part and the imaginary part are converted by the A / D converter 9.
2 to convert to a digital signal. The synchronization detector 4
From the received signals R'sg and I'sg, a frame break is searched for, and a pulse FSTr serving as a frame reference is output. Then, the FFT unit 3C separates symbols based on the pulse FSTr, performs OFDM demodulation by performing Fourier transform as described above, and outputs data R'f and I'f. The decoding unit 2R identifies the data R'f and I'f by, for example, a ROM table method and calculates the data D'o. The transmission path decoding unit 7 performs deinterleaving processing, energy despreading processing, error correction processing, and the like.

Next, FIG. 7 shows an example of a specific configuration of the synchronization detector 4 and will be described. The time axis signals R'sg and I'sg, which are the digital signals subjected to the quadrature demodulation, are output from the NULL end detector 4.
-1 and are input to the SWEEP operation unit 4-2. NULL
The end detector 4-1 detects a null in a no-synchronous state in the synchronization symbol from the symbol group of the frame configuration, detects a rough position (timing) of the synchronization symbol, and
The SWEEP symbol start time is estimated by the timer circuit from the LL end time, and a SWEEP start instruction pulse ST is output. The SWEEP calculation section 4-2 refers to the SWEEP start instruction pulse ST, estimates a waveform existing two symbols after the NULL symbol as a SWEEP symbol waveform, captures the waveform, and searches for an accurate switching timing of each symbol. More specifically, the input OFDM signal and the pattern read from the memory 4-3 are subjected to, for example, a correlation operation using the memory 4-3 in which the pattern of the SWEEP symbol is stored in advance, and the matching state of the two signal patterns is determined. Then, a phase shift from the estimated SWEEP waveform is calculated by calculation, and a correction signal VC for adjusting the reference clock CKr on the receiving side is output to match the frame phase on the receiving side with the transmission data. Frame counter 4-4
Starts counting the clock CK based on the SWEEP start instruction pulse ST, and outputs a pulse FSTr every time the count reaches a value (for example, 1072 × 900) corresponding to the frame period. After the value is returned to 0, counting of the clock CK is started again. Therefore, thereafter, the pulse FSTr is output at every fixed count, that is, at each frame start point,
On the receiving side, the pulse FSTr is used as the start timing of fast Fourier transform, decoding, and inverse rate conversion.

Next, a specific configuration of the NULL end detector 4-1 and details of the SWEEP start position estimating process will be described with reference to FIGS. The signals R'sg and I'sg supplied to the NULL end detector 4-1 are output to absolute value circuits 4-1-1 and 4-1.
The absolute value is converted into an absolute value by -2 and added by an adder 4-1-3 to obtain an absolute value added output 4A. The absolute value addition output 4A is compared with a threshold value Vth in a comparator 4-1-4, and the threshold value Vth
, That is, a comparison result output 4B corresponding to a NULL symbol period between T1 and T2. Then, the edge detector 4-1-5 detects a rising edge of the signal from the comparison result output 4B. Then, the delay circuit 4-1
-6, the signal rising edge detection signal 4C is delayed by one symbol to generate a SWEEP start instruction pulse ST. The correct SWEEP symbol start position (T3) can be specified by the SWEEP start start instruction pulse ST. Since the SWEEP calculation unit 4-2 can capture the start position of the SWEEP symbol waveform, the phase shift in the SWEEP calculation can be accurately determined. It can be calculated, and it is possible to search for an accurate switching timing of each symbol.
That is, the speed of the receiving clock CKrc is adjusted by the correction signal VC output from the SWEEP calculator 4-2,
By performing the lock process with the transmitted synchronization symbol phase, the error of the temporal position of the FFT gate disappears. If the time position of the SWEEP start instruction pulse which determines the detection edge of the synchronization symbol corresponding to the coarse adjustment is accurate, the amount of time position correction of the FFT gate performed by adjusting the speed of the clock CKrc, which corresponds to the fine adjustment, is reduced. And the time required to do so. That is, the gate position can be set to an error 0 (no deviation) in a shorter time,
The best decoding situation can be achieved.

[0010]

Here, in the case where transmission is performed using the transmission apparatus according to the prior art, transmission under poor transmission path conditions such as mobile transmission will be considered. In such a transmission path, the main wave directly propagated from the transmitting side to the receiving side and various reflected waves reflected on buildings, mountains, and the like are propagated with a predetermined delay time. Then
These combined waves will be received. When a reflected wave exists in addition to the main wave in this way, as shown in FIG. 10, NUL in the absolute value addition output 4A is caused by the influence of the reflected wave.
The levels of the start point portion Td1 of the L symbol and the start point portion Td2 of the CW symbol fluctuate. In the comparison between the absolute value addition output 4A of the comparator 4-1-4 and the threshold value Vth, the start point portion Td2 of the CW symbol is obtained. Becomes a level that does not exceed the threshold value Vth. Therefore, the threshold value Vth in this case
The following comparison result output 4B indicates a true NULL period (T1
... T2), but the starting portion Td1 of the NULL symbol.
The output is equivalent to the period of the start point portion Td2 of the CW symbol. As a result, since the edge detector 4-1-5 generates the signal rising edge detection signal 4C at the start point portion Td2 of the CW symbol, a large detection deviation occurs from the true NULL symbol end point. Then, since the delay circuit 4-1-6 operates from the time when the signal rising edge detection signal 4C is generated, the SWEEP start instruction signal ST is generated one symbol after the time Td2. Therefore, SWE
Since the EP start instruction signal ST is generated at a time when the actual SWEEP start position is significantly shifted (after about one symbol),
As a result, the waveform of the start point of the SWEEP symbol is not taken into the SWEEP calculation unit 4-2, so that the accuracy of the coarse adjustment is reduced, the correction amount performed in the fine adjustment is increased, and the time required for the fine adjustment is increased. Reaching the best decoding situation is delayed.

Therefore, if the threshold value Vth is set to a low value (for example, α = 0.3) in order to reduce the influence of the reflected wave, it becomes easier to detect the null end point of the main wave.
The shift amount at the time of the coarse adjustment is reduced, and the extension of the time required for the fine adjustment described above can be prevented. However, the above description is based on the premise that transmission is performed at a high CN with a small amount of noise components mixed therein. Under use conditions where the input electric field is low, the noise components increase.
A false signal generated by a noise component is mixed during the NULL period, which is essentially a no signal. Therefore, the detection accuracy of the end point of the NULL period in the comparison result output 4B may be significantly reduced. When the electric field further weakens, the noise component further increases, and as shown in FIG.
As a result, the absolute value addition output 4A during the LL period always exceeds the threshold value Vth.
In some cases, the end of the UL period cannot be detected at all.
To ensure the operation of detecting the end point of the NULL period under such a low CN condition, the threshold value Vth must be set to a high value (for example, α = 0.8). As described above, in the conventional configuration, if the target of the coarse adjustment is set to the main wave and the threshold value Vth is set low, it becomes difficult to detect the synchronization at the time of low CN as shown in FIG. On the other hand, the threshold V
When th is set high to facilitate synchronization detection at low CN, when a reflected wave is present as shown in FIG. 10, the coarse adjustment target becomes a reflected wave, and the time required for synchronization with the main wave by fine adjustment is increased. The disadvantage is that the time is lengthened. The present invention eliminates these drawbacks, and is not affected by the presence or absence of reflected waves and noise components, and can be used under any transmission conditions.
An object of the present invention is to realize an OFDM transmission system capable of accurately estimating a symbol start position and constantly detecting synchronization.

[0012]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a digital transmission apparatus using an orthogonal frequency division multiplex modulation system for transmitting several types of synchronization symbols and a plurality of data symbols as a frame-structured signal. A means for changing a threshold value as a reference for detecting an end portion of a no-signal period for detecting frame synchronization in the synchronization symbol group according to a transmission situation. Further, there is provided means for changing a threshold value, which is a reference for detecting an end portion of a no-signal period for detecting frame synchronization in the synchronization symbol group, every predetermined period. Further, a threshold value which is a reference for detecting an end portion of a no-signal period for detecting frame synchronization in the synchronization symbol group is set to an appropriate value at the beginning of the synchronization detection operation in a situation where a reflected wave exists. If the synchronization is not detected within a predetermined period, there is no reflected wave, but it is set to a high-level predetermined value that is an appropriate value in a low CN situation. There is provided means for switching control so as to return to the low level predetermined value. That is, when the CN is equal to or more than the predetermined value, coarse tuning to the main wave is performed to shorten the time required for complete synchronization. On the other hand, in the state of low CN, synchronization is first secured to achieve a wider range. Realization of normal synchronization with the main wave in a short time under various conditions.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an overall block configuration of a transmission apparatus using the OFDM modulation system of the present invention, which will be described below. This is equivalent to the transmission-side processing unit 101 having the same configuration as that shown in FIG.
3. Synchronization detector 4 and changer 7 The receiving clock CKr from the receiving processing unit 203 is connected to the clock terminal CK of the changer 7 and the synchronization detector 4. The data R'sg and I'sg from the receiving side processing unit 203 are connected to the I and Q terminals of the synchronization detector 4, respectively. The pulse FSTr and the correction signal VC from the synchronization detector 4 are connected to the terminal FSTr and the terminal VC of the reception-side processing unit 203, respectively. The output of the threshold value Vth of the changer 7 is connected to the terminal Vth of the synchronization detector 4. Next, an example of a specific configuration of the changer 7 is shown in FIG. 2 and will be described below. This is because the N frame counter 7-1, the decoder 7-2, the selector (S
EL) 7-3. Receiving side processing unit 20
3 is connected to the terminal CK of the N frame counter 7-1. An output Cout of the N frame counter 7-1 is connected to an input of the decoder 7-2.
The output P1 of the decoder 7-2 is connected to the control terminal S of the selector 7-3. The input A of the selector 7-3 has a value (for example, α = 0.3) for setting the output threshold Vth lower, and the input B has the output threshold Vth raised higher. (For example, α = 0.8) is connected. Here, the N frame counter 7-1 has a counter output C whose output changes by one every frame period.
Output out. Here, 0 to 5 are repeatedly output. The decoder 7-2 sets the counter output Cout to 0.
To 3 for level L and 4 to 5 for level H
A pulse P1 is output. The selector 7-3 selects the input A when the control terminal S is at the level L, and selects the input B when the control terminal S is at the level H, and outputs the corresponding threshold value Vth. That is, the changer 7 switches the output threshold value Vth to 0.3 or 0.8 at a predetermined cycle.

The operation of the changer 7 will be specifically described with reference to FIG. First, assuming that the time for each frame period is F1, F2, F3,..., The counter output Cout of the N frame counter 7-1 is 0 to 3 during the four frame periods from time F1 to F5, Becomes the L level, the selector 7-3 outputs α =
A threshold value Vth corresponding to 0.3 is selected and output. Then, during the next two frame periods (time F5 to F7),
The counter output Cout of the N frame counter 7-1 is 4 to
5, since the pulse P1 from the decoder 7-2 goes high, the selector 7-3 selects and outputs the threshold value Vth corresponding to α = 0.8. That is, the value of the output threshold value Vth becomes 0.3 in the four-frame period, switches to 0.8 in the next two-frame period, and thereafter, the same operation is repeated. As a result, even in a situation where a reflected wave exists, in the four frame period in which the value of the threshold value Vth is 0.3, as shown in FIG.
As a result of obtaining the comparison result output 4B in which the detection deviation of the end point is small, the time required for the fine adjustment is reduced. Further, even in a low CN state where there is no reflected wave but a lot of noise components are mixed, during the two frame periods when the threshold value Vth is 0.8, as shown in FIG. As a result of the detection, the phase shift in the SWEEP calculation can be accurately calculated, and the accurate switching timing of each symbol can be searched. As described above, in the present embodiment, the threshold value Vth for detecting the NULL period is used.
Is an appropriate value in the presence of reflected waves (e.g.,
0.3) and there is no reflected wave, but it is periodically switched to an appropriate value (for example, 0.8) in a low CN situation, so any transmission is not affected by the presence or absence of reflected waves and noise components. Even in such a situation, it is possible to accurately estimate the start position of the SWEEP symbol in a short time, and to realize an OFDM transmission system that can always detect synchronization. Here, the periodic switching of the threshold value Vth is set to a lower value (for example, 0.3) which is an appropriate value in the presence of a reflected wave at the beginning of the synchronization detection operation, and is set for a predetermined period.
If synchronization cannot be detected (e.g., three frame periods), it is possible to set a higher value (e.g., 0.8) which is an appropriate value in a low CN situation without a reflected wave and detect synchronization. Then, the value may be returned to the original lower value (for example, 0.3).

[0015]

As described above, according to the present invention, synchronization detection and FFT gate phase can be normalized in a short time even in the case of a high CN to a predetermined CN and a reflected wave is present. Even if the CN is less than a predetermined value, the time required for synchronization detection and FFT gate phase normalization is slightly longer depending on the presence or absence of a reflected wave.
A transmission system can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the overall configuration of the present invention.

FIG. 2 is a block diagram showing an example of a changer 7 of the present invention.

FIG. 3 is a time chart for explaining switching of a threshold value Vth according to the present invention;

FIG. 4 is a waveform diagram showing a general OFDM signal waveform.

FIG. 5 is a block diagram illustrating an example of a transmission device having a conventional configuration.

FIG. 6 is a block diagram showing an example of a conventional synchronization symbol insertion unit 5;

FIG. 7 is a block diagram showing an example of a conventional synchronization detector 4;

FIG. 8 is a block diagram showing an example of a conventional NULL end detector 4-1.

FIG. 9 is a time chart for explaining a conventional SWEEP symbol start timing estimation process.

FIG. 10 is a time chart for explaining a conventional SWEEP symbol start timing estimation process.

FIG. 11 is a time chart for explaining a conventional SWEEP symbol start timing estimation process.

FIG. 12 is a time chart for explaining a SWEEP symbol start timing estimation process of the present invention.

FIG. 13 is a time chart for explaining a SWEEP symbol start timing estimation process of the present invention.

[Explanation of symbols]

101: transmitting side processing unit, 1T: transmission line coding unit, 1R:
Transmission line decoding unit, 2T: switchable coding unit, 2R: decoding unit, 3A: IFFT unit, 3B: guard addition unit, 3C: F
FT section, 5: synchronization symbol insertion section, 8: orthogonal modulation processing section, 9: orthogonal demodulation processing section, 4: synchronization detector, 4-1: N
UL end detector, 4-2: SWEEP operation unit, 4-
3: SWEEP pattern memory, 4-4: frame counter, 4-1-1, 4-1-1: absolute value circuit, 4-1-1: adder,
4-1-1: Comparator, 4-1-1: Edge detector, 4-1-1: Delay circuit, 7: Modifier, 7-1: N frame counter, 7-
2: decoder, 7-3: selector.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor: Norihiro Nakata 32, Miyukicho, Kodaira-shi, Tokyo Inside Hitachi Electronics Co., Ltd. (72) Inventor Yoshikatsu Agatsuma 32, Miyukicho, Kodaira-shi, Tokyo Hitachi Electronics Co., Ltd. F term in Koganei factory (reference) 5K022 DD01 DD13 DD17 DD19 DD32 DD42 5K047 AA02 AA03 AA11 BB01 CC01 EE00 HH01 HH12 HH21 HH55 HH59 MM62

Claims (3)

[Claims] 1. A digital transmission apparatus using an orthogonal frequency division multiplexing modulation method for transmitting several types of synchronization symbol groups and a plurality of data symbols as a frame-structured signal, wherein a frame synchronization among the synchronization symbol groups is not detected. A digital transmission device, comprising: means for changing a threshold used as a reference for detecting an end portion of a signal period according to a transmission situation. 2. A digital transmission apparatus using an orthogonal frequency division multiplexing modulation system for transmitting several kinds of synchronization symbol groups and a plurality of data symbols as a signal having a frame structure, wherein a frame synchronization among the synchronization symbol groups is not detected. A digital transmission device comprising means for changing a threshold value as a reference for detecting an end portion of a signal period every predetermined period. 3. A digital transmission apparatus using an orthogonal frequency division multiplexing modulation method for transmitting several types of synchronization symbol groups and a plurality of data symbols as a signal having a frame configuration, wherein a frame synchronization among the synchronization symbol groups is not detected. At the beginning of the synchronization detection operation, a threshold value serving as a reference for detecting the end portion of the signal period is set to a low-level predetermined value that is an appropriate value in the presence of a reflected wave, and within a predetermined period. If synchronization detection is not possible, there is no reflected wave but a high level predetermined value which is an appropriate value in a low CN situation, and after the synchronization detection, means for switching control to return to the low level predetermined value. A digital transmission device characterized by being provided.