JP2000339063A - Communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication equipment capable of reducing the number of terminals by reducing terminals to be used only for resetting registers in an integrated circuit of a communication device and having an inexpensive reset function. SOLUTION: The communication device is constituted of a microprocessor(MC) 1, an IC 2 and registers, the MC 1 has a reset terminal 10 to which a reset signal is inputted, a read terminal 11, a write terminal 12, and a data terminal 13, the IC 2 has a read terminal 21, a write terminal 22 and a data terminal 23, and these read terminals, write terminals and data terminals are connected by communication lines. Resistors 26, 27 are respectively connected to the read terminal 21 and the write terminal 22, their nodes are connected to the input terminals of an OR circuit 25 and the output terminal of the OR circuit 25 is connected to registers. When a reset signal is inputted to the reset terminal 10, the read terminal 21 and the write terminal 22 are turned to high impedance and a reset signal is outputted from the OR circuit 25 to the registers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a communication device having a reset function, and more particularly to a communication device for resetting a microcomputer (microcomputer) and an integrated circuit (IC).

[0002]

2. Description of the Related Art Conventionally, a microcomputer and an integrated circuit for communication (I
In the communication device having C), the contents stored in the register are initialized (reset) when the power is turned on. In this reset, dedicated terminals (ports) are provided for the microcomputer and the IC in order to input a reset signal generated from the outside, and an initialization signal generated upon power-on is directly input to each of the reset terminals. Had to be reset.

[0003]

However, in the conventional communication apparatus as described above, a communication terminal dedicated to resetting is provided in the terminal of the IC.
The number of terminals of C has increased, which has caused a cost increase. In view of the above problems of the present invention,
It is an object of the present invention to provide a communication device having a low-cost reset function by reducing the number of terminals dedicated to reset in an integrated circuit of a communication device.

[0004]

In order to solve the above-mentioned object, according to the first aspect of the present invention, the microcomputer comprises one microcomputer, at least one integrated circuit, and at least one register. The integrated circuit has a reset terminal to which a reset signal is input, and a microcomputer side input / output terminal having at least two microcomputer side data input / output terminals, and the integrated circuit has at least two or more integrated circuit side data input / output terminals. An integrated circuit-side input / output terminal connected to the microcomputer-side data input / output terminal by a communication line, a first resistor having one end connected to one of the integrated circuit-side input / output terminals, A second resistor having one end connected to the other one of the input / output terminals, and a connection point between the integrated circuit-side input / output terminal and the first resistor serving as one input terminal;
A connection point between the integrated circuit side input / output terminal and the second resistor is the other input terminal, and an output terminal has a logic circuit connected to the register. A reset signal is input to a reset terminal. In such a case, the microcomputer side input / output terminal is brought into a predetermined state, and a register reset signal is output from the logic circuit to the register.

[0005] With the above configuration, when a reset signal is input to the microcomputer side reset terminal,
The microcomputer side input / output terminals are in the same state. Since the microcomputer side input / output terminal is connected to the integrated circuit side input / output terminal by a communication line, a signal in the same state is input from the integrated circuit side input / output terminal to the input terminal of the logic circuit. In the logic circuit, the signal in the same state is input, and a register reset signal is output to the register. The register is reset by the register reset signal.

According to a second aspect of the present invention, in the communication device of the first aspect, the microcomputer-side input / output terminal has a microcomputer-side read terminal, a microcomputer-side write terminal, and a microcomputer-side data input / output terminal, The integrated circuit side input / output terminal has an integrated circuit side lead terminal, an integrated circuit side write terminal, and an integrated circuit side data input / output terminal, the first resistor is connected to the integrated circuit side lead terminal at one end, and the second resistor is One end is connected to the integrated circuit side write terminal, and the microcomputer side read terminal and the microcomputer side write terminal are configured to have high impedance when a reset signal is input to the reset terminal.

With the above configuration, when a reset signal is input to the reset terminal on the microcomputer side,
The integrated circuit side read terminal and the integrated circuit side write terminal become high impedance. Since the integrated circuit side read terminal and the integrated circuit side write terminal are input terminals of the logic circuit, a register reset signal is output from the output terminal of the logic circuit to the register, and the register is reset.

[0008]

According to the present invention, a dedicated terminal for resetting the register is not required in the integrated circuit, so that the number of terminals of the integrated circuit can be reduced, and the cost can be reduced while maintaining the register reset function. There is an effect that a communication device can be provided.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing the overall configuration, which will be described below. Reference numeral 1 denotes a microcomputer having a CPU (Central Processing Unit), and the microcomputer 1 controls the apparatus. The microcomputer 1 includes an integrated circuit (I
C) A plurality of (three in this embodiment) 2 to 4 are connected. These ICs 2 to 4 have registers 21, 2
2, the registers 31 and 32 and the registers 41 and 42 are respectively connected.
And the program executed by the CPU of the microcomputer 1 are stored and read and written at a predetermined timing.

Reference numeral 5 denotes a switch, which is an input device. The microcomputer 1 performs a predetermined operation by inputting information of the switch 5 to the microcomputer 1. The calculated information is stored in a register and read at a predetermined timing to drive the load 6 as an output device.

Next, the relationship between the microcomputer and the IC will be described with reference to FIG. Here, the description will be made using the microcomputer 1 and one IC 2, but the other ICs have the same configuration.

The microcomputer 1 is provided with a reset terminal 10, a read terminal 11, a write terminal 12, and a plurality of data terminals 13 for inputting a reset signal from the outside as so-called I / O ports. The IC 2 has a read terminal 21, a write terminal 22, and a plurality of data terminals 23, which are I / O.
It is provided as a port. One end of a resistor 26 is connected to a lead terminal of the IC 2, and the other end of the resistor 26 is grounded. A resistor 2 is connected to the write terminal 22 of IC2.
7 is connected, and the other end of the resistor 27 is grounded. The outputs of the read terminal 21 and the write terminal 22 are connected to the input side of an OR circuit 25. The OR circuit 25 outputs a reset signal, which will be described later, to the registers 21 and 22.
Is output to.

The microcomputer 1 transmits a read signal from the lead terminal 11 of the microcomputer 1 to the lead terminal 21 of the IC 2 by a predetermined program, and reads the data stored in the registers 21 and 22 to the data terminals 13 and 23.
Similarly, a write signal is transmitted from the write terminal 12 of the microcomputer 1 to the write terminal 22 of the IC 2 and the data calculated by the microcomputer 1 is transmitted through the communication line between the data terminals 13 and 23. Register 2
1 and 22 are written. The data terminal 13 and the data terminal 23 are terminals that can perform both input / output functions, and determine whether each terminal is an input terminal or an output terminal when the power is turned on, that is, a so-called DD terminal.
This is an R (Data Direction Register) method.

As described above, in the present embodiment, the microcomputer 1 executes a predetermined program using the data of the switch 5 as an input device and the data stored in the registers 21 and 22. , 22, a read signal is transmitted from the lead terminal 11 of the microcomputer 1 to the lead terminal 21 of the IC 2, and the registers 21, 2 are read based on this signal.
2 is transmitted to the microcomputer 1 through a data communication line between the data terminals 13 and 23. The data calculated by the microcomputer 1 is stored in the register 2.
1 and 22, a write signal is transmitted from the write terminal 12 of the microcomputer 1 to the write terminal 22 of the IC 2, and based on this signal, the IC 2 is connected by a data communication line between the data terminals 13 and 23. Through the register 21,
22 is transmitted.

Next, the operation of the present embodiment will be described with reference to a timing chart shown in FIG. FIG. 3A shows the waveform of a reset signal 30 generated by the outside and input to the reset terminal 10 of the microcomputer 1, and FIG. 3B shows the reset signal 30 input to the microcomputer 1. 3C shows a read signal transmitted from the read terminal 11 to the read terminal 21, FIG. 3D shows a write signal transmitted from the write terminal 12 to the write terminal 22, and FIG. 3E shows an OR circuit. 3 (f) shows a reset signal output from the OR circuit, and FIG. 3 (g) shows data transmitted and received on a communication line between the data terminals 13 and 23.

As shown in FIG. 3, when a power supply (not shown) connected to the communication apparatus is turned on, an externally generated L-level reset signal is output to a reset terminal 10 of the microcomputer 1 at time t. Entered with ₁ . When an L-level reset signal is input to the microcomputer 1, the read terminal 11 and the write terminal 12 of the microcomputer 1 enter an input state, and the read terminal 11 and the write terminal 12 of the microcomputer 1 become high impedance. Therefore, at this time, the IC connected to the read terminal 11 and the write terminal 12 of the microcomputer 1
2 lead terminal 21 and write terminal 22
27, the output of the OR circuit 25 becomes H level, and this output (reset signal) is transmitted to the registers 21 and 22 connected to the IC 2 and stored in the registers 21 and 22. Erase contents (reset)
Is done.

[0017] Next, at time _{t 2} after the reset of the register 21, 22 is completed, a reset signal 30 from the outside
Becomes H level, and the reset terminal 1 of the microcomputer 1
The input to 0 also goes high. As a result, a predetermined program is executed, and the above-described DDR control is performed. That is, the lead terminal 11 to a time _t 2 ~t _3, together with the write terminal 12 is set to H-level signal is output sets each data terminal 13. As a result, the read terminal 21 and the write terminal 22 of the IC 2 become H level signals, the output of the OR circuit 25 receiving these signals also becomes L level, and the transmission of the reset signal to the register is stopped.

By [0018] Then the microcomputer 1 program, at time _{t 4,} and the lead terminal 11 and the L level, read into the microcomputer 1 at time _t 4 ~t ₅ the data in the register 21 by a data communication line.

[0019] By following the program of the microcomputer, at time _{t 6,} the write terminal 12 to the L level, writing from the calculation results IC2 of the microcomputer 1, to the time _t 6 ~ t ₇ to register 21. By repeating the calculation in this manner, the load is driven based on the switch 5.

In the present embodiment, a resistor is connected to the read terminal 21 and the write terminal 22 provided on the IC 2 and its output is input to the OR circuit 25, and the register 21 connected to K2 by this output. Since the resetting of 22 is performed, the dedicated reset terminal conventionally provided becomes unnecessary for the IC 2, so that the number of terminals can be reduced and a communication device having a low-cost reset function can be provided.

In this embodiment, the resistance 26,
Although the other end of the pull-down resistor 27 is a grounded pull-down resistor, the same effect can be obtained by using a pull-up resistor whose other end is connected to a power supply.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. Even if present, it is included in the present invention.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main part of an embodiment of the present invention.

FIG. 2 is an overall configuration diagram of an embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation of the exemplary embodiment of the present invention.

[Explanation of symbols]

 1 microcomputer 2 IC 3 IC 4 IC 5 switch 6 load 10 reset terminal 11 read terminal 12 write terminal 13 data terminal 21 read terminal 22 write terminal 23 data terminal 25 OR circuit 26 resistance 27 resistance 30 reset signal 31 register 32 register 41 register 42 register

Claims (2)

[Claims] 1. A microcomputer comprising at least one microcomputer, at least one integrated circuit, and at least one register, wherein the microcomputer has a reset terminal for receiving a reset signal, and at least two or more microcomputer-side data input / output terminals. And an integrated circuit having at least two or more integrated circuit-side data input / output terminals and connected to the microcomputer-side data input / output terminals via communication lines, respectively. A first resistor having one end connected to one of the integrated circuit side input / output terminals, a second resistor having one end connected to the other one of the integrated circuit side input / output terminals, A connection point between the integrated circuit side input / output terminal and the first resistor is one input terminal, and a connection point between the integrated circuit side input / output terminal and the second resistor is the other input terminal. And a logic circuit having an output terminal connected to the register, and when a reset signal is input to the reset terminal, the microcomputer-side input / output terminal enters the same predetermined state, and the logic circuit And a register reset signal is outputted from the communication device to the register. 2. The communication device according to claim 1, wherein the microcomputer side input / output terminal has a microcomputer side read terminal, a microcomputer side write terminal, and a microcomputer side data input / output terminal, and the integrated circuit side input / output terminal is An integrated circuit side read terminal, an integrated circuit side write terminal, and an integrated circuit side data input / output terminal, the first resistor is connected at one end to the integrated circuit side lead terminal, and the second resistor is connected to the integrated circuit side. The communication is characterized in that one end is connected to a circuit-side write terminal, and the microcomputer-side read terminal and the microcomputer-side write terminal are configured to have high impedance when a reset signal is input to the reset terminal. apparatus.