JP2000324092A - Clock supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand a frequency acquisition range while reducing jitters by outputting a transmission signal according to a given timing signal and a control signal of specific bits and generating a control signal according to the error between an externally supplied clock signal and the transmission signal. SOLUTION: The clock supply device leads a clock error signal given in the form of a digital signal to a DSP(digital signal processor) 4 and generates a control signal to be supplied to a DDS(direct digital synthesizer) 3 through digital arithmetic processing. A reference signal of 5 MHz is multiplied by a multiplier 2 to 20 MHz and then supplied to the DDS 3. A DSP 4 is a general processor having a program memory inside and its control contents can easily be modified by rewriting a program. The processing is confined to the digital signal processing, so the operation is very fast.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to, for example, SS (Spre
The present invention relates to a clock supply device used in a transmitter or a receiver using a modulation method.

[0002]

2. Description of the Related Art In the field of information communication, a clock supply device is used to synchronize a transmitting side and a receiving side. As shown in FIG. 3, the conventional clock supply device has a difference (clock error) between a reference signal from a high-precision clock supply source (not shown) and an output clock of the VCO 6.
Is smoothed by the loop filter 5 to be a control signal of the VCO 6.

[0003]

However, with the development of communication systems in recent years, the precision required for clock supply devices has become increasingly severe. In particular, GPS
In a field called (Global Positioning System), strict accuracy is required more than ever in order to perform high-precision positioning on the order of several tens of cm from the transmission time and propagation time of radio waves.

[0004] However, the conventional clock supply device largely depends on the characteristics (time constant and the like) of the loop filter 5 as an analog device, and it is difficult to obtain sufficient accuracy in terms of response speed and stability. Further, as is well known, it is difficult to achieve both a reduction in jitter at the time of clock reproduction and an expansion of a frequency pull-in range, and thus the strict specifications required for GPS have not been satisfied.

Further, once the conventional clock supply device is assembled, its characteristics are fixed. That is, it is difficult to freely change the tracking characteristic and the frequency pull-in range for the reference signal.

[0006] In the development stage of the communication system, it is indispensable to perform a test by changing the characteristics of each device in various ways, but due to the above circumstances, a sufficient test could not be performed in the clock supply device.

[0007] The present invention has been made in view of the above circumstances,
An object of the present invention is to provide a clock supply device capable of expanding the frequency pull-in range while reducing jitter and easily changing characteristics.

[0008]

To achieve the above object, the present invention provides an oscillation signal generating means for outputting an oscillation signal based on a given timing signal and a control signal of a predetermined bit, and a clock signal supplied from the outside. Control signal generating means for generating the control signal based on an error between the control signal and the oscillation signal.

More specifically, the oscillation signal generating means includes a memory for sequentially storing amplitude data of a sinusoidal waveform divided at a predetermined phase interval at an address corresponding to each phase; Reading means for discontinuously designating the address in a step based on a control signal and reading the amplitude data stored at the address; and a step-like voltage signal which converts the amplitude data read by the reading means into an analog signal. And a low-pass filter for removing high-frequency components from the step-like voltage signal. For example, at least the memory, the reading means, the digital / analog converting means, DDS (Direct Digital Synthes) with low-pass filter formed on the same substrate
izer).

Further, according to the present invention, the control signal generating means includes a D signal for generating the control signal by software processing.
It is characterized by being an SP (Digital Signal Processor).

In this case, the reproduced clock is obtained as an output of the oscillation signal generating means. Since the DDS is used as the oscillation signal generation means, a sine wave signal is generated by digital processing, and the time required for signal generation is extremely short. In order to generate a control signal to be given to the DDS, software processing by a DSP is performed. Therefore, by rewriting the software, the reproduction frequency and the clock pull-in range can be easily changed, and the flexibility is increased.

Further, in the present invention, a multiplier is provided to multiply the reference signal and to provide the multiplied reference signal to the oscillation signal generating means as a timing signal. In order to specify the step of reading waveform data in the DSP, two signals, a timing signal and a control signal, are required. However, as the frequency of the timing signal increases, the reading step becomes smaller. Thus, the accuracy of the oscillation signal can be improved.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a configuration of a clock supply device according to the present embodiment. This clock supply device guides a clock error signal given in the form of a digital signal to a DSP (Digital Signal Processor) 4, and generates a control signal to be given to the DDS 3 by digital arithmetic processing. In addition, a 5 MHz reference signal is multiplied to 20 MHz by the multiplier 4 and then DDS3.
To give to.

Here, DDS (Direct Digital Synthes)
izer) will be briefly described with reference to FIG. As shown in FIG. 2, the DDS 3 (general DDS) adds a control signal provided in the form of digital data by an accumulator 31 based on the frequency of a reference signal, and latches the addition result.
2 to the address of the ROM 33. This ROM
33 stores waveform data obtained by sampling a sine wave waveform in fine steps, and discrete data is supplied to the D / A converter 34 by the output of the latch 32. A step-like voltage waveform is output from the D / A converter 34, and a desired oscillation output (reproduced clock) can be obtained by removing a spurious component by a low-pass filter (LPF). I have.

The step of reading from the ROM 33 can be freely varied by a control signal and a reference signal supplied to the accumulator 31. That is, as the number of bits of the control signal given as digital data is increased and the frequency of the reference signal is increased, the output frequency (reproduced clock frequency) can be varied in finer steps.

In addition, the DDS has the following features. -Very little spurious is included in the output signal.・ High purity of output signal.・ Response speed to frequency change is very fast.

The DSP 4 (general DSP) is a general-purpose processor having a built-in program memory, as is well known, and can easily change the control contents by rewriting the program. Since the processor is specialized for digital signal processing, its operation is very fast. For this reason, in combination with the high-speed reaction time of the DDS3, the following speed related to the clock reproduction becomes extremely high, and an effect that jitter can be reduced can be obtained.

In this embodiment, the DSP 4 uses 32
A bit control signal is provided to DDS3.
In general, as the number of bits of the control signal increases, the variable step of the reproduced clock signal can be made finer, so that the precision related to clock reproduction can be increased, which also has the effect of reducing jitter. By the way, the output accuracy of the conventional clock supply device is at most 8
This corresponds to the case where a bit control signal is given.

Further, in the above configuration, since the reference signal is multiplied by 4 by the multiplier and then applied to the DDS 4, the effect of improving the accuracy related to clock reproduction can be obtained.

Further, since the software control is performed by the DSP 4, the reproduction clock frequency and the variable step can be easily changed. Also, due to the inherent properties of DDS, the reproduction clock frequency can be varied over a very wide range.

Thus, in the present embodiment, the DDS3 is used as the clock reproduction source, and the clock is reproduced by software control by the DSP4. A variable range (reduction in jitter) can be achieved. In addition, since software control is performed, the system is highly flexible, can immediately respond to operations under various conditions, and is convenient for testing during system design.

In the embodiment of the present invention, D
The number of bits of the control signal from SP4 is not limited to 32,
The number of bits can be arbitrarily changed according to the processing capability of the DSP 4. Further, the configuration of the DDS3 is not limited to the above configuration, and a configuration in which waveform data is directly read from the ROM may be used.

[0023]

As described in detail above, in the present invention, the clock reproduction is performed by software control by the DSP using the DDS, so that the frequency pull-in range can be expanded while reducing the jitter, and the characteristics can be easily improved. It is possible to provide a clock supply device that can be changed to the following.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock supply device according to an embodiment of the present invention.

FIG. 2 is a diagram used to explain the principle of DDS.

FIG. 3 is a block diagram showing a configuration of a conventional clock supply device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Amplifier 2 ... Multiplier 3 ... DDS (Direct Digital Synthesizer) 31 ... Accumulator 32 ... Latch circuit 33 ... ROM 34 ... Digital / analog converter (D / A converter) 35 ... Low-pass filter (LPF) 4 ... DSP (Digital Signal Processor) 5 ... Loop filter 6 ... Voltage controlled oscillator (VCO)

Claims (4)

[Claims] An oscillation signal generating means for outputting an oscillation signal based on a given timing signal and a control signal of a predetermined bit; and an oscillation signal generating means for outputting the control signal based on an error between a clock signal supplied from outside and the oscillation signal. A clock supply device comprising: a control signal generation unit that generates the control signal. 2. The oscillation signal generation means includes: a memory that sequentially stores amplitude data of a sine wave waveform divided at a predetermined phase interval at an address corresponding to each phase; Reading means for discontinuously designating the address in the step based on the amplitude data stored at the address, and converting the amplitude data read by the reading means into an analog signal to generate a step-like voltage signal. 2. The clock supply device according to claim 1, further comprising: digital / analog conversion means for outputting; and a low-pass filter for removing a high-frequency component from the stepped voltage signal. 3. The DDS (Direct Digital Synthesizer) in which at least the memory, the readout unit, the digital / analog conversion unit, and the low-pass filter are formed on the same substrate.
The control signal generating means is a DSP (Digital Signal Processor) that generates the control signal by software processing.
3. The clock supply device according to claim 2, wherein the clock supply device is configured as r). 4. The clock supply device according to claim 1, further comprising a multiplier that multiplies an externally supplied reference signal to generate the timing signal.