JP2000340953A - Manufacture of multilayered printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method of manufacturing a printed wiring board, wherein a high density wiring pattern can be formed and a high connection reliability can be obtained. SOLUTION: In a multilayered wiring board 1, wherein a wiring layer 6 is connected to a wiring layer 2 through a bump 7, the layer 6 is a stripped to expose part of a base 7a of the bump 7. An insulator layer 9a is formed on the layer 6. A hole 11 for exposing the base 7a of the bump 7 is formed in the layer 9a. By plating the upper part of the layer 9a and the hole 11, a conductor layer 13 and a via hole 11a are formed. The layer 13 is etched to form a prescribed wiring pattern 14. The layer 9a is a photo-curing resin layer. The photo-curing resin layer is exposed and developed via a photoresist, and the unexposed part thereof is removed to form the hole 11. The hole 11 is formed in the layer 9a by having the layer 9a irradiated with a laser light.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed wiring board for connecting between wiring layers by a through-type conductive wiring portion.

[0002]

2. Description of the Related Art In recent years, with the development of technology for miniaturizing electronic components and mounting technology for wiring boards, it has become necessary to increase the density of printed wiring boards and reduce costs. Conventionally, a multilayer printed wiring board has been manufactured by plating a conductor such as copper in a through-hole (through hole) provided in the board and making connection between wiring layers. It is becoming difficult to cope with high density and cost reduction.

[0003] In view of the above, a technology that replaces the above-mentioned conventional manufacturing method is being studied. For example, a manufacturing method disclosed in Japanese Patent Application Laid-Open No. 6-342977 is known. The technique described in the above publication firstly forms a plurality of bumps by printing a silver paste at a predetermined position on a conductive support such as a copper foil, and laminates a synthetic resin sheet on the copper foil on which the bumps are formed. Then, the tip of the bump penetrates and is exposed to the synthetic resin sheet by applying pressure. Then, a conductor layer such as a copper foil is laminated on the synthetic resin-based sheet and pressurized, and the tip of the bump exposed from the synthetic resin-based sheet is pressure-bonded to the conductor layer. A through-type conductor wiring portion for connecting foils is formed. According to the technique described in the above publication, a copper foil for forming the conductive support and the conductive layer is then etched to form a wiring pattern, thereby obtaining a double-sided printed wiring board.

If the conductor layer is replaced with a copper foil and the double-sided printed wiring board is used, the bumps exposed from the synthetic resin-based sheet are formed on a wiring pattern formed on the surface of the double-sided printed wiring board. To form a through-type conductor wiring portion by crimping the tip of the substrate and repeating the operation of etching the copper foil forming the conductive support to form a wiring pattern, thereby manufacturing a multilayer printed wiring board. it can.

In a multilayer printed wiring board obtained by the manufacturing method described in the above-mentioned publication, a BGA (Ball Grid A) is added to a wiring pattern formed from the conductive support.
(rray) and CSP (Chip Size / Scale)
A high-density wiring pattern capable of sufficiently mounting electronic components such as a semiconductor package called “Package” can be obtained.

However, the bumps need to have a diameter enough to penetrate the synthetic resin sheet. Therefore, when forming a wiring pattern by etching on a copper foil or the like on which the bumps are formed, the bumps are required. The pitch of the wiring pattern is restricted by the bump diameter, and it is difficult to form a wiring pattern with higher density.

Further, there is a need for a multilayer printed wiring board having higher connection reliability when mounting the electronic components such as the BGA and the CSP on a wiring pattern having a higher density.

[0008]

SUMMARY OF THE INVENTION In view of the foregoing, the present invention can further increase the density of a wiring pattern, and can achieve higher wiring patterns when an electronic component such as a semiconductor package called BGA or CSP is mounted. An object of the present invention is to provide a method for manufacturing a printed wiring board that can obtain connection reliability.

[0009]

In order to achieve the above object, a method of manufacturing a multilayer printed wiring board according to the present invention is characterized in that an outermost wiring layer is formed with an adjacent wiring layer via a first insulator layer. A step of exfoliating at least a part of the wiring layer to expose a part of a base of the bump on a surface of the multilayer wiring board connected by the bump penetrating the first insulator layer; Forming a second insulator layer made of a synthetic resin on the wiring layer whose base is exposed;
Forming a hole in the second insulator layer to expose the base of the bump; plating the second insulator layer and the hole to form a hole on the second insulator layer; Forming a first conductor layer by the applied plating, and forming a via connecting the first conductor layer and the base of the bump by the plating applied to the hole; Forming a predetermined wiring pattern by etching the conductor layer.

According to the manufacturing method of the present invention, first, a part of the outermost wiring layer of the multilayer wiring board is peeled off to expose the base of the bump. Therefore, by forming a hole exposing the base of the bump in the second insulator layer laminated on the multilayer wiring board, and plating the hole on the second insulator layer, A first conductor layer formed on a second insulator layer is connected to the bump via a via formed in the hole by plating.

Therefore, when the first conductor layer is etched to form a wiring pattern, a wiring pattern having a high density can be formed without being restricted by the bump diameter. In addition, since a large adhesive strength is obtained between the plating applied to the hole and the bump, a wiring pattern formed by etching the first conductive layer is connected through the via. Thereby, excellent connection reliability with the bump can be obtained.

In the manufacturing method of the present invention, the second insulator layer laminated on the multilayer wiring board may be a photo-curable resin layer or a non-photo-curable resin layer. When the second insulator layer is made of a photocurable resin layer, a photoresist is formed on the surface of the photocurable resin layer so as to cover a portion where the base of the bump is exposed. Then, after exposing and curing the photocurable resin layer using the photoresist as a mask, an unexposed portion of the photocurable resin is removed to form a hole exposing a base of the bump. Further, when the insulator layer is made of a non-light-curable resin layer, the surface of the non-light-curable resin layer is irradiated with laser light to form a hole exposing a base of the bump.

The non-photocurable resin layer may include a second conductor layer on a surface opposite to a surface laminated on the multilayer wiring board. However, in this case, when the second conductive layer is irradiated with the laser beam, the laser beam is reflected.
The conductive layer is etched to remove the portion of the second conductive layer where the base of the bump is exposed,
The hole is formed by irradiating the non-light-curable resin layer at a portion where the conductive layer has been peeled off with laser light. Or the second
The conductor layer is subjected to an oxidation treatment to form a black oxide film, and a portion where the base of the bump is exposed is irradiated with laser light through the oxide film to form the hole.

When the non-photocurable resin layer includes the second conductive layer, plating is performed on the second conductive layer on the insulating layer and on the hole following the formation of the hole. To form a first conductor layer by plating on the second conductor layer, and to connect the first conductor layer and the base of the bump by plating on the hole. Form vias to be connected. Then, the first and second conductor layers are etched to form a predetermined wiring pattern.

As described above, since a large adhesive strength is obtained between the plating applied to the hole and the bump, the first conductor layer is connected via the via as described above. Thereby, excellent connection reliability with the bump can be obtained, and excellent connection reliability with the bump via the first conductor layer on which the second conductor layer is also laminated. Sex can be obtained.

[0016]

Next, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. FIG. 1 is an explanatory sectional view showing one configuration example of a multilayer wiring board used in the manufacturing method of the present invention, and FIG. 2 is an explanatory sectional view showing a manufacturing method of the multilayer wiring board shown in FIG. 3 to 7
Is an explanatory sectional view showing a step of a first aspect of the manufacturing method of the present embodiment, and FIGS. 8 to 11 are explanatory sectional views showing steps of a second aspect of the manufacturing method of the present embodiment. .

First, a multilayer wiring board 1 used in the present embodiment will be described with reference to FIG. FIG. 1 (a)
The illustrated multilayer wiring board 1 has wiring layers 2 provided on both front and back surfaces, and is configured with a base substrate 4 in which the wiring layers 2 and 2 are connected by interstitial via holes 3 as a core. In the multilayer wiring board 1, an insulating layer 5 made of a synthetic resin sheet such as a prepreg is laminated on a base substrate 4, and a wiring layer 6 formed on the surface of the insulating layer 5 is It has a four-layer configuration connected to the wiring layer 2.

The base substrate 4 is an insulating layer made of glass epoxy resin or the like having a thickness of, for example, 300 μm, and the wiring layer 2 is made of, for example, a copper foil having a thickness of 18 μm.
The interstitial via hole 3 is, for example,
It has a diameter of 0.25 mm, is filled with a conductive paste, is dried, or is plated inside.

The multilayer wiring board 1 can be manufactured as follows. First, as shown in FIG. 2A, a plurality of bumps 7 are formed at predetermined positions on a conductive support 8 such as a 18-μm-thick copper foil. The bumps 7 are formed by laminating a metal mask having a through hole at a predetermined position on the conductive support 8, screen-printing a conductive paste such as a silver paste on the metal mask, and drying the paste. Is done.

Next, as shown in FIG. 2B, the synthetic resin sheet 5 is laminated on the conductive support 8 on which the bumps 7 are formed, and the bumps 7 are pressed to form the bumps 7 on the synthetic resin sheet 5. And the tip thereof is exposed from the synthetic resin sheet 5. The synthetic resin sheet 5 has a thickness of 60 μm. In order for the bumps 7 to penetrate the synthetic resin sheet 5, for example, the diameter of a portion that comes into contact with the conductive support 8 is 0.1 μm.
It is formed so as to have a size of 2 mm and a height of 0.1 mm.

Next, as shown in FIG. 2 (c), the conductive support 8 on which the synthetic resin sheet 5 is laminated is placed on the surface where the bumps 7 are exposed from the synthetic resin sheet 5 as described above. Is pressed on both sides of the base substrate 4 having Next, the base substrate 4 on which the conductive support 8 on which the synthetic resin-based sheet 5 is laminated is pressure-bonded to both surfaces is mounted on a multilayer press, and is integrated by being heated and pressed in a vacuum.

Next, as shown in FIG. 2D, a wiring layer 6 is formed by etching a conductive support 8 integrated with the base substrate 4 via a synthetic resin sheet 5. The multilayer wiring board 1 shown in FIG. 1A is obtained. FIG. 1A is an enlarged view of a main part of the multilayer wiring board 1 of FIG. 2D.

Next, with reference to FIG. 1B and FIGS. 3 to 7, a first mode of the method for manufacturing a multilayer printed wiring board of the present embodiment using the multilayer wiring board 1 will be described.

In the first embodiment of the present embodiment, first, the outermost wiring layer 6 of the multilayer wiring board 1 is etched to remove a part of the wiring layer 6, and as shown in FIG. Then, the base 7a of the bump 7 is exposed. At this time, the wiring layer 6
The connection with the bump 7 is secured by the part which is not peeled off. The operation of peeling a part of the wiring layer 6 may be performed simultaneously with the etching for forming the wiring layer 6 from the conductive support 8 shown in FIG.

Next, as shown in FIG. 3, a photocurable resin layer 9 is formed on the wiring layer 6 where the bases 7a of the bumps 7 on both surfaces of the multilayer wiring board 1 are exposed. As the photocurable resin for forming the photocurable resin layer 9, a photosensitive epoxy resin such as a dimerization reaction resin, a cation polymerization resin, or an anion polymerization resin can be used. As such a photocurable resin, for example, a solder resist manufactured by Tamura Corporation (trade name: FINDEL DSR-2200M)
L), Provimer (trade name) manufactured by Ciba Specialty Chemicals Co., Ltd., and the like. The photocurable resin exemplified above has both thermosetting and photocurable properties. The photocurable resin is applied to the multilayer wiring board 1 by a method such as screen printing, curtain coating, spray coating, and the like, and dried to a thickness of, for example, 60 nm.
A photocurable resin layer 9 of μm can be formed.

Next, as shown in FIG. 4, a photoresist 10 is provided so as to cover a portion where the base 7a of the bump 7 of the multilayer wiring board 1 is exposed. The layer 9 is exposed to ultraviolet light to be exposed. Then, the photocurable resin leaves an unexposed photocurable resin layer 9 behind the photoresist 10, and the portion exposed to the ultraviolet rays is cured to form an insulator layer 9a.

The photoresist 10 and the unexposed photocurable resin layer 9 behind the photoresist 10 are then removed by developing with a 1% aqueous solution of sodium carbonate. As shown in FIG. 5, the base 7a of the bump 7 is removed. An exposed hole 11 is formed. The hole 11 only needs to be large enough to expose the base 7a of the bump 7, and is formed, for example, so that the diameter of the opening is 0.1 mm. At this time, if necessary, a through hole 12 for forming a through hole may be formed. The through hole 12 is formed to have a diameter of, for example, 0.3 mm by a drill, a laser, an electron beam, or the like.

Next, as shown in FIG. 6, the surface of the insulator layer 9a made of a photocurable resin is plated to form a conductor layer 13 having a thickness of, for example, 18 μm. The plating is simultaneously applied to the hole 11 and the through hole 12, and the via 11 a connects the conductor layer 13 and the bump 7 to the hole 11, and the through hole connects the conductor layers 13, 13 to the through hole 12. 1
2a is formed. FIG. 6 shows a configuration in which the via 11 a is not in contact with the wiring layer 6.
Are electrically connected to the wiring layer 6 via the bumps 7. Therefore, the via 11 a may be in direct contact with the wiring layer 6.

In the plating, the surface of the insulator layer 9a is cleaned to remove burrs when the through holes 12 are formed, and the through holes 1 are removed.
After polishing the inside of the 2 with an abrasive and washing with water, a desmear treatment, a pretreatment, an electroless plating treatment, and an electrolytic plating treatment are performed in this order.

In the desmear treatment, the resin chips melted by the cutting heat generated when the through hole 12 is formed
This is a process for removing smears formed and adhered to the inner wall of No. 2. The desmear treatment is performed by the insulating layer 9a, the hole 11
After immersing the multilayer wiring board 1 in which the through-holes 12 are formed in a swelling solution, washing with hot water and dissolving the smear in a potassium permanganate solution or a sodium permanganate solution to remove the smear. Then, after washing with water, the adhered manganese dioxide is removed.

In the pretreatment subsequent to the desmear treatment, the surfaces of the insulating layer 9a and the holes 11 and the inside of the through holes 12 are degreased and washed with a degreasing agent, washed with hot water, and then with a soft etching agent (cupric chloride). Solution) to remove the oxide film on the surfaces of the insulator layer 9a, the holes 11, and the through holes 12. Next, the residue (smut) of the etching agent is removed by pre-dip. Then, a treatment with a palladium compound solution is performed to attach a palladium compound for generating nuclei for electroless plating.

In the electroless plating subsequent to the pretreatment, the palladium compound is first reduced by a reducing agent to generate palladium which is a core of the electroless plating. Next, after the reducing agent is washed with water and removed, the insulating layer 9a and the hole 11 are removed.
Then, the multilayer wiring board 1 in which the through holes 12 are formed is immersed in an electroless plating bath. The electroless plating bath includes copper sulfate, formalin, sodium hydroxide, a chelating agent, and a surfactant, and reduces copper sulfate with formalin to precipitate copper. As a result, a copper plating layer is formed on the surfaces of the insulator layer 9a, the holes 11, and the through holes 12. The multilayer wiring board 1 on which the copper plating layer is formed is washed with water to remove the residue of the electroless plating bath.

The electrolytic plating subsequent to the electroless plating is performed for thickening the copper plating layer. The electrolytic plating is performed by immersing the multilayer wiring board 1 on which the copper plating layer is formed in an electrolytic plating bath, using the copper plating layer as a cathode, and using an electrode plate made of phosphorous copper as an anode, and applying a current between both electrodes. Do. The electrolytic plating bath includes copper sulfate, sulfuric acid,
Those containing chlorine ions and additives are used. The conductor layer 13, the via 11a, and the through hole 12a are formed by the electrolytic plating.

The multilayer wiring board 1 on which the conductor layer 13, the via 11a and the through hole 12a are formed is washed with water to remove the residue of the electrolytic plating bath.

Next, by etching the conductor layer 13, a multilayer printed wiring board 15 having a wiring pattern 14 is obtained as shown in FIG. The etching can be performed, for example, as follows.

First, a photosensitive film (dry film) serving as an etching resist film is adhered to the conductive layer 13.
And the openings of the vias 11a and the through holes 12a are closed. Next, exposure and development are performed using a manufacturing film, and an etching resist film is left only in a portion necessary for the wiring pattern 14 and an opening of the via 11a and the through hole 12a. Then, when the etchant is sprayed, the portion of the conductor layer 13 not covered with the etching resist film is dissolved and removed, and the wiring pattern 14 is formed. At this time, the via 11a and the through hole 12a
Since it is covered with the etching resist film, it can be left as it is without being dissolved and removed by the etching solution.

In the multilayer printed wiring board 15 shown in FIG.
The diameter of the land connected to the via 11a could be made smaller than the diameter of the land connected to the bump 7 in the wiring layer 6, and the density of the wiring pattern 14 could be increased. Further, since the wiring pattern 14 is connected to the bump 7 by the via 11a formed by the plating, excellent connection reliability with the wiring layer 6 can be obtained.

Next, with reference to FIG. 1B and FIGS. 8 to 11, a second embodiment of the method for manufacturing a multilayer printed wiring board of the present embodiment using the multilayer wiring board 1 will be described.

In the second mode of the present embodiment, first, a part of the outermost wiring layer 6 of the multilayer wiring board 1 is peeled off by the same operation as in the first mode, and as shown in FIG. Thus, the base 7a of the bump 7 is exposed. At this time, the connection between the wiring layer 6 and the bump 7 is ensured by the portion that has not been peeled.

Next, as shown in FIG. 8, an insulating layer 16 made of a synthetic resin is formed on the wiring layer 6 where the bases 7a of the bumps 7 on both surfaces of the multilayer wiring board 1 are exposed.
The synthetic resin forming the insulator layer 16 of the present embodiment is non-photocurable, and the insulator layer 16 has the conductor layer 17 on the surface opposite to the surface laminated on the multilayer wiring board 1. . In the present embodiment, a commercially available resin-coated copper foil is pressure-bonded to the multilayer wiring board 1 on the resin side, so that the multilayer wiring board 1 can be configured to have the insulator layer 16 and the conductor layer 17 laminated thereon. .

Next, as shown in FIG. 9, the conductive layer 17 was etched to remove the portion of the conductive layer 17 where the base 7a of the bump 7 was exposed, and the insulating layer 16 was exposed. The exposed part 16a is formed. Then, the insulator layer 16
The exposed portion 16a is irradiated with a laser beam to incinerate the insulator layer 16 below the exposed portion 16a. At this time, the conductor layer 1
If the layer 7 is not peeled off, the laser beam is reflected on the conductor layer 17 and the insulator layer 16 cannot be burned.

As a result, as shown in FIG.
A hole 11 exposing the base 7a is formed. Hole 11
May be large enough to expose the base 7a of the bump 7, and is formed, for example, so that the diameter of the opening is 0.1 mm. At this time, if necessary, a through hole 12 for forming a through hole may be formed. Through hole 12
Can be measured, for example, with a drill, laser, electron beam, or the like.
It is formed to a diameter of 3 mm.

Next, the surface of the conductor layer 17 laminated on the insulator layer 16 is plated by exactly the same method as in the first embodiment, and the conductor layer shown by the phantom line in FIG. 1
Form 3 The conductor layer 13 is formed to a thickness of, for example, 18 μm. The plating is simultaneously performed in the hole 11 and the through hole 12, and the conductor layer 13 and the bump 7 are formed in the hole 11.
11a, the conductor layer 13 in the through hole 12,
13 are formed. FIG.
1 shows a configuration in which the via 11a is not in contact with the wiring layer 6, but since the conductor layer 13 is electrically connected to the wiring layer 6 via the bump 7, the via 11a is connected to the wiring layer 6. It may be in direct contact.

Next, the conductor layer 13 and the conductor layer 17 are subjected to etching in exactly the same manner as in the first embodiment, thereby forming a multilayer printed wiring board 18 having a wiring pattern 14 as shown in FIG. Is obtained.

In this embodiment, the conductor layer 17 is etched to irradiate the exposed portion 16 where the insulator layer 16 is exposed with laser light. However, the conductor layer 17 is oxidized, A black oxide film may be formed on the surface, and laser light may be irradiated through the oxide film. Since the oxide film is black, reflection of laser light can be avoided, and the conductor layer 17 and the insulator layer 16 thereunder can be prevented.
And can be removed simultaneously.

The oxidation treatment can be performed, for example, as follows.

First, in order to remove oil adhering to the surface of the conductive layer 17, the conductive layer 17 is washed with an aqueous sodium hydroxide solution and degreased. Next, the degreased conductor layer 17 is treated with a soft etching agent (sodium persulfate / sulfuric acid solution), and further, is pickled with sulfuric acid to remove a hydroxide formed by the soft etching agent. And
By treating the pickled conductor layer 17 with an oxidizing agent, a black oxide film is formed. As the oxidizing agent, a mixed solution of sodium hydroxide, sodium chlorite, trisodium phosphate and the like can be used.

The oxide film is removed by a soft etching agent when plating on the conductor layer 17. Therefore, there is no inconvenience even if the oxide film is left as it is after the laser beam irradiation.

In the multilayer printed wiring board 18 shown in FIG. 11, the land diameter connected to the via 11a can be made smaller than the land diameter connected to the bump 7 in the wiring layer 6, and the wiring pattern 14 can be made denser. I was able to.
Further, since the wiring pattern 14 is connected to the bump 7 by the via 11a formed by the plating, excellent connection reliability with the wiring layer 6 can be obtained, and the conductor layer 17 is also laminated. Excellent connection reliability with the wiring layer 6 can be obtained via the wiring pattern 14 provided.

In the second embodiment of the present embodiment, as described above, the insulator layer 16 having the conductor layer 17 is laminated on the multilayer wiring board 1. The body layer 17 may not be provided. In this case, the hole 11 is formed by directly irradiating the portion of the insulator layer 16 where the base 7a of the bump 7 is exposed with laser light. Then, the conductor layer 1 is formed in the same manner as in the first embodiment.
3 and the wiring pattern 14 can be formed.

In each of the embodiments of the present embodiment, the wiring pattern 14 is provided for heat-resistant coating and protection from the external environment.
It is preferable to apply an insulating ink thereon to form a resist having a thickness of, for example, 20 μm.

[Brief description of the drawings]

FIG. 1 is an explanatory cross-sectional view showing one configuration example of a multilayer wiring board used in a manufacturing method of the present invention.

FIG. 2 is an explanatory sectional view showing a method for manufacturing the multilayer wiring board shown in FIG. 1;

FIG. 3 is an explanatory cross-sectional view showing a step of the first embodiment of the manufacturing method of the present invention.

FIG. 4 is an explanatory cross-sectional view showing a step of the first embodiment of the manufacturing method of the present invention.

FIG. 5 is an explanatory sectional view showing a step of the first embodiment of the manufacturing method of the present invention.

FIG. 6 is an explanatory sectional view showing a step of the first embodiment of the manufacturing method of the present invention.

FIG. 7 is an illustrative sectional view showing a step of the first embodiment of the manufacturing method of the present invention.

FIG. 8 is an explanatory sectional view showing a step of the second aspect of the manufacturing method of the present invention.

FIG. 9 is an explanatory sectional view showing a step of the second aspect of the manufacturing method of the present invention.

FIG. 10 is an illustrative sectional view showing a step in the second embodiment of the manufacturing method of the present invention.

FIG. 11 is an explanatory sectional view showing a step of the second aspect of the manufacturing method of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board, 2, 6 ... Wiring layer, 5 ... First insulator layer, 7 ... Bump, 9 ... Photocurable resin layer, 9
a, 16: second insulator layer, 10: photoresist,
11: hole, 13: first conductive layer, 14: wiring pattern, 17: second conductive layer.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Shoji Fujisawa 573-19 Toiso, Eniwa-shi, Hokkaido Clover Electronics Co., Ltd. Inside the Hokkaido Plant (72) Inventor Masaru Ogasawara 573-19 Toiso, Eniwa-shi, Hokkaido Clover Electronics Co., Ltd. F-term in the Hokkaido factory (reference)

Claims (5)

[Claims] An outermost wiring layer connected to an adjacent wiring layer via a first insulator layer by a bump penetrating the first insulator layer; Removing at least a part of the wiring layer to expose a part of the base of the bump; and forming a second insulator layer made of a synthetic resin on the wiring layer where the base of the bump is exposed. Forming a hole exposing the base of the bump in the second insulator layer; plating the second insulator layer and the hole to form the second insulating layer; The first conductor layer is formed by plating on the body layer, and the first conductor layer is formed by plating on the hole.
Forming a via connecting the conductive layer and the base of the bump, and forming a predetermined wiring pattern by etching the first conductive layer. Substrate manufacturing method. 2. The method according to claim 1, wherein the second insulating layer is made of a photocurable resin layer, and a photoresist is formed on a surface of the photocurable resin layer so as to cover a portion where a base of the bump is exposed. After exposing and curing the photocurable resin layer using a photoresist as a mask, the unexposed portion of the photocurable resin is removed to form a hole that exposes the base of the bump. The method for manufacturing a multilayer printed wiring board according to claim 1. 3. The method according to claim 1, wherein the second insulator layer is made of a non-light-curable resin layer, and the surface of the non-light-curable resin layer is irradiated with laser light to form a hole exposing a base of the bump. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein: 4. The non-photocurable resin layer includes a second conductor layer on a surface opposite to a surface laminated on the multilayer wiring board, and etching the second conductor layer, The second conductive layer at a portion where the base of the bump is exposed is peeled off, and the non-light-curable resin layer at the portion where the second conductive layer is peeled off is irradiated with laser light to form the base of the bump. Forming a hole that exposes the first conductive layer; and plating the second conductive layer and the hole to form a first conductive layer by plating performed on the second conductive layer. Forming a via connecting the first conductive layer and the base of the bump by plating applied to the hole; and forming a predetermined wiring pattern by etching both conductive layers. 4. The method for manufacturing a multilayer printed wiring board according to claim 3, comprising: 5. The non-photocurable resin layer includes a second conductor layer on a surface opposite to a surface laminated on the multilayer wiring board, and oxidizes the second conductor layer. Forming a black oxide film, irradiating a laser beam through the oxide film on a portion where the base of the bump is exposed, and forming a hole exposing the base of the bump; The first conductor layer is formed by plating on the body layer and the hole, and the first conductor layer is formed by plating on the second conductor layer, and the first conductor is formed by plating on the hole. 4. The multi-layer printing method according to claim 3, further comprising a step of forming a via connecting the body layer and the base of the bump, and a step of forming a predetermined wiring pattern by etching both conductor layers. Manufacturing method of wiring board.