JP2000227456A - Scan flip-flop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out a sure scan test by holding a signal outputted from a multiplexer in a data latch circuit before the signal held in the data latch circuit is held in FF synchronously with a clock signal. SOLUTION: Input signals D1, D2 are inputted to three-state inverters 12, 14 individually, and its output is short-circuited to be inputted to an inverter 16. By means of an FF 20, an output of the inverter 16 is inputted to a data input and a clock signal CK is inputted to a clock input, and an output signal Q is outputted from its output. A bus holder 18 is connected to an input of the inverter 16. A scan enable signal is varied before the clock signal CK in the FF 20 is actuated, and a reverse signal for the input signal D1 or D2 is previously held in the bus holder 18. Subsequently, the reverse signal held in the bus holder 18 is reversed by an inverter 16 to be held in the FF 20 when the clock signal CK is actuated. In this way, a shift operation can be secured without causing any shift erroneous operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a scan flip-flop used as a test circuit for improving controllability and observability of an internal circuit of a semiconductor device.

[0002]

2. Description of the Related Art FIG. 5 is a conceptual diagram showing an example of a conventional scan flip-flop. The scan flip-flop 34 shown in the figure is used in place of a normal flip-flop as the above-mentioned test circuit, and selects either the input signal D1 or the input signal D0 according to the state of the scan enable signal S. And a flip-flop 38 for holding the output signal of the multiplexer 36 in synchronization with the clock signal CK.
And

Here, the inputs 1, 0 of the multiplexer 36 are
, Input signals D1 and D0 are respectively inputted, a scan enable signal S is inputted to a selection input thereof, and an output signal thereof is inputted to a data input of the flip-flop 38. The clock signal CK is input to the clock input of the flip-flop 38,
Output an output signal Q.

In the scan flip-flop 34,
When the scan enable signal S is at the high level, the input signal D1 is output from the multiplexer 36, whereas when the scan enable signal S is at the low level, the input signal D0 is output. And the multiplexer 36
Is held in the flip-flop 38 in synchronization with the rising timing of the clock signal CK, and is output as the output signal Q.

FIG. 6 shows a conceptual diagram of an example of a scan circuit configured using a conventional scan flip-flop. The scan circuit 40 in the illustrated example is an example of a test circuit configured by using the scan flip-flops 34 shown in FIG. 5, and a scan chain (shift register) is formed by connecting a plurality of scan flip-flops 34 in series. It is configured. Note that FIG.
Two scan flip-flops 34 are shown.

The output signal from the internal circuit 42 is input to the input 0 of the multiplexer 36 of the scan flip-flop 34, and the output signal from the preceding scan flip-flop 34 is input to the input 1. The output of each scan flip-flop 34 is also input to the internal circuit 42. The clock signal is supplied to buffer 4
4 to each scan flip-flop 34. Note that the scan enable signal S is omitted in FIG.

In the scan circuit 40, first, when the scan enable signal is set to low level, the output signal of the internal circuit 42 is output from the multiplexer 36,
The data is held in the flip-flop 38 in synchronization with the clock signal. Thereafter, when the scan enable signal is set to a high level, the output signal of the preceding scan flip-flop 34 is output from the multiplexer 36 and is held in the flip-flop 38 of the next scan flip-flop 34 in synchronization with the clock signal. .

Therefore, for example, the input 1 of the multiplexer 36 of the first-stage scan flip-flop 34 is connected to the input terminal for scan input, and the output signal of the last-stage scan flip-flop 34 is connected to the output terminal for scan output. By doing so, a signal input from the scan input is set in the scan flip-flop 34 to control the internal circuit 42, or the state of the internal circuit 42 is taken in the scan flip-flop 34 and output from the scan output for confirmation. can do.

The signal held in each scan flip-flop 34 is sequentially shifted to the next-stage scan flip-flop 34 in synchronization with the clock signal. At this time, depending on the routing of the clock signal wiring, a delay 46 due to the wiring occurs as conceptually shown in FIG. 6, and the clock signal inputted to the preceding scan flip-flop 34 is more than the clock signal inputted to the preceding scan flip-flop 34. In some cases, the clock signal input to the input terminal 34 is slower.

In this case, when the output signal of the preceding scan flip-flop changes in synchronization with the clock signal input to the preceding scan flip-flop, the clock signal of the subsequent scan flip-flop changes. , The subsequent scan flip-flop 34
In this case, the output signal after the change of the scan flip-flop 34 in the preceding stage is fetched, which causes a shift malfunction such that one clock is shifted by two clocks.

In order to solve this problem, conventionally, for example, a buffer is inserted into the output signal of the preceding scan flip-flop 34 to delay the signal, or the automatic placement and routing is performed again, so that the output signal of the preceding and subsequent scan flip-flop 34 is reduced. By making the skew of the input clock signal fall within the allowable range, the output signal of the preceding scan flip-flop 34 is prevented from penetrating into the subsequent scan flip-flop 34 by one clock.

However, as described above, even if the output signal of the preceding scan flip-flop 34 is delayed or the automatic placement and routing is performed again, for example, the manufacturing process,
The delay time of the output signal and the clock signal of the scan flip-flop 34 fluctuates due to the influence of fluctuations in voltage, temperature, and the like. There was a problem that it was not known whether it could be done.

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan flip-flop capable of preventing a shift malfunction due to a skew of a clock signal and reliably performing a scan test, in view of the problems based on the prior art. To provide.

[0014]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a first method which is not simultaneously active.
And a multiplexer for outputting a first or second input signal corresponding to the first or second control signal in an active state only while the second or third control signal is in an active state; A data latch circuit for holding a signal output from the multiplexer while a control signal is in an active state, and a flip-flop for holding a signal held in the data latch circuit in synchronization with a clock signal, A signal output from the multiplexer is held in the data latch circuit before the signal held in the latch circuit is held in the flip-flop in synchronization with the clock signal. Offer

Here, before the signal held in the data latch circuit is held in the flip-flop in synchronization with the clock signal, means for holding the signal output from the multiplexer in the data latch circuit. A control signal generating circuit for generating the first and second control signals having a predetermined pulse width in accordance with the timing at which the scan enable signal changes, and providing the output control signal to the multiplexer of each of the scan flip-flops By supplying it to

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a scan flip-flop according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a conceptual diagram showing the configuration of an embodiment of a scan flip-flop according to the present invention. The illustrated scan flip-flop 10 is used in place of a normal flip-flop to configure a scan circuit.
The inverter includes three-state inverters 12 and 14 as an example of the multiplexer of the present invention, an inverter 16, a bus holder (BH) 18 as an example of the data latch circuit of the present invention, and a flip-flop 20.

Here, the three-state inverters 12, 14
Are input signals D1 and D0, respectively.
The outputs are short-circuited and input to the inverter 16. The output of the inverter 16 is a flip-flop 20
, A clock signal CK is input to a clock input of the flip-flop 20, and an output signal Q is output from the flip-flop 20. Also,
The bus holder 18 is connected to an input of the inverter 16.

A control signal SB and its inverted signal SB # are input to the control input and its inverted input of the three-state inverter 12, respectively, and a control signal and an inverted signal thereof are respectively input to the control input and its inverted input of the three-state inverter 14. SN and its inverted signal SN # are input. These control signals SB, SB # and control signal S
N and SN are both pulse signals having a predetermined pulse width, as described below, and only one of them is active at the same time.

FIG. 2A is a conceptual diagram of one embodiment of a control signal generating circuit, and FIG. 2B is a timing chart of one embodiment showing the operation thereof. The control signal generation circuit 22 shown in FIG. 2A includes control signals SB, SB # and control signals SN, SN # input to the control inputs of the three-state inverters 12, 14 shown in FIG.
Rise / fall detection circuit 24
And an OR gate 26.

The rising / falling detection circuit 24 receives a scan enable signal S, and the rising / falling detection circuit 24 outputs control signals SB and SN '. The control signal SN ′ is input to one input of the OR gate 26, the scan test signal SCAN_TEST is input to the other inverted input, and the control signal SN is output from the OR gate 26. Note that, in the figure, the control signal S which is an inverted signal of the control signals SB and NB is
B # and NB # are omitted.

In the case of the present embodiment, the rising / falling detecting circuit 24 detects the rising timing of the scan enable signal S and determines a predetermined timing from the rising timing, as shown in the timing chart of FIG. Generates a control signal SB having a pulse width of
A falling timing of the scan enable signal is detected, and a control signal SN ′ having a predetermined pulse width, that is, a control signal SN is generated from the falling timing.

Scan test signal SCAN_TEST
Is a test signal for switching between the normal operation mode and the scan test mode. In the case of the present embodiment, when the scan test signal SCAN_TEST is at the low level, the normal operation mode is set, and the scan enable signal S is also at the low level, so that the control signals SB and SN are fixed to the low level and the high level, respectively. Therefore, 3
The state inverters 12 and 14 are turned off and on, respectively, and the input signal D0 is held in the flip-flop 20 in synchronization with the clock signal CK.

On the other hand, scan test signal SCAN
When _TEST is at a high level, the scan test mode is set and the control signal S output from the control signal generation circuit 22 is set.
B and SN '(SN) operate at the timing shown in FIG. That is, when the scan enable signal S rises, the control signal SB is generated, and only when the control signal SB is at the high level, the three-state inverter 12 is turned on, and the inverted signal of the input signal D1 is held in the bus holder 18. .

Similarly, when the scan enable signal S falls, a control signal SN is generated, and only when the control signal SN is at the high level is the three-state inverter 14 switched off.
Is turned on, and the inverted signal of the input signal D0 is held in the bus holder 18. The inverted signal held in the bus holder 18 is inverted by the inverter 16 and is held in the flip-flop 20 at the rising timing of the clock signal CK and is output as the output signal Q.

That is, in the scan flip-flop 10 of the present invention, the clock signal C
By changing the scan enable signal S before K rises to a high level, an input signal D1 or an inverted signal of the input signal D0 can be held in the bus holder 18 in advance. Then, the bus holder 18
Is further inverted by the inverter, and is held in the flip-flop 20 at the rise of the clock signal CK.

The scan flip-flop 10 of the present invention is configured as one macro cell.
Here, instead of the three-state inverters 12 and 14, 3
A state buffer or the like may be used, and in this case, the inverter 16 is unnecessary. Although the bus latch is illustrated as the data latch circuit of the present invention, any conventionally known data latch circuit that holds data can be applied.
In addition, as the rise / fall detection circuit 24, all conventionally known circuits can be applied.

The clock input of the flip-flop 20 may be a positive edge type shown in the illustrated example or a negative edge type opposite thereto. The scan test signal SCAN_TEST may be provided exclusively for testing a scan circuit formed by using the scan flip-flop of the present invention. However, usually, a semiconductor device has a dedicated test for individually testing internal function blocks. It is preferable to use these input terminals and internal registers.

FIG. 3 is a conceptual diagram showing the configuration of an embodiment of a scan circuit using the scan flip-flop of the present invention. The scan circuit 28 in the illustrated example includes:
A scan chain (shift register) by connecting a plurality of scan flip-flops 10 of the present invention shown in FIG. 1 in series.
This is an example of the case where is configured. In FIG. 1, two scan flip-flops 10 are shown for easy comparison with the prior art.

The input D0 of the scan flip-flop 10
The internal circuit 30 (input of the three-state inverter 14)
The output signal from the preceding scan flip-flop 10 is input to the input D1 (input of the three-state inverter 12). Control signals SB and SN are input to each scan flip-flop 10, and the output is also input to the internal circuit 30. Further, a clock signal CK is supplied to each scan flip-flop 10.

The operation of the scan circuit 28 shown in FIG. 3 will be described below with reference to the timing chart shown in FIG. As shown in FIG. 3, in the following description, the clock signals input to the preceding (left side in the figure) and subsequent (right side in the figure) scan flip-flops 10 are clock signals CK1 and CK2, respectively. Are output signals Q1 and Q2, respectively. Also, the same reference numerals are used in the timing chart of FIG.

Here, the clock signal CK2 input to the subsequent scan flip-flop 10 is, as conceptually shown in the scan circuit 28 of FIG. 3, from the clock signal CK to the clock input of the subsequent scan flip-flop 10. As shown in the timing chart of FIG. 4, it is assumed that the clock signal CK1 input to the preceding-stage scan flip-flop 10 is delayed by a predetermined time due to the delay 32 caused by the routed wiring.

Therefore, in the case of the conventional scan circuit 40 shown in FIG. 6, after the output signal of the preceding scan flip-flop 34 (left side in the figure) changes in synchronization with the rising timing of the clock signal CK1, the clock signal is changed. Since CK2 rises, the output signal after the change of the preceding scan flip-flop 34 is held in the subsequent scan flip-flop 34 (right side in the figure) in synchronization with the rising timing of the clock signal CK2, and a shift malfunction occurs. .

On the other hand, in the scan circuit 28 of the present invention shown in FIG. 3, first, before the rising timing of the clock signal CK1, that is, the output signal (data1, 2, 3, 3) of the preceding scan flip-flop 10
..) Change, the scan enable signal S rises. As a result, the control signal SB becomes the high level which is in the active state for a predetermined fixed time, and the output signal of the preceding scan flip-flop 10 before the change is held in the bus holder 18 of the subsequent scan flip-flop 10.

Subsequently, as shown in the timing chart of FIG. 4, after the output signal of the preceding scan flip-flop 10 before the change is held in the bus holder 18 of the subsequent scan flip-flop 10, the clock signal CK1 is output.
Rises, and the output signal of the preceding scan flip-flop 10 changes. After that, the clock signal CK2 rises, and the subsequent scan flip-flop 10
The signal held in the bus holder 18 is held.

That is, the output signal of the preceding scan flip-flop 10 before the change is correctly held in the subsequent scan flip-flop 10. As described above, according to the scan flip-flop 10 of the present invention, in the scan circuit 28, the clock signal CK2 of the subsequent scan flip-flop 10 is delayed more than the clock signal CK1 of the preceding scan flip-flop 10. Also, a scan test can be performed reliably and normally without causing a shift malfunction.

Subsequently, the scan enable signal S falls in preparation for the next clock cycle. At this time, similarly, the control signal SN becomes the high level which is in the active state for a predetermined fixed time, and the output signal of the internal circuit 30 is temporarily held in the bus holder 18 of the subsequent scan flip-flop 10. The output signal of the internal circuit 30 held by the bus holder 18 is the clock signal CK2
Does not rise and is not held in the flip-flop 20.

Thereafter, the above-described operation is repeatedly performed, and the output signal of the preceding-stage scan flip-flop 10 is shifted to the subsequent-stage scan flip-flop 10 every time the clock signal CK rises. Although the scan flip-flop of the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and various improvements and changes may be made without departing from the gist of the present invention. is there.

[0039]

As described above in detail, in the scan flip-flop of the present invention, the signal held in the data latch circuit is output from the multiplexer before being held in the flip-flop in synchronization with the clock signal. Is held in the data latch circuit. Thus, according to the scan flip-flop of the present invention, in the scan circuit, the output signal of the preceding scan flip-flop changes in synchronization with the clock signal, and then the clock signal input to the subsequent scan flip-flop changes. Even in such a case, it is possible to completely guarantee the shift operation in the scan circuit without causing a shift malfunction and without the need for labor and time for redoing the automatic arrangement and wiring.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating the configuration of an embodiment of a scan flip-flop according to the present invention.

FIG. 2A is a conceptual diagram of one embodiment of a control signal generation circuit, and FIG. 2B is a timing chart of one embodiment showing an operation thereof.

FIG. 3 is a conceptual diagram of a configuration of an embodiment of a scan circuit configured using the scan flip-flop of the present invention.

FIG. 4 is a timing chart illustrating an operation of the scan circuit illustrated in FIG. 3 according to an embodiment;

FIG. 5 is a conceptual diagram illustrating an example of a conventional scan flip-flop.

FIG. 6 is a configuration conceptual diagram of an example of a scan circuit configured using a conventional scan flip-flop.

[Explanation of symbols]

 10, 34 scan flip-flop 12, 14 3-state inverter 16 inverter 18 bus holder 20, 38 flip-flop 22 control signal generation circuit 24 rise / fall detection circuit 26 OR gate 28, 40 scan circuit 30, 42 internal circuit 32, 46 Delay 36 Multiplexer 44 Buffer D1, D0 Input signal Q, Q1, Q2 Output signal SB, SB #, SN ', SN, SN # Control signal CK, CK1, CK2 Clock signal S Scan enable signal SCAN_TEST Scan test signal

Claims (1)

[Claims] 1. A first or second input signal corresponding to an active state of the first or second control signal, respectively, only while the first and second control signals which are not simultaneously active are in the active state. , A data latch circuit for holding a signal output from the multiplexer while the first or second control signal is in an active state, and synchronizing a signal held in the data latch circuit with a clock signal. Before the signal held in the data latch circuit is held in the flip-flop in synchronization with the clock signal, the signal output from the multiplexer is stored in the data latch. A scan flip-flop which is stored in a circuit.