JP2000182872A - Chip inductor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip inductor which can use various sorts of substrate materials and have a high end electrode mounting strength and an superior processing workability and cost. SOLUTION: In the manufacture of a chip inductor, an interlayer insulating layer 4 is formed over the entire surface of an insulating substrate 1, except for external electrode patterns 2a and 2b and a spiral pattern 2c. Then a conductor layer 5 is formed by electroplating on the patterns 2a, 2b and 2c to provide a conductor pattern surrounded by the interlayer insulating layer 4. Since an external electrode is formed simultaneously with the formation of an element, its mounting strength becomes high. Since vacuum coating is not adopted, its processing workability is improved, its processing cost is suppressed, and at the same time various sorts of substrate materials can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip inductor used for an electronic device such as a mobile phone and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, miniaturization of electronic devices such as cellular phones,
With the increase in integration and frequency, demand for chip-type inductance elements that are small and surface-mountable, that is, chip inductors, is rapidly increasing.

As such a chip inductor, a mold type chip inductor manufactured by mounting a winding as a separate body on a substrate and covering the whole with a resin, a green sheet or paste of ferrite or ceramic is used. A multilayer chip inductor manufactured by alternately laminating and printing conductors and insulators and then firing, and a spiral inductor pattern (spiral conductor pattern) formed on an insulating substrate, for example. At present, flat chip inductors that are advantageous from the viewpoint of miniaturization, integration, narrow tolerance characteristics, and the like are mainly used.

Conventionally, in the manufacture of a planar chip inductor, a spiral conductive pattern, together with a terminal electrode (external electrode) connected to an outer peripheral end thereof, is subjected to a thick film method of applying and baking a conductive paste, or vacuum plating such as vapor deposition and sputtering. After the film is formed on the substrate using a method or the like, a pattern is formed by etching mainly by wet etching, and then, the inner peripheral end of the conductor pattern is provided on the conductor pattern, for example, a gap, an insulating paste or an insulating resin. The lead electrode is connected to a terminal electrode different from the outer peripheral end on the conductor pattern forming surface side through a hole penetrating the insulating layer made of the like, or on the back surface side of the conductor pattern forming surface through a hole penetrating the substrate. It is common to form them (for example, JP-A-9-129471, JP-A-9-191167).
And JP-A-9-199365).

Then, for example, a V-shaped groove is formed by a V-cut machine (slitter) and divided into chips, or a chip is formed by dicing with a dicing saw. Thereafter, both ends of the chip are formed inside the chip. An external electrode is completed by forming an end face electrode so as to be connected to the electrode.

At this time, it is desirable to increase the thickness of the conductor pattern, suppress the conductor resistance of the conductor pattern, and improve the Q characteristic.

[0007]

However, the conventional method for manufacturing a chip inductor as described above has the following problems. That is, in the conventional manufacturing method, if the thickness of the spiral conductive paste is increased by improving the inductance obtaining range and the Q characteristic, the etching time after the film formation becomes longer. As shown in FIG. 7, not only the intended depth direction but also the side direction is corroded, and side etching occurs, thereby reducing the dimensional accuracy of the conductor pattern, thereby increasing the variation in inductance characteristics. In order to avoid this, it has been proposed to provide a concave portion having the same pattern as the conductor pattern on the substrate in advance to increase the film thickness (see Japanese Patent Application Laid-Open No. 9-129471). There is a problem in the point.

Further, the vacuum plating method such as evaporation or sputtering, which is generally used for forming a conductor pattern by a conventional method, gives a strong thermal stress to a member such as a substrate. It is necessary to select the material to be used in consideration of the above, and the conventional manufacturing method employing the vacuum plating method has a problem that usable substrate materials are limited.

In a conventional method for manufacturing a chip inductor, an external electrode, particularly an extraction electrode of an inductor having a spiral conductor pattern, is often formed by a vacuum plating method or the like before and after the device is manufactured. There is also a problem that the terminal connection is made at a temperature that does not affect the element at the same time as being exposed to strong thermal stress many times, and there is a limit to the improvement of the strength of the external electrode.

In the chip forming step, chips are formed by forming a groove by a slitter after the device is manufactured, and are divided into chips by dicing with a dicing saw, and chips are formed by a chocolate break method using a substrate having a snap. Although it is more disadvantageous in terms of workability and processing cost than conversion, the conventional manufacturing method uses a vacuum-injection method, so a chip with a chocolate break method using a relatively weak stress-resistant snap-in board is used. There was also a problem that it was difficult to achieve this. Further, for the same reason, it is very difficult to employ a slit-embedded substrate that is more stress-resistant.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is capable of adopting a wider range of substrate materials than conventional ones, has high external electrode attachment strength, and is excellent in processing workability and processing cost. An inductor and a method for manufacturing the inductor are provided.

[0012]

In order to solve the above-mentioned problems, a method of manufacturing a chip inductor according to the present invention comprises a step of forming a conductive ultra-thin film on a slit-filled insulating substrate; Forming a resist in a pattern forming region, removing the conductive ultra-thin film other than the resist forming region, removing the resist, and interlayer insulating in a region other than the conductive pattern forming region comprising the conductive ultra-thin film It is characterized by including at least a step of forming a layer and a step of forming a conductor layer by electrolytic plating on a conductor pattern formation region surrounded by the interlayer insulating layer. With such a configuration, the method for manufacturing a chip inductor of the present invention minimizes side etching, so that a chip inductor having a conductor pattern with a high aspect ratio and excellent in high-frequency characteristics can be provided.

In order to solve the above-mentioned problems, a method of manufacturing a chip inductor according to the present invention comprises a step of forming a conductive ultra-thin film on an insulating substrate with slits, a conductive pattern forming region on the conductive ultra-thin film and an external electrode Forming a resist in a formation region, removing the conductive ultra-thin film other than the resist formation region, removing the resist,
Forming an interlayer insulating layer in a region other than the conductive pattern forming region and the external electrode forming region made of the conductive ultrathin film; and forming the conductive pattern forming region and the external electrode forming region surrounded by the interlayer insulating layer. The method is characterized by including at least a step of forming a conductor layer thereon by an electrolytic plating method. With such a configuration, the method for manufacturing a chip inductor of the present invention provides a chip inductor having a high aspect ratio and a conductor pattern having a high aspect ratio while minimizing side etching, and at the same time as forming an element, forming an external electrode. Can be formed to provide a chip inductor having a high-strength external electrode.

Preferably, in claims 1 and 2,
It does not include a vacuum plating step. With such a configuration, the selection range of the substrate to be used is widened, and the manufacturing cost can be reduced.

Preferably, in claim 1 to 3, the insulating substrate with slits further has a snap, and the conductor patterns are mutually separated for each pattern formed by the slits and snaps of the insulating substrate with slits. The method is further characterized in that the method further comprises a step of independently forming and forming a chip by a chocolate break method using a snap of the snap-on insulating substrate after forming the conductor pattern. With such a configuration, a chip inductor can be manufactured at a lower cost with better workability than before.

Further, in order to solve the above problems, a chip inductor according to the present invention is manufactured by the method for manufacturing a chip inductor according to any one of claims 1 to 4. With such a configuration, the chip inductor of the present invention has a conductor pattern with a high aspect ratio and is a chip inductor excellent in high-frequency characteristics.

Further, in order to solve the above problems, a chip inductor according to the present invention is characterized in that it has a conductor pattern having an aspect ratio in a range of 1 to 10. With such a configuration, the chip inductor of the present invention has excellent high-frequency characteristics.

Preferably, in claim 6, the conductive pattern is formed of a conductive ultra-thin film and a conductive layer. With such a configuration, the conductor pattern can easily have a high aspect ratio.

[0019] Preferably, in Claims 6 and 7, further comprising an interlayer insulating layer having at least the same thickness as the conductor pattern, and a protective layer covering the conductor pattern and the interlayer insulating layer. I do. With such a configuration, the conductor pattern can be easily and inexpensively made to have a high aspect ratio.

Preferably, in claim 6 to 8, the conductor pattern is a spiral conductor pattern, and an external electrode, a lead electrode and a conductor pattern are formed directly on the substrate. . With such a configuration, it is possible to manufacture a chip inductor in which the attachment strength of the external electrode is improved more easily and cheaply than before.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a chip inductor according to the present invention will be described in more detail with reference to the drawings, taking one embodiment as an example.

FIGS. 1 to 5 are diagrams schematically showing a manufacturing process of an embodiment of a chip inductor according to the present invention.
2 (a) to 5 (j) are partially enlarged views in which one of the chips formed based on the slit of the slit-inserted substrate is enlarged and shown. The figure on the side is a cross-sectional view taken along line II shown in the figure on the upper side of FIG.

First, in manufacturing the chip inductor of the present invention, as shown in FIG. 1, it is desirable to use an insulating substrate 1 provided with a commercially available or self-made slit (1-A). By using the insulating substrate 1 with slits, the advantage of the present invention that a wide range of substrate materials can be used by not employing the vacuum plating method is remarkably exhibited. The insulating substrate with slits 1 used in the present invention is not particularly limited, and can be freely selected from conventional insulating substrates in consideration of dielectric constant, strength, cost and the like. A substrate or an organic substrate such as a liquid crystal polymer can be suitably used. Further, there is no limitation on the shape of the slit provided on the substrate, and the slit can have a desired shape. Further, FIGS. 6A to 7
As shown in (e), by providing a snap orthogonal to the slit, a chip can be manufactured independently for each pattern formed by the slit and the snap. In this case, the snaps 1-A provided on the insulating substrate 1 may be provided on both or one of the upper and lower surfaces of the substrate, or may be provided penetrating both surfaces. If necessary, a through hole may be provided at an appropriate position on the substrate (see FIG. 7E). In FIGS. 6 and 7, slits are shown as white areas surrounded by solid lines, snaps are shown as dotted lines,
The through holes are shown as black circles.

FIG. 2A shows the insulating substrate 1 with the slit.
2 shows a state in which a conductive metal such as copper is applied to the surface by a technique such as electroless plating to form a conductive ultrathin film 2. The thickness of the conductive ultrathin film 2 is usually 0.05 to 3.0.
It can be about μm, preferably about 0.1 to 1.0 μm. However, if desired, an external electrode pattern and a spiral pattern are formed by directly providing an interlayer insulating layer 4 described later on the substrate 1 without providing the conductive ultrathin film 2, and forming an external electrode pattern and a spiral pattern on the pattern region. The conductor layer 5 can be formed by an electroless plating method.

FIG. 2 (b) shows the resist 3 formed by photolithography or laser or the like by masking the external electrode pattern forming region and the spiral pattern forming region of the conductive ultra-thin film 2 formed in FIG. 2 (a). The state in which it was formed is shown. The material of the resist 3 is not particularly limited.
It can be freely selected from commonly used resist materials. At this time, in FIG. 2B, the resist 3 is formed so as to cover the conductive ultrathin film 2 along the side surface of the slit, but between the external electrode patterns of two chips facing each other with the slit interposed therebetween. It can also be formed so as to span a bridge so as to bridge the bridge, that is, to cover the slit with a lid.

FIG. 2C shows an external electrode pattern 2 which is obtained by removing the conductive ultrathin film 2 exposed in a region other than the region covered with the resist 3 in FIG. 2B by etching or the like.
a and 2b and a spiral pattern 2c connected to one external electrode 2a are shown.

FIG. 3D shows a state in which the insulating substrate 1 with slits is immersed in a stripping solution to dissolve and remove the resist 3 in accordance with a conventional method.

FIG. 3E shows the external electrode pattern 2.
This shows a state in which an interlayer insulating layer 4 is formed by photolithography or the like while masking regions other than a, 2b and the spiral pattern 2c. The material of the interlayer insulating layer 4 is not particularly limited, and can be freely selected from commonly used insulating materials, for example, an organic insulating material such as a polyimide resin or an epoxy resin or an inorganic insulating material such as a glass paste. . The thickness of the interlayer insulating layer 4 is at least equal to or greater than the thickness of the spiral conductor pattern finally formed, and is preferably the same as the thickness of the spiral conductor pattern.

FIG. 3 (f) shows a method in which a conductive metal such as copper is applied to the external electrode pattern and the spiral pattern surrounded by the interlayer insulating layer 4 of FIG. 3 (e) by a technique such as electrolytic plating. The state where the conductor layer 5 is formed is shown. The material of the conductive layer 5 is not particularly limited as long as it is a conductive material, but is usually a conductive metal such as copper or silver, and may be the same material as the conductive ultrathin film 2. Alternatively, it can be a different material. The spiral conductor pattern formed at this time, that is, the spiral pattern 2c and the conductor layer 5
Although the spiral conductor pattern made of is superior in electrical characteristics as the aspect ratio is higher, it is usually 1 in consideration of cost and the like.
The aspect ratio ranges from 10 to 10, preferably from 1.5 to 3.

FIG. 4 (g) shows a state where contacts 7, 8 and 9 are formed by photolithography or laser or the like after printing the upper insulating layer 6 on the entire upper surface of the substrate 1. The insulating material constituting the upper insulating layer 6 is not particularly limited as long as it has a low dielectric constant and can secure insulation. For example, as the organic material, a resin such as a liquid crystal polymer, a polyimide resin or an epoxy resin is used. Examples of the composition and the inorganic material include a glass paste and the like.

FIG. 4H shows a lead electrode pattern 10 for connecting the contacts 7 and 9 with the conductive metal such as copper by electroless plating or photolithography on the upper insulating layer 6. The state is shown. The extraction electrode pattern 10 can also be formed by screen-printing a conductive paste. The extraction electrode pattern 1
The material 0 is not particularly limited as long as it is a conductive material, but is usually a conductive metal such as copper or silver, and should be the same material as the conductive ultrathin film 2 and the conductive layer 5. Or different materials.

FIG. 4 (i) shows a state in which a protective layer 11 covering all the film formed on the upper surface of the substrate 1 is formed. The material of the protective layer 11 is not particularly limited as long as it can ensure insulation with a low dielectric constant.
Examples of the organic material include a resin composition such as a polyimide resin and an epoxy resin, and examples of the inorganic material include a glass paste. Since this protective layer 11 is provided for the purpose of mechanically protecting the product from the outside, it may be omitted depending on the use conditions of the product.

FIG. 5 (j) shows the insulating substrate 1 with the slit.
Is shown in the form of a chip by dividing the substrate in a direction perpendicular to the slit by a method commonly used in the art such as dicing. Of course,
When a substrate provided with both slits and snaps as shown in FIGS. 6 and 7 is used, a chip inductor can be obtained more easily and easily by a chocolate break method using snaps.

From FIG. 5 (j), in the present embodiment,
It can be seen that the conductive layer 5 is formed on the conductive ultrathin film 2 and integrally forms the external electrode and the spiral conductive pattern.

According to this embodiment, since the external electrodes are formed at the same time as the formation of the device, a strong electrode can be easily manufactured without fear of damaging the device. In addition, since the vacuum plating process is not included in the formation of the external electrodes, there is no need to limit the film thickness, and further, the processing time is shortened, the productivity is improved, and the material selection of the substrate and the like can be performed. Spreads.
Therefore, it is possible to use a substrate with a slit which has been conventionally difficult to employ, and furthermore, using a substrate provided with both slits and snaps, a chip can be easily and inexpensively formed by the chocolate break method.

Further, according to the present invention, even when a wet etching method is used for removing the conductive ultrathin film 2,
Since the thickness of the conductive ultra-thin film 2 to be removed by etching is thinner, the etching time is much shorter than before, so that severe side etching as shown in FIG. 9 occurs and the aspect ratio of the conductor pattern 13 under the mask 12 is reduced. Is not reduced and there is no possibility of non-uniformity. That is, as schematically shown in FIG. 10, in the present invention, a resist 3 is formed in a desired pattern on the conductive ultrathin film 2, and the conductive ultrathin film 2 in a region other than the pattern is removed by etching. Thereafter, the resist 3 is peeled off, and then an interlayer insulating layer 4 surrounding the conductive ultrathin film 2 is formed.
In the present invention, only the conductive ultra-thin film 2 is removed by etching, so that the etching time is much shorter than before, and no or little if any side etching occurs. . Therefore, the aspect ratio of the conductor pattern according to the conventional method is at most 0.3 to 0.5 due to the influence of side etching.
Despite the degree, for the first time according to the invention,
It has become possible to obtain a conductor pattern having a high aspect ratio of 0 uniformly.

Further, a part or all of the insulating material used for the chip inductor of the present invention, that is, a part or all of the insulating substrate 1, the interlayer insulating layer 4, the upper insulating layer 6, and the protective layer 11, may be made of a magnetic material such as ferrite. When a material made of a material or containing a magnetic material is used, the characteristics of the chip inductor of the present invention are slightly lower in high-frequency characteristics than when a material containing no magnetic material is used. Since the range is wide and the DC resistance value can be reduced, it can be used for applications other than the high frequency region, for example, for a power supply circuit of a portable electronic device.Accordingly, according to the present invention, when manufacturing a chip inductor, By selecting the materials used according to the characteristics and designing the product,
A chip inductor suitable for a very wide range of applications can be obtained.

Further, as a substrate used in the present invention, FIG.
By using a substrate provided with through holes as shown in FIG. 8E, an extraction electrode is formed as shown in FIG. 8A to omit the extraction electrode pattern 10, or as shown in FIG. In addition, it is also possible to provide a conductor pattern for connecting to different external electrodes on the front and back of the substrate and connect the internal terminations thereof to obtain a chip inductor without the extraction electrode itself.
FIGS. 8A and 8B are a top view of the chip inductor in order from the top and a broken line (II-I) in the top view.
I, III-III) are a cross-sectional view and a bottom view, and the symbols in the figures have the same meaning as the same symbols in FIGS. The chip inductor having such a structure can also be manufactured at a lower cost than the conventional one because the slit-embedded substrate can be used according to the present invention.

Although the present invention has been described above by exemplifying a chip inductor having a spiral conductor pattern,
The chip inductor of the present invention is not limited to this, but includes all planar chip inductors.

[0040]

As described above in detail, in the method for manufacturing a chip inductor and the chip inductor according to the present invention, no wet etching is performed, or even when wet etching is performed, the conductive material to be etched is extremely thin. Since only a short time is required compared to the conventional method, no or very little side etching occurs. When it is a conductor, the line pitch of the spiral conductor pattern can be reduced, and the maximum number of turns can be increased. Further, it is possible to expand the inductance obtaining range and improve the Q characteristic. Further, since the amount of the conductive material to be removed by etching is small, it is advantageous in terms of productivity and environmental problems due to waste.

In addition to the above, since the method of the present invention does not include a vacuum plating step, thermal stress applied to the substrate and the like is reduced, and no warpage is generated on the substrate. There is no need to limit the required film thickness. In addition, since there is no processing in a vacuum, restrictions on the outgassing property of the used material are relaxed. Further, since no evacuation or atmosphericization is required, the processing time is shortened, the productivity is improved, and the range of material selection for the substrate and the like is widened.

In the present invention, since the external electrodes are formed at the same time as the formation of the element, a strong electrode can be easily manufactured by a method such as printing of a conductive paste without damaging the element.

Further, in the present invention, since the electroplating method which does not cause stress on members is adopted as a method of forming a conductor pattern, a substrate provided with slits and, if desired, snaps is used, and a simple chocolate break method is used. In addition, chips can be formed at low cost.

From the above advantages, according to the present invention, it is possible to greatly reduce the total product cost.

[Brief description of the drawings]

FIG. 1 is a top view of a slit-containing insulating substrate used in an embodiment of a chip inductor according to the present invention.

FIG. 2 is a diagram schematically showing a part of a manufacturing process of one embodiment of a chip inductor according to the present invention.

FIG. 3 is a diagram schematically showing a part of a manufacturing process of one embodiment of a chip inductor according to the present invention.

FIG. 4 is a diagram schematically showing a part of a manufacturing process of one embodiment of a chip inductor according to the present invention.

FIG. 5 is a diagram schematically showing one embodiment of a chip inductor according to the present invention.

FIG. 6 is a diagram schematically illustrating a slit-containing insulating substrate that can be used in the present invention.

FIG. 7 is a diagram schematically illustrating a slit-containing insulating substrate that can be used in the present invention.

FIG. 8 is a diagram schematically showing an embodiment different from FIG. 5 of the chip inductor according to the present invention.

FIG. 9 is a diagram schematically showing side etching generated by a conventional manufacturing method.

FIG. 10 is a diagram illustrating a conductor pattern forming step in the method for manufacturing a chip inductor of the present invention.

[Explanation of symbols]

 Reference Signs List 1 substrate 1-A slit 2 conductive ultrathin film 2a external electrode pattern 2b external electrode pattern 2c spiral pattern 3 resist 4 interlayer insulating layer 5 conductive layer 6 upper insulating layer 7 contact 8 contact 9 contact 10 lead electrode pattern 11 protective layer 12 Mask 13 Conductor pattern

Claims (9)

[Claims] A step of forming a conductive ultra-thin film on the slit-filled insulating substrate; a step of forming a resist in a conductive pattern forming region on the conductive ultra-thin film; Removing, removing the resist, forming an interlayer insulating layer in a region other than the conductive pattern forming region made of the conductive ultrathin film, and on the conductive pattern forming region surrounded by the interlayer insulating layer At least including a step of forming a conductor layer by an electrolytic plating method. 2. A step of forming a conductive ultra-thin film on the slit-filled insulating substrate; a step of forming a resist in a conductive pattern forming region and an external electrode forming region on the conductive ultra-thin film; Removing the conductive ultra-thin film; removing the resist; forming an interlayer insulating layer in a region other than the conductive pattern forming region and the external electrode forming region formed of the conductive ultra-thin film; A method for manufacturing a chip inductor, comprising at least a step of forming a conductor layer by electrolytic plating on the conductor pattern formation region and the external electrode formation region surrounded by layers. 3. The method according to claim 1, wherein the method does not include a vacuum plating step. 4. The conductive pattern forming step further comprises forming the conductive pattern independently of each other by a pattern formed by the slit and the snap of the slit-containing insulating substrate. The method of manufacturing a chip inductor according to claim 1, further comprising a step of forming chips by a chocolate break method using a snap of the snap-on insulating substrate. 5. A chip inductor manufactured by the method for manufacturing a chip inductor according to claim 1. 6. A chip inductor having a conductor pattern having an aspect ratio in a range of 1 to 10. 7. The chip inductor according to claim 6, wherein the conductor pattern comprises a conductive ultra-thin film and a conductor layer. 8. The chip according to claim 6, further comprising an interlayer insulating layer having at least the same thickness as the conductor pattern, and a protective layer covering the conductor pattern and the interlayer insulating layer. Inductor. 9. The conductor pattern according to claim 6, wherein the conductor pattern is a spiral conductor pattern, and the external electrode pattern and the conductor pattern are formed directly on the substrate. Chip inductor.