JP2000013369A - Encryption circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the processing capability of a block encryption circuit. SOLUTION: In an encryption circuit, memory control sections 8 and 9 that extract a plain text from a memory and block encryption core sections 4, 14 are placed in parallel and respective encryption texts are used to generate a key for a succeeding plain text in cross-connection structure so as to enhance processing capability of the encryption circuit. Then a selector 20 is used to select a final encrypted text.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encryption circuit for realizing a block cipher.

[0002]

FIG. 3 shows a conventional block cipher and CCB.
It is a block diagram which shows the circuit structure of C (Converted-Cipher Block Chaining) system. In FIG. 3, FIG. 3A shows a basic unit 1 of the block cipher circuit.
Is composed of a block cipher function unit 3 having various contents according to the encryption method, and an exclusive OR circuit 2. The input plain text has a data width of 64 bits. First, the operation of the basic unit 1 of the block cipher circuit will be described. In the circuit of the basic unit 1, the input data is divided into upper 32 bits and lower 32 bits, and the upper 32 bits are processed by the block cipher function unit 3 and then exclusive. The logical sum circuit 2 calculates the sum with the lower 32 bits of data, sets the sum data as the upper bits of the next data, and sets the upper 32 bits of the input data as the lower bits of the next data.

FIG. 3 (2) shows a core portion of a block cipher, which includes N basic units 1 in series (π1, π2,
... ΠN) and a key data control unit 5 for performing a key schedule. The operation of the core part of this block cipher will be described. A key of 64 bits is generated by the key data control unit 5 from the input data of the key length of 40 bits, and the key is input to the above-mentioned basic unit 1, and the basic unit 1 is used N times. The encryption process is performed by repeating.

FIG. 3 (3) shows an encryption circuit of the CCBC system. In the CCBC system, in addition to the above-mentioned block cipher core unit 4, a CCBC function unit 7 for converting a ciphertext, and a CCBC function unit 7 An exclusive OR circuit 6 for taking an exclusive OR of the result and the current key data. The operation of the CCBC method will be described. First, a 64-bit ciphertext is also obtained from the input 64-bit plaintext data by the block cipher core unit 4, and then the CCBC is obtained.
The data is converted into 40-bit data by the function unit 7,
The exclusive OR with the current key is taken by the exclusive OR circuit 6, and the key data control unit 5 generates a 64-bit key to be used for the block cipher core unit 4 as a key for encrypting the next plaintext data. use. At this time, the ciphertext that is exclusive-ORed with the current key is the intermediate data of the block cipher core unit 4 described above, and the ciphertext in which the basic unit 1 is repeated N / 2 times is used.

[0005] As described above, the CCBC method uses a ciphertext corresponding to the current plaintext data as a part of the next plaintext encryption key, so that the block cipher processing for one plaintext is completed. You need to keep the data until, and usually have memory.

When this conventional configuration is implemented by hardware, a memory for holding data has a larger area than the hardware of the encryption circuit shown in FIG.

[0007]

However, in the conventional configuration, when this configuration is hardened, the memory for holding data tends to be larger than the hardware of the encryption circuit.

In particular, for plaintext with a high data transfer rate, more memory for storing plaintext is required due to the data processing capability of the encryption circuit.

For example, considering the processing of an MPEG2 TS packet, the data valid period is Max 100 Mbps, and the encryption circuit of the conventional configuration is connected to the system clock 25 MHz.
z, 16Mbps if the block cipher core is 100 cycles
It is. In this case, the memory for storing the plaintext is MPEG2
A capacity for six TS packets is required. The capacity of the memory at this time is determined by the ratio between the hardware processing capacity of encryption and the transfer rate of the input data, and the higher the transfer rate of the input data, the more memory capacity is required.

The present invention has been made to solve the above-mentioned conventional problems, and has as its object to improve the processing capability of an encryption circuit.

[0011]

In order to achieve this object, in an encryption circuit according to the present invention, two sets of block cipher cores are arranged in parallel, and each ciphertext is passed to an adjacent set. And a memory control unit (data latch) for controlling input data, and a selector for controlling ciphertext.

With this configuration, the processing capability of the encryption circuit can be improved to about twice that of the related art.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION
Two sets of a block cipher core unit, a key data control unit, and a memory control unit (data latch) for reading an input plaintext from a memory are arranged in parallel, and the output circuits of the respective ciphertexts are connected in a crossing manner. A final ciphertext is obtained by switching the processed data by a selector.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an encryption circuit according to an embodiment of the present invention. In FIG. 1, 1
Reference numeral 0 denotes a memory for storing plaintext data, and reference numeral 4 denotes a block cipher core unit having the same operation as that shown in FIG. 3 showing the above-mentioned conventional example, and a combination of N basic units 1 and key data control for key scheduling. And 5. Reference numeral 14 denotes a block cipher core unit having the same function as the block cipher core unit 4. Similarly, a combination of N basic units 1 and a key data control unit 1 for performing a key schedule.
And 5. This is a circuit having the same operation as the key data control unit 5. Reference numeral 16 denotes a circuit having the same function as the exclusive OR circuit 6. Reference numeral 17 denotes a circuit having the same function as the CCBC function unit 7. Reference numeral 8 denotes a memory control unit (data latch) for reading data to be subjected to block cipher from a memory 10 for storing plain text. 9
Is a memory control unit (data latch) for reading out data to be subjected to block ciphering from the memory 10 for storing plain text, similarly to the memory control unit 8. The timing at which data is sent to the unit 4 is delayed by N / 2 repetitions of the basic unit 1. Reference numeral 20 denotes a selector for converting ciphertext processed in parallel by the block cipher core unit 4 and the block cipher core unit 14 as continuous data.

Next, the operation of the encryption circuit according to the present embodiment will be described. First, from the memory 10 to the memory control unit 8
And the memory control unit 9 reads out two plaintext data. The memory control unit 8 sends the first plaintext to the block cipher core unit 4. The memory control unit 9 holds the second plaintext until the processing of the block cipher core unit 4 repeats the basic unit 1 N / 2 times. After the processing of the block cipher core unit 4 repeats the basic unit 1 N / 2 times, the memory control unit 9 passes the data to the block cipher core unit 14. At the same time, the exclusive-OR circuit 16 performs an OR operation on the ciphertext of the block cipher core unit 4 with the current key data, and sends the result to the key data control unit 15 for generating a key for the second plaintext. Can be Then, the second ciphertext output from the memory control unit 9 is encrypted by the block cipher core unit 14.
After the process of the block cipher core unit 14 repeats the basic unit 1 N / 2 times, the memory control unit 8 passes the data to the block cipher core unit 4. At the same time, the exclusive-OR circuit 6 performs an OR operation on the ciphertext of the block cipher core unit 14 with the current key data, and sends the result to the key data control unit 5 for generating a third plaintext key. Can be Then, the third ciphertext output from the memory control unit 8 is encrypted by the block cipher core unit 4.

The subsequent processing is similarly performed for the block cipher core unit 4.
And the process of the block cipher core unit 14 are alternately repeated to encrypt the plaintext. The final cipher text is generated by extracting the results of the block cipher core unit 4 and the block cipher core unit 14 in order by the selector 20.

FIG. 2 shows a timing chart of an encryption process of an MPEG2 TS packet as an example.

[0019]

As described above, according to the present invention, the processing capacity can be approximately doubled and the memory capacity can be reduced by adding a cross-flow CCBC system to the block cipher circuit. This implements an encryption circuit. Taking the above-mentioned MPEGTS packet as an example, the encryption processing capacity can be increased to 31 Mbps, and the capacity of the memory for storing plaintext can be reduced to three packets.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an encryption circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of block encryption according to the embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a conventional block cipher and CCBC circuit;

[Explanation of symbols]

 1 Basic unit of block encryption circuit 2, 6, 16 Exclusive OR circuit 3 Block encryption function unit 4, 14 Block encryption core unit 5, 15 Key data control unit 7, 17 CCBC function unit 8, 9 Memory control unit (data Latch) 10 memory 20 selector

Claims (1)

[Claims] 1. A block cipher core unit, a key data control unit, and a memory control unit for reading input plaintext from a memory are arranged in two sets in parallel, and an output circuit for each ciphertext is connected in a crossing manner. An encryption circuit characterized in that a final ciphertext is obtained by switching data processed in parallel by a selector.