JP2000058820A - Power semiconductor element and power module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide electrode structure where capability and reliability in an element can be improved in a power semiconductor element. SOLUTION: In a power semiconductor element, first electrodes 12 are installed on the surface of a semiconductor layer, interlayer insulating layers 11 are formed on the surfaces of the first electrodes 12, and a second electrode 10 is installed just above the first electrodes 11 on the surface of the interlayer insulating layers 11. Since the area utilization factor of the element is improved and the damage to bonding is relieved, the capability and reliability of the power semiconductor element can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device and a power module used for a power converter such as an inverter.

[0002]

2. Description of the Related Art IGBT which is a typical power semiconductor device
With the use of techniques such as lifetime control and miniaturization, reduction of switching time and reduction of loss due to low saturation voltage are steadily progressing. However, as a result of the low saturation voltage, IG
The saturation current of the BT also increases, shorting the load, shorting the upper and lower arms,
For example, device destruction when a saturation current flows through the IGBT has become a problem. This is a reduction in short-circuit withstand capability. In order to solve this problem, an intelligent power module in which various protection circuits such as an IGBT and a gate drive circuit and an overcurrent protection circuit are sealed in one package
(IPM) is becoming popular in IGBT modules.

In order to realize the IPM, it is necessary to monitor a current flowing in the IGBT. For this,
IG equipped with a terminal for detecting a current of one thousandth of the main current
BT (IGBT with sense terminal) is required. FIG. 4 shows an equivalent circuit of an IGBT with a sense terminal. Common to the gate terminal 43 and the collector terminal 42, the sense IGBT 40 and the main IGBT
41 is a structure connected in parallel. Since the current of the sense IGBT 40 is several thousandths of that of the main IGBT 41, the area of the so-called active region that contributes to energization is several thousandths of that of the main IGBT 41. The emitter terminal of the sense IGBT 40 becomes the sense terminal 44 and is connected to a current detection circuit (usually a resistor).

FIG. 2 is a schematic plan view of an IGBT with a sense terminal. 5 schematically shows an aluminum electrode pattern. A gate electrode Al wiring 24 is formed on the entire chip from a wire bonding region (gate pad) 21 of the gate electrode, and most other regions are the emitter electrode 20 of the main IGBT 41. The electrode pad 22 having substantially the same area as the gate pad 21 is a wire bonding region (sense pad) of the sense terminal (the emitter terminal 44 of the sense IGBT 40). The size of the gate pad 21 and the sense pad 22
It is determined by the area required for bonding the Al wire. For example, when bonding an Al wire having a meridian of 0.3 mm, the size of the pad is approximately 1 mm ² . An area 23 surrounded by a rectangle indicates an active area of the sense IGBT 40. As described above, since this active region is one-thousandth of the main IGBT 41 (almost the entire chip), it is much smaller than the area required for bonding of about 1 mm ² .

[0005] In addition, ultrasonic bonding of an Al wire is generally used because the electrical connection, which is a key in mounting the IGBT, is inexpensive. This is Al of IGBT
An ultrasonic welding is performed while pressing an Al wire on the electrode with a pressure of several hundred grams.

[0006]

The above-mentioned conventional IGBT with a sense terminal has the following problems with regard to low loss. As described above, the area of the active region 23 below the sense pad 22 is much smaller than the size of the sense pad 22. FIG. 3 is a schematic diagram showing an example of a cross-sectional structure of this portion.
Shown in Region 19 is active region 23 of sense IGBT 40
Which is a so-called normal IGBT structure. n ⁺ - emitter 13, p-base 14, p ⁺ - region 15, the gate electrode (poly-Si) 102, n - - the base 16, p ⁺ -
It is composed of a collector 17. The Al electrode 33 is the sense pad 22 which is the emitter electrode of the sense IGBT. A region 32 other than the sense IGBT region 19 is constituted by an element isolation oxide film 31 and a deep p ⁺ -layer (p-well layer) 30. The p-well layer 30 is short-circuited to the emitter terminal 45 of the main IGBT 41. In this area, the primary IGBT
There should be 41 active areas, but the emitter pads cannot be formed because of the presence of the sense pads 22 on this area. Therefore, the presence of a large number of IGBT cells with the emitter electrode floating causes a problem such as latch-up, and all regions other than the sense IGBT region 19 under the sense pad 22 are regions 32. Therefore, IGB under the sense pad
T is hardly formed. That is, the sense pad 22
Most of the area under is a dead space that does not contribute to energization. This leads to an increase in the saturation voltage of the IGBT chip, which is a serious drawback for power semiconductor devices where low saturation voltage is an important indicator of high performance.

Further, for the above-mentioned reason, it is practically impossible to provide a plurality of sense IGBT regions 23 in a chip, but only at one place. Therefore, the main IGBT41 and the sense IGBT
For example, the difference between the gate resistances and the like of 40 is remarkable, and the operations of the two become non-uniform, causing a problem that the current ratio changes transiently.

Further, other functions such as temperature detection are provided by I
When it is provided in a GBT chip and connected to a control circuit outside the chip, the number of Al electrode pads becomes large, and the area of the main IGBT 41 is significantly reduced.

Next, as a problem in mounting the IGBT,
Degradation of element breakdown voltage due to Al wire bonding can be cited. The cause is as follows. A small amount of Si exists in the Al electrode of the IGBT. This Si is contained in the electrode film.
It may locally precipitate (Si nodule) and form a wedge shape. Then, the deposited Si is violently shaken during the ultrasonic bonding, breaks through the passivation film of the IGBT, and penetrates into the diffusion layer of the IGBT. When this phenomenon occurs, for example, a short circuit occurs between the emitter and the collector, and the IGBT malfunctions. This phenomenon is more likely to occur when the diffusion layer is shallower for higher performance of the IGBT, and the yield reduction due to Al wire bonding becomes remarkable.

The present invention has been made in consideration of the above problems, and has as its object to provide an electrode structure in a power semiconductor device that can improve the performance and reliability of the device.

[0011]

The main components of the power semiconductor device according to the present invention are a first electrode provided on the surface of a semiconductor layer, an interlayer insulating layer located on the surface of the first electrode, and an interlayer insulating layer. A second electrode located directly above the first electrode on the surface of the insulating layer; With such a configuration, the degree of freedom in the arrangement of the element region and the electrodes in the power semiconductor element is improved. More specific configurations include the following configurations.

In the above main structure, the semiconductor layer has a first element region and a second element region, the first electrode is in contact with the first element region, and the second electrode is a first electrode region. And is located on the surface of the interlayer insulating film immediately above the second element region. Then, the second electrode becomes a pad for connecting an external lead. According to this configuration,
A second element region can be provided directly below a pad connected to the first element region. Therefore, it is possible to increase the use area of the second element region. This configuration is suitable when the first element region is a sense IGBT region and the second element region is a main IGBT region.

In the above main structure, the second electrode is a bonding pad. According to this structure, the damage to the semiconductor layer due to bonding is reduced by the interlayer insulating film.

In the above main structure, the semiconductor layer has an element region, and further has another element located on the surface of the semiconductor layer. A second electrode is connected to the element and the second electrode is connected to the element region. It is located on the surface of the interlayer insulating film immediately above. This configuration is suitable when the other element is a diode formed on an oxide film. According to this configuration, when another element is formed on the semiconductor layer, the degree of freedom in the arrangement of the element region and the electrode can be increased.

In the above main configuration, the semiconductor layer has a switching element region, the first electrode is a control electrode wiring in the switching element region, the control electrode wiring is covered with an interlayer insulating film, and the second electrode is a switching electrode. Connected to the element region. This configuration is based on the switching element region IGBT
This is a region, and is suitable when the control electrode wiring is a gate wiring. According to this configuration, the electrode pattern connected to the switching element region can be widened even if there is a control electrode wiring. Therefore, a plate-shaped external lead electrode having low electric resistance, for example, a bus bar electrode wiring can be connected to the electrode pattern connected to the switching element region. A power module containing a power semiconductor element to which such a plate-shaped external lead electrode is connected, for example, I
In the GBT module, wiring resistance and wiring inductance are reduced.

The present invention relates to an IGBT, a power MOSFET,
It can be applied to various power devices such as T and bipolar transistors.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) The basic configuration will be described with reference to FIGS. FIG. 1 shows an I-type terminal with a sense terminal according to the present invention.
FIG. 3 schematically shows a cross-sectional structure of a sense IGBT region 19 of the GBT and a main IGBT region 18 near the periphery thereof. The structure of the gate and the diffusion layer of the IGBT is a conventional
Same as T. That is, the p ⁺ − collector layer 17, n
^- - the base layer 16, a gate oxide film 104, the gate electrode po
The ly-Si layer 102 is formed, and the p-base 14, n ⁺ −
Emitter 13, p ⁺ for obtaining ohmic contact
A layer 15 is formed; After the gate electrode passivation oxide film 101 is formed, the emitter electrode 12 (Al
Film) and the p-base 14 and the n ⁺ -emitter 13 are connected. The Al film 12 is thinner than a conventional IGBT emitter electrode film and has a thickness of 1 μm or less. Further, the Al film 12
An interlayer insulating film (oxide film) 11 deposited by plasma CVD or the like is formed thereon to a thickness of about 0.5 μm, and a through hole 103 is formed. The through hole 103 connects the second Al layer 10 and the first Al layer 12. In this embodiment, the thickness of the second Al layer 10 is 5 μm, which is almost the same as that of a conventional IGBT emitter electrode.

The unique feature of this embodiment is that the sense IGBT
The main IGBT region 18 is formed very close to the region 19. That is, there is no dead space of the main IGBT. For comparison, IGB with normal sense terminal
FIG. 3 shows a schematic sectional view of the vicinity of the sense IGBT region 19 of T (corresponding to FIG. 1). In the conventional example, the vicinity of the sense IGBT region 19 is close to the deep p ⁺ − layer (p-well
Layer 30 is formed (region 32) and the main IGBT is not formed. The reason for this has already been described, and will be described in detail with reference to FIG. FIG. 19 is a schematic sectional view of the sense pad 22 region of FIG. For simplicity, the region of the gate wiring 24 is omitted, the emitter contact region is shown only by the p-base 14, and the n ⁺ -emitter 13 and the p ⁺ -layer 15 are omitted. Conventionally, the IGBT emitter electrode has a thickness of 5
It is formed of only one thick Al layer 33 of not less than μm. Therefore, the emitter electrode 20 cannot be formed under the sense pad 22 which requires a large area due to Al wire bonding, so that the p-well layer 30 basically becomes a dead space.

On the other hand, FIG. 18 shows a diagram of this embodiment corresponding to FIG. In the case of this embodiment, since the emitter electrode is formed of the first and second Al layers, the interlayer oxide film 11 is disposed below the sense pad 180 formed of the second Al layer.
A first Al layer can be provided. Therefore, the main IG
The BT can be arranged very close to the sense IGBT, the emitter electrode of the main IGBT can be composed of the first Al layer 12, and can be connected to the emitter electrode (second Al layer) 181 around the sense pad 180.

As described above, the first and second Al layers 10,
By arranging the main IGBT below the interlayer oxide film 11 using the IGBT 12, the dead space below the sense pad can be eliminated.

In an IGBT which is a power semiconductor for power conversion, the emitter current is caused by Al formed on the entire upper surface of the device.
Electric current is supplied from the electrode to the upper side of the element. Therefore, the loss due to the resistance of the Al electrode can be ignored. However, in the case of the present embodiment, the current of the main IGBT under the interlayer oxide film 11 cannot be applied to the upper side of the device unlike the other regions. There must be. Therefore, the thickness of the Al electrode 12 must be determined in consideration of the resistance of this portion. In this embodiment, the thickness of the Al electrode 12 is 1 μm.

(Embodiment 2) According to the present invention, the dead space under the sense pad 22 which has conventionally been a problem can be basically eliminated. Therefore, many sense IGBTs can be formed in one chip (FIG. 6). In the conventional structure, since there is a dead space, it is impossible at all to form a large number because the area of the main IGBT region is significantly reduced. This is because the emitter-collector saturation voltage (VCE (sat)) is greatly increased, and the loss is significantly increased. For example, rated voltage / current, 6
In the case of the IGBT of 00V / 50A, the ratio of the sense pad in the emitter electrode was about 6% (in the case of one pad). Therefore, if the sense IGBT region is made up of four pads, the ratio becomes about 25%, which is completely unacceptable. The embodiment shown in FIG. 6 shows a case where the emitter electrode 20 has four pads, and a sense IGBT is arranged corresponding to each region of the emitter electrode 20 and four sense pads 22 are arranged. . With this structure, since a sense region can be provided in each of the four independent IGBT regions, more accurate current detection can be performed.

In this embodiment, the gate pad 21 is arranged at the center of the chip. However, another arrangement such as the end of the chip may be used.

(Embodiment 3) According to the present invention, in addition to eliminating the dead space under the sense pad,
There is an extremely important effect that the reliability of the T module can be greatly improved. An embodiment in which this effect is realized will be described with reference to FIG.

FIG. 2 is a schematic cross-sectional view of the Al wire bonding region 1001. The feature is that an interlayer oxide film 11 necessary for forming an IGBT chip electrode into an Al2 layer is arranged in an Al wire bonding region 1001.
Since the conventional structure has one Al electrode, the Si nodule 1003 generated in the Al electrode directly damages the Si substrate when the Al wire is ultrasonically welded, and in some cases, destroys the substrate passivation layer, Penetrates inside the substrate. However, in the present embodiment, even if the Si nodule 1003 is generated in the Al wire bonding portion, the hard oxide film 11 exists under the Si nodule 1003, and therefore hardly penetrates into the Si substrate. Since the hard oxide film 11 is dispersed, a highly reliable wire bonding portion can be realized without concentration. In this example, the thickness of the interlayer oxide film 11 is 0.5 μm. This thickness is designed to have a rigidity that can withstand the damage of the Si nodule 1003. Therefore, in this example, the oxide film is deposited by plasma CVD or the like, but the thickness is appropriately determined according to the type of the insulating film such as a silicon nitride film.

FIG. 11 is a schematic plan view of a conventional structure IGBT chip when the emitter pad 20 has a six-pad structure. The diameter of the Al wire 1002 is 0.3 mm. The thicker the wire, the larger the current capacity can be and the number of wires can be reduced. Therefore, it is desirable to make the wire thicker for mounting. However, making the wire thicker requires increasing the power at the time of ultrasonic welding, and this causes the above problem to become apparent. In view of this, the thickness is made comparatively thin at 0.3 mm and the number of pads is increased to three pads. On the other hand, FIG.
Shown in In this case, as described above, it is not necessary to consider the damage of wire bonding, so that the ultrasonic power can be increased. Therefore, the diameter of the Al wire 1002 is 0.5 mm, which is larger than that of the conventional wire, and the number of wires is reduced to one for each pad. At this time, the interlayer oxide film 11 is of course disposed below the wire bonding 1001.

As described above, according to this embodiment, since the reliability can be maintained and the number of Al wires can be reduced,
There is also an effect that the manufacturing cost of the IGBT module can be reduced. (Embodiment 4) In some cases, not only the current detection function but also a diode for detecting the temperature of the chip is built in the IGBT chip constituting the IPM. IGB with built-in diode
FIG. 7 shows an equivalent circuit of the T chip, and FIG.
FIG. 8 is a schematic plan view of the chip. The principle of operation is to apply a constant current between the anode and the cathode of the diode 71, and to detect the temperature by the change in the on-voltage of the diode 71.

In this embodiment, the diode 71 is made of poly.
-Si layer. p-type poly-Si layer 91, n-type
forming a poly-Si layer 92 on the isolation oxide film 31;
The wiring is performed by the first Al layer 12 and the second Al layer 10. For the same reason as the sense IGBT region described above, in the case of a single Al layer,
A dead space is formed under the anode 80 and cathode 81 pads. In this case, a region below the three pads including the sense pad 22 becomes a dead space. This is a problem for IGBTs characterized by low loss. Therefore, the second Al
An interlayer oxide film 11 is arranged below the anode 80 and cathode 81 electrodes formed of the layer 10 to form a main IGBT.

As described above, the present embodiment has shown the case where a diode is built in. Considering future intelligent IGBTs, various peripheral elements and circuits may be incorporated in addition to diodes. Also in this case, it is extremely effective to arrange the interlayer oxide film below the built-in element and the electrode pad (second Al layer) of the circuit and arrange the main IGBT thereunder.

(Embodiment 5) As described above,
The emitter electrode of the IGBT is divided into a plurality in one chip. For example, in the case of a device with a rated voltage of 600 V, there are four pads (50 A) and twelve pads (100 A). The reason for this is that it is necessary to wire the Al wiring of the gate in the chip. FIG. 5 shows a schematic diagram of a cross-sectional structure near the Al wiring of a conventional IGBT chip. Since only the Al layer 33 can be used, the Al wiring 24 and the emitter electrode 20 need to be separated, and the emitter electrode is inevitably separated.

If the Al wiring 24 does not exist, the gate wiring is formed only of poly-Si which is a gate electrode material, resulting in an extremely high resistance. In this case, with an IGBT chip having a side length of 1 cm or more at the maximum, uniform operation of each IGBT cell in the chip can no longer be expected.

Therefore, the present invention is also applied to the gate Al wiring portion. FIG. 13 shows a schematic diagram of a cross-sectional structure. In the gate Al wiring section 130, the Al wiring is wired by the first Al layer 12, the wiring is insulated by the interlayer oxide film 11, and the emitter electrode is formed on the entire surface of the chip by the second Al layer 10. Of course, in the case of a gate pad and an IGBT with a sense terminal, the sense pad needs to be separated.

As described above, in the case of this embodiment, regardless of the current rating, the emitter electrode can be formed by one pad without being separated in the chip. This increases the degree of freedom of the wire bonding, the number of wires, the number of positions, and the like, thereby increasing the degree of freedom in the mounting form, and contributing to downsizing of the IGBT module.

(Embodiment 6) According to Embodiment 5, one pad can be formed without separating the emitter electrode. By utilizing this, various wiring connection methods to the IGBT chip can be considered instead of the conventional Al wire bonding method.

Conventionally, it has been performed in a diode or the like.
For the case where the busbar is directly bonded to the chip electrode,
This is shown in FIGS. Fig. 14 shows the tip and busbar 14.
FIG. 15 is a schematic plan view showing only 0, and FIG. 15 is a schematic cross-sectional structure up to a module base 151, which is an example of a module.

In this embodiment, the rated voltage / current, 600 V /
Shown for 50A case, chip size is 6mm
It is. The gate wiring is performed by ultrasonic bonding of the Al wire 111 (same as the conventional), and the emitter wiring is 5 mm in width.
Al ribbon 140 is also ultrasonically bonded. With this emitter wiring, low resistance and low inductance, which are difficult to realize by conventional Al wire bonding, can be realized. As described above, a bus bar as wide as the chip size can be realized by forming the gate wiring and the emitter electrode with different metal layers. Further, in the present embodiment, the bonding of the bus bar 140 is realized by ultrasonic welding of the Al ribbon, but other methods such as solder bonding of a Ni-plated copper plate are also conceivable. In this case, it is difficult to form the emitter electrode 20 with an Al layer, and the emitter electrode 20 must have a Ni / Ti / Ni / Au laminated structure or the like. The first Al layer remains as it is, and the second Al layer
It is conceivable that the layer is a metallized layer for this soldering.

(Embodiment 7) FIG. 17 shows an embodiment in which the bus bar is connected to the IGBT chip shown in Embodiment 6 and the equivalent circuit is a three-phase inverter module shown in FIG. . The form of the module is
This figure shows a case where a so-called insert case is used in which N, P, U, V, and W power terminals and control terminals (not shown) are insert-molded in a case. That is, the case 170 includes the P wiring 173 and the N wiring 17.
4. The U, V, and W wirings 175, 176, and 177 are insert-molded.

As in the conventional IGBT module, a flywheeling diode (FWD) 172 and an IGBT 152 are soldered to the ceramic substrate 150. One ceramic substrate 150 corresponds to one arm 160 in FIG. This substrate is solder-bonded to a copper base 151 serving as a heat sink, and a heat radiation system from the Si chip to the heat sink is completed. As described above, the case 170 is bonded to the copper base 151 on which the element and the ceramic substrate are mounted by using a silicone-based thermosetting adhesive. Gate wiring and other control system wiring
Control terminal 1 by Al wire bonding as before
71, which is characterized by the following power connection method.

In the case of the present embodiment, the electrodes of the Si chip are metallized for solder bonding as described above, and are 0.8 mm thick insert-molded Ni-plated copper plates 174, 17
3,175 are solder-bonded to one ceramic substrate 150 and a Si chip mounted on the substrate. Specifically, the P wiring 173 is formed of a copper foil 17 on the ceramic substrate 150.
8, the N wiring 174 is connected to the IGBT 152, and the W wiring 175 is connected to the IGBT 152.
Is copper foil 179, FWD172, IGBT on ceramic substrate 150
153 is soldered. Since the ceramic substrate and the insert case 170 are aligned with the copper base 151, these solders do not need to be aligned and can be easily bonded.

As described above, since the copper busbar wiring is used instead of the Al wiring for the power system wiring, an IGBT module with low resistance and low inductance can be realized.

[0042]

According to the present invention, the area utilization of the device can be improved and the damage of bonding can be reduced, so that the performance and reliability of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing one embodiment of the present invention.

FIG. 2 is a schematic plan view of a conventional IGBT with a sense terminal.

FIG. 3 is a schematic sectional view of a conventional IGBT with a sense terminal.

FIG. 4 is an equivalent circuit diagram of an IGBT with a sense terminal.

FIG. 5 is a schematic sectional view of a gate electrode wiring region of a conventional IGBT.

FIG. 6 shows an embodiment of an IGBT with a sense terminal according to the present invention.

FIG. 7 is an equivalent circuit of an IGBT with a temperature detection terminal.

FIG. 8 is a schematic plan view of FIG. 7;

FIG. 9 is a schematic cross-sectional view of FIG. 7 according to the present embodiment.

FIG. 10 shows an embodiment of the low damage electrode of the present invention.

FIG. 11 is a schematic diagram of a conventional IGBT wire bonding.

FIG. 12 is a schematic diagram of wire bonding of the IGBT of the present invention.

FIG. 13 is a schematic sectional view of a gate electrode wiring portion of the IGBT of the present invention.

FIG. 14 shows an embodiment of the electrode wiring of the IGBT of the present invention.

FIG. 15 is a schematic sectional view of FIG. 14;

FIG. 16 is an equivalent circuit of a three-phase inverter module.

FIG. 17 shows an embodiment of a three-phase inverter module equipped with the IGBT chip of the present invention.

FIG. 18 is an enlarged view of FIG. 1;

FIG. 19 is an enlarged view of FIG. 3;

[Explanation of symbols]

10: second Al layer, 11: interlayer insulating film, 12: first Al
Layers, 13... N ⁺ -emitter layers, 14.
5 ... p ⁺ -layer, 16 ... n ^-- base, 17 ... p ⁺ -collector layer, 18 ... main IGBT region, 19 ... sense IGBT
Region, 101: passivation film, 102: gate electrode (poly-Si), 103: through hole, 104: gate oxide film, 20: main IGBT emitter electrode, 21: gate electrode, 22: sense IGBT emitter electrode (sense electrode) , 23 ... Sense IGBT active area, 24,
130 ... gate electrode Al wiring, 30 ... deep p ⁺ layer (p−
well layer), 31 element isolation oxide film, 32 p-well layer region, 33 Al layer, 40 sense IGBT, 41 main I
GBT, 42: Collector terminal, 43: Gate terminal, 44
... Sensor IGBT emitter terminal (sense terminal), 45 ...
Main IGBT emitter terminal, 70: IGBT with built-in temperature detection diode, 71: Temperature detection diode, 72: Temperature detection terminal, 73: Temperature detection terminal (ground), 80: Temperature detection terminal electrode, 81: Temperature detection terminal electrode (ground) ,
90: temperature detection diode region, 91: temperature detection diode (p layer), 92: temperature detection diode (n layer), 11
1,1002: Al wire, 140: busbar wiring, 1
50: ceramic substrate, 151: copper base, 152, 1
53 ... IGBT chip, 160 ... 1 arm, 170 ... Module case, 171 ... Control terminal pad, 172 ... Fly wheeling diode (FED), 173 ... P wiring, 174 ... N wiring, 175 ... W wiring, 176 ... V Wiring, 177: U wiring, 178, 179: copper foil on ceramic substrate, 1001: Al wire bonding area, 10
03 ... Si nodule.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Koichi Inoue 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory, Ltd. No. 1-1 F-term in Hitachi Research Laboratory, Hitachi, Ltd. F-term (reference) 5F033 BA02 BA12 CA01 DA05 DA35 EA03 EA25 5F044 EE06 EE11

Claims (8)

[Claims] A first electrode provided on a surface of the semiconductor layer; an interlayer insulating layer located on a surface of the first electrode;
A power semiconductor device, comprising: a second electrode located immediately above the first electrode on a surface of the interlayer insulating layer. 2. The semiconductor device according to claim 1, wherein the semiconductor layer has a first element region and a second element region, wherein the first electrode is in contact with the first element region, and the second electrode is , Electrically connected to the first electrode and located on the surface of the interlayer insulating film immediately above the second element region;
A power semiconductor element, wherein the electrode is a pad for connecting an external lead. 3. The semiconductor device according to claim 2, wherein said first device region is a sense IGBT region, and said second device region is
A power semiconductor device comprising a GBT region. 4. The power semiconductor device according to claim 1, wherein said second electrode is a bonding pad. 5. The semiconductor device according to claim 1, wherein the semiconductor layer has an element region, and further has a diode formed on an oxide film located on a surface of the semiconductor layer, wherein the first electrode is provided in the element region. And the second electrode is connected to the diode, and is located on the surface of the interlayer insulating film immediately above the element region. 6. The semiconductor device according to claim 1, wherein the semiconductor layer has a switching element region, the first electrode is a control electrode wiring in the switching element region, and the control electrode wiring is covered with the interlayer insulating film. A power semiconductor element, wherein the second electrode is connected to the switching element region. 7. A power semiconductor device according to claim 6, wherein said switching element region is an IGBT region, and said control electrode wiring is a gate wiring. 8. A power module in which a semiconductor device is housed in a case, wherein the semiconductor device is a power module.
4. The power module according to claim 1, wherein a plate-shaped external lead electrode is connected to the second electrode.