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GB8804470D0 - Improvements in/relating to multi-stage binary adders &/substractors - Google Patents

Improvements in/relating to multi-stage binary adders &/substractors

Info

Publication number
GB8804470D0
GB8804470D0 GB888804470A GB8804470A GB8804470D0 GB 8804470 D0 GB8804470 D0 GB 8804470D0 GB 888804470 A GB888804470 A GB 888804470A GB 8804470 A GB8804470 A GB 8804470A GB 8804470 D0 GB8804470 D0 GB 8804470D0
Authority
GB
United Kingdom
Prior art keywords
substractors
relating
stage binary
binary adders
adders
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB888804470A
Other versions
GB2215496A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Priority to GB8804470A priority Critical patent/GB2215496A/en
Publication of GB8804470D0 publication Critical patent/GB8804470D0/en
Priority to JP1045001A priority patent/JPH01310434A/en
Publication of GB2215496A publication Critical patent/GB2215496A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Logic Circuits (AREA)
GB8804470A 1988-02-25 1988-02-25 Multi-stage parallel binary adders and/or subtractors Withdrawn GB2215496A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB8804470A GB2215496A (en) 1988-02-25 1988-02-25 Multi-stage parallel binary adders and/or subtractors
JP1045001A JPH01310434A (en) 1988-02-25 1989-02-23 Multi-stage parallel binary adder/subtractor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8804470A GB2215496A (en) 1988-02-25 1988-02-25 Multi-stage parallel binary adders and/or subtractors

Publications (2)

Publication Number Publication Date
GB8804470D0 true GB8804470D0 (en) 1988-03-23
GB2215496A GB2215496A (en) 1989-09-20

Family

ID=10632394

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8804470A Withdrawn GB2215496A (en) 1988-02-25 1988-02-25 Multi-stage parallel binary adders and/or subtractors

Country Status (2)

Country Link
JP (1) JPH01310434A (en)
GB (1) GB2215496A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146424A (en) * 1991-11-21 1992-09-08 Unisys Corporation Digital adder having a high-speed low-capacitance carry bypass signal path
DE69428466T2 (en) * 1993-11-23 2002-05-23 Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto Parallel data processing in a single processor
US6088800A (en) 1998-02-27 2000-07-11 Mosaid Technologies, Incorporated Encryption processor with shared memory interconnect
DE10215784A1 (en) * 2002-04-10 2003-10-30 Infineon Technologies Ag Calculator and subtracting method
JP2010086256A (en) * 2008-09-30 2010-04-15 Mitsubishi Electric Corp Parallel processing type processor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4707800A (en) * 1985-03-04 1987-11-17 Raytheon Company Adder/substractor for variable length numbers

Also Published As

Publication number Publication date
GB2215496A (en) 1989-09-20
JPH01310434A (en) 1989-12-14

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)