GB2459302A - A method of dicing wafers to give high die strength - Google Patents
A method of dicing wafers to give high die strength Download PDFInfo
- Publication number
- GB2459302A GB2459302A GB0807101A GB0807101A GB2459302A GB 2459302 A GB2459302 A GB 2459302A GB 0807101 A GB0807101 A GB 0807101A GB 0807101 A GB0807101 A GB 0807101A GB 2459302 A GB2459302 A GB 2459302A
- Authority
- GB
- United Kingdom
- Prior art keywords
- wafer
- dicing
- etching
- partially
- back face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 235000012431 wafers Nutrition 0.000 title claims description 141
- 238000000034 method Methods 0.000 title claims description 33
- 238000005530 etching Methods 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 230000002269 spontaneous effect Effects 0.000 claims abstract description 16
- 229910052736 halogen Inorganic materials 0.000 claims abstract description 8
- 150000002367 halogens Chemical class 0.000 claims abstract description 8
- 230000007547 defect Effects 0.000 claims abstract description 7
- 150000001875 compounds Chemical class 0.000 claims abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 claims description 10
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 8
- IGELFKKMDLGCJO-UHFFFAOYSA-N xenon difluoride Chemical compound F[Xe]F IGELFKKMDLGCJO-UHFFFAOYSA-N 0.000 claims description 6
- 229910000042 hydrogen bromide Inorganic materials 0.000 claims description 5
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052801 chlorine Inorganic materials 0.000 claims description 4
- 239000000460 chlorine Substances 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- -1 halide compound Chemical class 0.000 claims description 4
- 239000000463 material Substances 0.000 abstract description 5
- 150000002366 halogen compounds Chemical class 0.000 abstract description 3
- 150000004820 halides Chemical class 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000010257 thawing Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 239000011343 solid material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/67346—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders characterized by being specially adapted for supporting a single substrate or by comprising a stack of such individual supports
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Laser Beam Processing (AREA)
Abstract
A semiconductor wafer, having a first face including active devices and a back face opposed to the first face, is mounted on a wafer carrier 11 with the back face accessible. The wafer is at least partially diced to form an at least partially diced wafer. A back face of the at least partially diced wafer is etched with a spontaneous etchant such as XeF 2 while the wafer is still on the wafer carrier, at least to reduce defects generated in at least partially dicing the wafer, to produce an etched, at least partially diced wafer 30. Where the wafer is only partially diced in the dicing step, dies are singulated from the wafer by etching remaining semiconductor material in the die lanes during the etching step. Spontaneous etchants which may be used include noble halogens, halides, halogen compounds and interhalogen compounds.
Description
A method of dicing wafers to give high die strength This invention relates to a method of dicing semiconductor wafers to give high die strength.
Spontaneous etching of silicon, with a high etch selectivity in respect of a majority of capping layers used in the semiconductor industry, is well known.
Stress relief after dicing of a semiconductor wafer is known to improve die strength providing greater durability of the die. US 6,498,074 discloses a method of partially dicing from an active face and then back-thinning semiconductor wafers from an opposed back face using a dry etch to obtain semiconductor chips with rounded bottom edges and corners. In this process, which is a reverse process of a known backgrind and dice sequence for producing thinned die, a wafer is partially diced to form grooves on the active face of the wafer. The wafer is remounted, after partial dicing, in a non-contact wafer holder with the active face uppermost and is then dry etched with an atmospheric plasma etch to remove silicon from a back of the wafer until the grooves are exposed. The dry etching also removes stress built up on the backside and sidewall of the dies by removal of silicon from these areas and rounds edges and corners of the dies to rcmove stress points. However, the method involves remounting the wafer between grooving and etching and uses plasma etching which is relatively expensive compared with other forms of etching.
It is an object of the present invention at least to ameliorate the aforesaid
shortcomings in the prior art.
According to a first aspect of the present invention there is provided a method of dicing a semiconductor wafer having a first face including active devices and a back face opposed to the first face, the method comprising the steps of: mounting the wafer on wafer carrier means with the back face accessible; at least partially dicing the wafer on the wafer carrier means to provide an at least partially diced wafer; and etching the back face of the at least partially diced wafer on the wafer carrier means with a spontaneous etchant at least to reduce defects generated in the at least partially dicing of the semiconductor wafer, to produce an etched diced wafer.
Conveniently, the step of mounting the wafer on wafer carrier means comprises mounting the wafer on one of tape means, mechanical clamping means, electrical clamping means and vacuum clamping means.
Advantageously, the step of etching the at least partially diced wafer comprises etching with a gaseous or liquid etchant.
Preferably, the step of etching with a gaseous or liquid etchant comprises etching with a halogen or a halide compound.
Conveniently, the step of etching comprises etching with one of fluorine, chlorine, hydrochloric acid and hydrogen bromide.
Advantageously, the step of etching comprises etching with a noble halogen or an interhalogen compound Preferably, the step of etching comprises etching with xenon fluoride.
Advantageously, the etching step is at least partially carried out during the dicing step Advantageously, the etching step is at least partially carried out after the dicing step.
Conveniently, the etching step completes dicing of a partially diced wafer.
Preferably, the step of at least partially dicing comprises at least partially dicing with mechanical saw means or laser means.
Conveniently, the step of dicing the wafer comprises aligning, through transparent carrier means, alignment marks on the wafer with dicing means.
Advantageously, mounting the wafer on wafer carrier means comprises first partially dicing the wafer from the first face before mounting the wafer; and etching the back face comprises reducing the thickness of the wafer sufficiently to complete dicing of the wafer.
Advantageously, the method comprises further etching to etch sidewalls of die singulated from the wafer.
Conveniently, etching the back face is performed in parallel with etching sidewalls of singulated die.
Advantageously, the semiconductor wafer is a silicon wafer.
According to a second aspect of the invention, there is provided a dicing apparatus for dicing semiconductor wafers having a first face including active devices and a back face opposed to the first face, the apparatus comprising: wafer carrier means arranged for mounting the wafer with the back face accessible; dicing means arranged for at least partially dicing the wafer, from the back face, on the wafer carrier means; and etching means arranged for etching the at least partially diced wafer, from the back face, on the wafer carrier means with a spontaneous etchant at least for reducing defects generated by at least partially dicing the wafer, for producing an etched, at least partially diced, wafer.
Conveniently, the wafer carrier means comprises one of carrier tape means, mechanical clamping means, electrical clamping means and vacuum clamping means.
Advantageously, the etching means comprises a gaseous or liquid etchant.
Preferably, the etching means comprises a halogen or a halide compound.
Conveniently, the etching means comprises one of fluorine, chlorine, hydrochloric acid and hydrogen bromide.
Preferably, wherein the etching means comprises xenon fluoride.
Preferably the dicing means comprises mechanical saw means or laser means.
Advantageously, the dicing means comprises aligning means for aligning, through transparent carrier means, alignment marks on the wafer with the dicing means.
The invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 is a schematic perspective drawing of a semiconductor wafer mounted active side down on a carrier tape on a tape frame preparatory to processing according to a first embodiment of the present invention; Figure 2 is a schematic perspective drawing of the wafer of Figure 1 after dicing; Figure 3 is a schematic perspective drawing of the wafer of Figure 2 being dry etched; Figure 4 is a schematic thawing on an enlarged scale compared with the preceding Figures of a die removed from the diced wafer of Figure 3 and mounted on a substrate; Figure 5 is a schematic perspective thawing of a semiconductor wafer mounted active side down on a carrier tape on a tape frame preparatory to processing according to a second embodiment of the present invention; Figure 6 is a schematic perspective drawing of the wafer of Figure 5 after partial dicing; Figure 7 is a schematic vertical cross-section on an enlarged scale of the partially diced wafer of Figure 6; Figure 8 is a schematic perspective drawing of the partially diced wafer of Figures 6 and 7 being dry etched to complete dicing to form a diced wafer; Figure 9 is a schematic vertical cross-section on an enlarged scale of the diced wafer of Figure 8; Figure 10 is a schematic thawing on an enlarged scale of a die removed from the diced wafer of Figure 8 and mounted on a substrate; and Figure 11 is a flowchart of a method according to the invention. F In the Figures like reference numerals denote like parts.
Referring to Figures 1 and 11, in a first embodiment of the invention, a semiconductor wafer 10 is mounted 101 active side down on a known wafer carrier tape 11 on a tape frame 12, that is on a known dicing tape and frame.
However, the wafer carrier may be made of any optically transparent flexible or solid material that holds the wafer in place either through the use of an adhesive layer or by mechanical means such as physical, electrical or vacuum clamping.
The wafer 10, mounted on the wafer carrier 11, is aligned, either using infrared light through the carrier with alignment marks on the active side or using alignment marks on the backside, with a laser or mechanical saw and diced 102 from the backside with the laser or mechanical saw to form a diced wafer 20, as shown in Figures 2 and 11. The laser may be a diode-pumped solid-state laser, a mode-locked laser or any other laser suitable for machining the semiconductor and other materials of the wafer. Suitable laser wavelengths may be selected from infrared to ultraviolet wavelengths.
Referring to Figures 3 and 11, the diced wafer, still mounted on the wafer tape carrier 11 and tape frame 12 used in the dicing step, is placed in contact with, and etched 103 by, a spontaneous etchant of silicon for a predetermined time in a chamber 31 having an inlet 32 and an outlet 33. That is, the chamber 31 is cycled with XeF2 or, for a silicon wafer, any spontaneous etchant of silicon, followed by a chamber purge for a predetermined one or more cycles with a predetermined etching time period. However, other spontaneous etchants such as halidcs and halogen compounds in gaseous or liquid form such as, but not restricted to, F2, Cl2, HC1, I-IBr can be used for silicon or other semiconductor wafers as appropriate. The etchant removes a layer of semiconductor from the backside of the wafer and the sides of the dicing lanes, i.e. the die sidcwalls, to form an etched diced wafer 30, eliminating defects generated in the dicing process thereby increasing resultant die strength.
Alternatively, the wafer may be in the etchant environment during at least some of the dicing step.
As shown in Figure 4, the dies 40 are then removed from the wafer carrier 11 and remounted individually on a die pad 41 or die cavity of a support system of a semiconductor package.
Referring to Figures 5 to 10, in a second embodiment of the invention a semiconductor wafer 50 is mounted active side down on a known wafer carrier tape 51 on a tape frame 52. However, the wafer carrier may be made of any optically transparent flexible or solid material that holds the wafer in place either through the use of an adhesive layer or by mechanical means such as physical, electrical or vacuum clamping.
The wafer 50, mounted on the wafer carrier 51, is then aligned, either using infrared light through the carrier with alignment marks on the active side or using alignment marks on the backside, and scrihed or partially diced from the backside with a laser or mechanical saw to form a partially diced wafer 60 as shown in Figures 6 and 7. The laser may be a diode.pumped solid-state laser, a mode-locked laser or any other laser suitable for machining the semiconductor and other materials of the wafer. Suitable laser wavelengths may be selected from infrared to ultraviolet wavelengths.
Referring to Figure 8, the partially diced wafer, still mounted on the wafer tape carrier 51 and tape frame 52 used in the dicing step, is placed in contact with a spontaneous etchant of silicon for a predetermined time in a chamber 31 having an inlet 32 and an outlet 33. That is, the chamber 31 is cycled with XeF2 or, for a silicon wafer, any spontaneous etchant of silicon, followed by a chamber purge for a predetermined one or more cycles with a predetermined etching time period.
However, other spontaneous etchants such as noble halogens, halides, halogen compounds and interhalogen compounds in gaseous and liquid form such as, but not restricted to, F2; Cl7, HC1, HBr can be used for silicon or other semiconductor wafers as appropriate. The etchant completes dicing of the wafer by removing remaining semiconductor material 611 in the partial dice lanes 61 to form a diced wafer 80 as shown in Figures 8 and 9 and removes a layer of semiconductor from the backside of the wafer and the sides of the dicing lanes, eliminating defects generated in the partial dicing step thereby increasing resultant die strength. That is, the scribe or partial dice lanes 61 separating partially singulated dies 62 are etched to complete dicing lanes 81 separating singulated dies 82 mounted on the wafer tape carrier 51.
Alternatively, the wafer may be in the etchant environment during at least some of the partial dicing with the mechanical saw or laser.
As shown in Figure 10, dies 90 are then removed from the wafer carrier 11 and remounted individually on a die pad 91 or die cavity of a support system of a semiconductor package.
This embodiment has the advantage that completion of dicing occurs substantially simultaneously for all dies in a waler, avoiding stress caused by sequential singulation in known sequential dicing methods.
In both embodiments the flexural bend strength of the resultant dies may tested by a known one, three or four point flexural bend strength test.
Thus there is provided a method for producing dies 40, 90 with high die strength in which a silicon wafer, or a wafer of another semiconductor material, after or during partial or complete dicing is etched in contact with a spontaneous etchant. The method provides high flexural strength dies, as measured with, for example, in a one point, three point or four point break test, from a wafer in which the means of supplying the spontaneous silicon etchant and the means of dicing the wafers are part of a same mechanical system. That is, high flexural strength dies are produced from a wafer using an apparatus in which means of wafer alignment, wafer dicing, supplying a spontaneous silicon etchant and die removal are all part of a single mechanical sequence, without a requirement for re-mounting the wafer during the sequence.
The results of 1-point, 3-point and 4-point flexural bend strength testing show that the average die strength is higher than a die produced without such etching, although the actual value of flexural die strength is very dependent on other processes to which the die has been subjected.
The present invention has the advantage over the disclosure of US 6,498,074 that the wafer does not need to be remounted. In the present invention, the wafers are stress relieved and diced while mounted on a same carrier.
Claims (26)
- CLAIMS1. A method of dicing a semiconductor wafer having a first face including active devices and a back face opposed to the first face, the method comprising the steps of: a. mounting the wafer on wafer carrier means with the back face accessible; b. at least partially dicing the wafer on the wafer cattier means to provide an at least partially diced wafer; and c. etching the back face of the at least partially diced wafer on the wafer can-icr means with a spontaneous etchant at least to reduce defects generated in the at least partially dicing of the semiconductor wafer, to produce an etched diced wafer.
- 2. A method as claimed in claim 1, wherein the step of mounting the wafer on wafer carrier means comprises mounting the wafer on one of tape means, mechanical clamping means, electrical clamping means and vacuum clamping means.
- 3. A method as claimed in any of the preceding claims, wherein the step of etching the at least partially diced wafer comprises etching with a gaseous or liquid etchant.
- 4. A method as claimed in claim 3, wherein the step of etching with a gaseous or liquid etchant comprises etching with a halogen or a halide compound.
- 5. A method as claimed in claim 4, wherein the step of etching comprises etching with one of fluorine, chlorine, hydrochloric acid and hydrogen bromide. F
- 6. A method as claimed in claim 4, wherein the step of etching comprises etching with a noble halogen or an interhalogen compound.
- 7. A method as claimed in claim 4, wherein the step of etching comprises etching with xenon fluoride.
- 8. A method as claimed in any of the preceding claims, wherein the etching step is at least partially carried out during the dicing step.
- 9. A method as claimed in any of the preceding claims, wherein the etching step is at least partially carried out after the dicing step.
- 10. A method as claimed in any of the preceding claims wherein the etching step completes dicing of a partially diced wafer.
- 11. A method as claimed in any of the preceding claims, wherein the step of at least partially dicing comprises at least partially dicing with mechanical saw means or laser means.
- 12. A method as claimed in any of the preceding claims, wherein the step of dicing the wafer comprises aligning, through transparent carrier means, alignment marks on the wafer with dicing means.
- 13, A method as claimed in any of the preceding claims wherein: a. mounting the wafer on wafer carrier means comprises first partially dicing the wafer from the first face before mounting the wafer; and b. etching the back face comprises reducing the thickness of the wafer sufficiently to complete dicing of the wafer.
- 14. A method as claimed in claim 13, comprising further etching to etch sidewalls of die singulated from the wafer.
- 15. A method as claimed in claim 14, wherein etching the back face is performed in parallel with etching sidewalls of singulated die.
- 16. A method as claimed in any of the preceding claims, wherein the semiconductor wafer is a silicon wafer.
- 17. A dicing apparatus for dicing semiconductor wafers having a first face including active devices and a back face opposed to the first face, the apparatus comprising: a. wafer carrier means arranged for mounting the wafer with the back face accessible; b. dicing means arranged for at least partially dicing the wafer, from the back face, on the wafer carrier means; and c. etching means arranged for etching the at least partially diced wafer, from the back face, on the wafer carrier means with a spontaneous etchant at least for reducing defects generated by at least partially dicing the wafer, for producing an etched, at least partially diced, wafer.
- 18. A dicing apparatus as claimed in claim 17, wherein the wafer carrier means comprises one of carrier tape means, mechanical clamping means, electrical clamping means and vacuum clamping means.
- 19. A dicing apparatus as claimed in claims 17 or 18, wherein the etching means comprises a gaseous or liquid etchant.
- 20. A dicing apparatus as claimed in claim 19, wherein the etching means comprises a halogen or a halide compound.
- 21. A dicing apparatus as claimed in claim 20, wherein the etching means comprises one of fluorine, chlorine, hydrochloric acid and hydrogen bromide.
- 22. A dicing apparatus as claimed in claim 20, wherein the etching means comprises xenon fluoride.
- 23. A dicing apparatus as claimed in any of claims 17 to 22, wherein the dicing means comprises mechanical saw means or laser means.
- 24. A dicing apparatus as claimed in any of claims 17 to 23, wherein the dicing means comprises aligning means for aligning, through transparent carrier means, alignment marks on the wafer with the dicing means.
- 25. A method of dicing a semiconductor wafer substantially as described herein with reference to and as shown in the accompanying Figures.
- 26. A dicing apparatus substantially as described herein with reference to and as shown in the accompanying Figures.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0807101A GB2459302A (en) | 2008-04-18 | 2008-04-18 | A method of dicing wafers to give high die strength |
| TW098113117A TW201013766A (en) | 2008-04-18 | 2009-04-20 | A method of dicing wafers to give high die strength |
| PCT/EP2009/054678 WO2009127740A1 (en) | 2008-04-18 | 2009-04-20 | A method of dicing wafers to give high die strength |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0807101A GB2459302A (en) | 2008-04-18 | 2008-04-18 | A method of dicing wafers to give high die strength |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB0807101D0 GB0807101D0 (en) | 2008-05-21 |
| GB2459302A true GB2459302A (en) | 2009-10-21 |
Family
ID=39472344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0807101A Withdrawn GB2459302A (en) | 2008-04-18 | 2008-04-18 | A method of dicing wafers to give high die strength |
Country Status (3)
| Country | Link |
|---|---|
| GB (1) | GB2459302A (en) |
| TW (1) | TW201013766A (en) |
| WO (1) | WO2009127740A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7066263B2 (en) * | 2018-01-23 | 2022-05-13 | 株式会社ディスコ | Machining method, etching equipment, and laser processing equipment |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164336A (en) * | 1986-12-26 | 1988-07-07 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JP2002016021A (en) * | 2000-06-28 | 2002-01-18 | Toshiba Corp | Production method of semiconductor chip and the semiconductor chip |
| US6498074B2 (en) * | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
| JP2003179005A (en) * | 2001-12-13 | 2003-06-27 | Tokyo Electron Ltd | Method and device for separating semiconductor devices |
| WO2003100829A2 (en) * | 2002-05-20 | 2003-12-04 | Imagerlabs | Forming a multi segment integrated circuit with isolated substrates |
| US20060003551A1 (en) * | 2004-06-30 | 2006-01-05 | Freescale Semiconductor, Inc. | Ultra-thin die and method of fabricating same |
| GB2420443A (en) * | 2004-11-01 | 2006-05-24 | Xsil Technology Ltd | Dicing semiconductor wafers |
| US20060284285A1 (en) * | 2005-06-17 | 2006-12-21 | Seiko Epson Corporation | Manufacturing method for a semiconductor device, semiconductor device, circuit substrate and electronic device |
-
2008
- 2008-04-18 GB GB0807101A patent/GB2459302A/en not_active Withdrawn
-
2009
- 2009-04-20 TW TW098113117A patent/TW201013766A/en unknown
- 2009-04-20 WO PCT/EP2009/054678 patent/WO2009127740A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63164336A (en) * | 1986-12-26 | 1988-07-07 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| US6498074B2 (en) * | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
| JP2002016021A (en) * | 2000-06-28 | 2002-01-18 | Toshiba Corp | Production method of semiconductor chip and the semiconductor chip |
| JP2003179005A (en) * | 2001-12-13 | 2003-06-27 | Tokyo Electron Ltd | Method and device for separating semiconductor devices |
| WO2003100829A2 (en) * | 2002-05-20 | 2003-12-04 | Imagerlabs | Forming a multi segment integrated circuit with isolated substrates |
| US20060003551A1 (en) * | 2004-06-30 | 2006-01-05 | Freescale Semiconductor, Inc. | Ultra-thin die and method of fabricating same |
| GB2420443A (en) * | 2004-11-01 | 2006-05-24 | Xsil Technology Ltd | Dicing semiconductor wafers |
| US20060284285A1 (en) * | 2005-06-17 | 2006-12-21 | Seiko Epson Corporation | Manufacturing method for a semiconductor device, semiconductor device, circuit substrate and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201013766A (en) | 2010-04-01 |
| GB0807101D0 (en) | 2008-05-21 |
| WO2009127740A1 (en) | 2009-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1825507B1 (en) | Increasing die strength by etching during or after dicing | |
| TWI698954B (en) | Dicing wafers having solder bumps on wafer backside | |
| US20160071770A1 (en) | Plasma etching and stealth dicing laser process | |
| US20070173068A1 (en) | Etching of substrates of light emitting devices | |
| KR20100032643A (en) | Wafer temporary bonding method using si direct bonding(sdb), and semiconductor device and fabricating method thereof using the same bonding method | |
| US20120060925A1 (en) | Surface processing method of silicon substrate for solar cell, and manufacturing method of solar cell | |
| US12060266B2 (en) | Method with mechanical dicing process for producing MEMS components | |
| US20240170332A1 (en) | Wafer with test structure and method of dicing wafer | |
| JP2003197569A (en) | Method of manufacturing semiconductor chip | |
| WO2007081624B1 (en) | Notch stop pulsing process for plasma processing system | |
| GB2459302A (en) | A method of dicing wafers to give high die strength | |
| GB2459301A (en) | A method of dicing wafers to give high die strength | |
| JP5320954B2 (en) | Manufacturing method of SOI wafer | |
| CN110998797B (en) | Cutting processing method | |
| US11380586B2 (en) | Cutting method | |
| JP2008071907A (en) | Manufacturing method of semiconductor chip and semiconductor chip | |
| US20240213028A1 (en) | Silicon (Si) Dry Etch for Die-to-Wafer Thinning | |
| WO2024049863A1 (en) | Methods of separating semiconductor dies | |
| CN118737960A (en) | Method for separating semiconductor wafer | |
| Teng et al. | Medical Device Wafer Singulation | |
| JP2002076100A (en) | Silicon boat and method for manufacturing the same | |
| KR20050066170A (en) | Defect analysis method of semiconductor device | |
| CN107393875A (en) | The method for manufacturing semiconductor devices | |
| KR20060075452A (en) | Method for etching to prevent wafer damage |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| COOA | Change in applicant's name or ownership of the application |
Owner name: ELECTRO SCIENTIFIC INDUSTRIES, INC. Free format text: FORMER OWNER: XSIL TECHNOLOGY LIMITED |
|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |