GB2352346A

GB2352346A - Direct digital synthesis of variable frequency waveforms

Info

Publication number: GB2352346A
Application number: GB9917076A
Authority: GB
Inventors: Alastair Fields; Phillip James Harbord
Original assignee: Fluke Precision Measurement Ltd
Current assignee: Fluke Precision Measurement Ltd
Priority date: 1999-07-22
Filing date: 1999-07-22
Publication date: 2001-01-24
Anticipated expiration: 2019-07-22
Also published as: GB2352346B; GB9917076D0

Abstract

A direct digital synthesis circuit 30 generates variable frequency cyclic waveforms. The circuit 30 has a clock 31, a phase accumulator 33 with a frequency control input 34 for a first phase increment value, a wavetable 37 for storing waveform values, and a D/A converter 40 for generating a waveform from the waveform values. The phase values from the phase accumulator 33 have a resolution exceeding that needed to address uniquely entries in the wavetable 37. The clock circuit 31 is a variable frequency clock generator with a fine frequency control input 48 for varying the frequency of the clock pulses and hence also of the cyclic waveform, and the phase values in one cycle are the same as the corresponding phase values in a subsequent cycle of the phase values.

Description

2352346 Direct Digital Synthesis of Variable Frequency Waveforms, The

present invention relates to the use of a direct digital synthesis circuit to generate variable frequency 5 cyclic waveforms.

A direct digital synthesizer is an apparatus that generates a cyclic waveform from values of the desired waveform that have been stored in a lookup table or other :LO equivalent memory. The waveform values are clocked out of the lookup table at a predetermined time by supplying the lookup table with an address value that relates to a desired waveform value at that particular time. The address value therefore represents a phase value of the waveform to be synthesized at that time.

The phase values are generated by a phase accumulator with a predetermined phase increment between each phase value. The series of phase values generated in this way cycle to a maximum value, which is normally just under 360 degrees of phase for the cyclic waveform., and then back through a zero phase. Once the waveform value is available as an output from the lookup table, the waveform value is clocked into a digital - to- analogue (D/A) converter, for example using a clock signal from a clock which also drives the generation of the address values for the lookup table. The D/A converter then generates the synthesized waveform from the series of waveform values received from the lookup table.

For a given cyclic waveform. as stored in the lookup table, the output frequency of the synthesiser then depends on the frequency at which wave values are clocked out of the lookup table, and the size of the phase increment value.

The larger the phase increment value, the higher the frequency.

The lookup table normally stores wave values with a resolution comparable with that of the resolution of the D/A converter. For example, a typical lookup table will have a 16-bit resolution of a cyclic waveform. If the phase accumulator stores phase values also with 16 bits of resolution so that the 64k possible phase values corresponded uniquely with the 64k lookup table addresses, then the minimum achievable frequency would be the clock frequency divided by 64k. A typical clock frequency is of the order of 4 MHz, in which case the minimum frequency would be about 61 Hz. The maximum frequency achievable is just below 2 MHz. Many applications require a lower minimum frequency, or a greater frequency adjustment range.

Therefore, it is known in the prior art for the phase accumulator to store phase values with a greater resolution than the lookup table, for example 32 bits. The least significant 16 bits of the phase values are then discarded so that only the 16 most significant bits of the phase values are used as an address by the lookup table. In the case of a clock frequency of 4 MHz, this gives a frequency adjustment range of down to 9.3 x 10-4 Hz.

Although this allows a greater range of frequency adjustment, the inventors have discovered through careful observation problems in the long-term frequency stability of such slowly changing synthesized waveforms.

It is an object of the present invention to provide a direct digital synthesis circuit with improved stability at low frequency operation.

Accordingly, the invention provides a direct digital synthesis circuit for generating a variable frequency cyclic waveform, comprising a first clock circuit, a first phase accumulator circuit, a first frequency control input to the first phase accumulator by which a first phase increment value may be supplied to the first phase 5 accumulator circuit, a first waveform. circuit, the first waveform. circuit including a first lookup table storing waveform. values and a first D/A converter for generating a waveform from the waveform values, in which:

a) the first clock circuit supplies a first series of clock pulses to the first phase accumulator circuit; b) the first phase accumulator circuit upon receipt of said clock pulses generates in repetitive cycles a corresponding first series of phase values for addressing the lookup table, the phase values being sequentially incremented according to the first phase increment value and having a resolution exceeding that needed to address uniquely entries in the lookup table; C) the first phase accumulator circuit supplies the cyclical first series of phase values to the first waveform circuit; d) the first waveform circuit upon receipt of each of said phase values looks up from the first lookup table a corresponding waveform value; e) the first waveform circuit supplies said waveform values to the first D/A converter; and f) the first D/A converter upon receipt of said waveform. values generates a corresponding cyclic waveform at a frequency dependent on the first series of clock pulses and first phase increment value; - 4 characterised in that:

g) the first clock circuit includes a variable frequency clock generator with a second frequency control input for varying the frequency of the first series of clock pulses and hence also of the cyclic waveform; and h) the phase values in one cycle of the f irst series of phase values are the same as the corresponding phase values in a subsequent cycle of the f irst series of phase values.

Normally, the waveform values are supplied to the first D/A converter synchronously with the first series of clock pulses.

In order to achieve a lower minimum frequency and so increase the overall frequency range of the direct digital synthesis circuit, the first phase accumulator circuit has an address resolution that exceeds that necessary for there to be one unique phase address for each waveform value in the lookup table. For example, the phase values may have 32-bit resolution, and the waveform. values may have 16-bit resolution. The 16 least significant bits of the phase values may then be discarded when the lookup table uses the phase values to look up a waveform value. Superfluous phase address information is therefore discarded as the first phase accumulator circuit supplies the cyclical first series of phase values to the first waveform circuit.

The inventors have discovered that the low frequency instability in a variable frequency direct digital synthesizer occurs when the phase increment value is smaller in magnitude than the excess resolution of the phase values over the number of entries in the lookup table. When this is the case, it is possible f or there to be two or more consecutive phase values which result in the same waveform, entry being supplied to the D/A converter from the lookup table. Unless the phase increment value divides into the excess resolution an integral number of times with no remainder, then the number of clock cycles over which the same waveform entry is lookup up and supplied to the D/A converter will vary between n and n + 1, where n: 1. This results in low frequency variation in the D/A converter output.

Using the same phase values on each cycle of the f irst series of phase values means that the same entries in the lookup table are looked up on each cycle of the first series of phase values. The invention therefore constrains the phase increment value such that the phase values in one cycle of the first series of phase values are the same as the corresponding phase values in a subsequent cycle of the f irst series of phase values. This however limits the smoothness with which the frequency of the repetitive synthesized waveform may be varied. Therefore, the first clock circuit includes a variable frequency clock generator with a second frequency control input for varying the frequency of the first series of clock pulses and hence also of the cyclic waveform. Preferably, the frequency adjustment range of the variable frequency clock generator is sufficient so that there are no sudden or isolated steps in the frequency adjustment of the synthesized output. In the case of binary logic, the frequency adjustment range of the variable clock should theref ore be at least a f actor of two. Thus, the f irst frequency control input to the phase increment value provides a "coarse" frequency control, and the second frequency control input to the variable frequency clock provides a "fine" frequency control.

In a preferred embodiment of the invention, the variable frequency clock generator comprises a second clock circuit, a second phase accumulator circuit, the second phase accumulator circuit having the second frequency control input by which a second phase increment value may be supplied to the second phase accumulator circuit, a second waveform circuit including a second lookup table storing waveform. values, and an output stage, in which:

a) the second clock circuit supplies a second series of clock pulses to the second phase accumulator circuit; b) the second phase accumulator circuit upon receipt of said clock pulses generates in repetitive cycles a corresponding second series of phase values that are sequentially incremented according to the second phase increment value; C) the second phase accumulator circuit supplies the cyclical second series of phase values to the second waveform. circuit; d) the second waveform circuit upon receipt of each of said phase values looks up from the second lookup table a corresponding waveform value; e) the second waveform. circuit supplies said waveform. values to the output stage; and f) the output stage upon receipt of said waveform, values generates the first series of clock pulses at a frequency dependent on the second series of clock pulses and the second phase increment value.

Because of the limited range of frequency adjustment in the variable clock, the variable clock need not suffer from the frequency instability inherent in prior art

Because the variable frequency clock generator need only have a limited frequency adjustment range, it is not necessary that the phase values have a resolution exceeding that needed to address uniquely entries in the lookup table. Preferably, the phase values have a resolution equivalent to that of the lookup table. The variable frequency clock generator therefore does not suffer from the low frequency variability that can occur when the resolution of the phase values exceeds that of the lookup table.

Thus, the second phase values in one cycle of the second series of phase values are not necessarily the same as the corresponding phase values in a subsequent cycle of the second series of phase values.

The second clock circuit is preferably a fixed frequency clock circuit.

In one embodiment of the invention, the first phase 25 accumulator circuit supplies the cyclical first series of phase values to at least one additional waveform circuit This additional waveform. circuit comprises a phase adder, a phase control input to said phase adder by which a phase of f set value may be added to the f irst phase value, a lookup table storing wavef orm. values and a D/A converter for generating a waveform. from the waveform, values. The lookup table can be the first lookup table, in which case means are provided to multiplex phase values in the first and additional waveform circuits to the first lookup table and to multiplex waveform. values from the lookup table to said D/A converter. This allows a plurality of phase 8 - shif ted variable frequency cyclic waveforms to be generated.

Also according to the invention, there is provided a method of generating a variable frequency cyclic waveform using a direct digital synthesis circuit, said circuit comprising a first clock circuit, a first phase accumulator circuit, a first frequency control input to the first phase accumulator by which a first phase increment value may be supplied to the first phase accumulator circuit, a first waveform circuit, the first waveform circuit including a first lookup table storing waveform, values and a first D/A converter for generating a waveform from the waveform values, in which the method comprises the steps of:

i) supplying a first series of clock pulses from the first clock circuit to the first phase accumulator circuit; ii) upon receipt of said clock pulses using the first phase accumulator circuit to generate in repetitive cycles a corresponding first series of phase values that are sequentially incremented according to the first phase increment value and that have a resolution exceeding that needed to address uniquely entries in the lookup table; iii) supplying the cyclical first series of phase values from the first phase accumulator circuit to the first waveform circuit; iv) upon receipt of each of said phase values using the first waveform circuit to look up from the first lookup table a corresponding waveform value; V) supplying said waveform values from the first waveform circuit to the first D/A converter; and vi) upon receipt of said waveform values using the first D/A converter to generate a corresponding cyclic waveform at a frequency dependent on the first series of clock pulses and first phase increment value; characterised in that the first clock circuit comprises a variable frequency clock generator with a second frequency control input and in that the method comprises the steps of:

vii) using the second frequency control input to set the frequency of the first series of clock pulses and hence also of the cyclic waveform; and viii) in step ii) the phase values are generated in repetitive cycles such that the phase values in one cycle are the same as the corresponding phase values in a subsequent cycle. The invention will now be described by way of example, with reference to the accompanying drawings in which: 25 Figure 1 is a schematic drawing of a prior art direct digital synthesis circuit having a fixed clock, one frequency control input, and 'a phase accumulator in which phase values are not necessarily the same from 30 one cycle to the next;

Figure 2A is a schematic plot of a sinusoidal waveform produced by the circuit of Figure 1; Figure 2B is an expanded schematic plot of two subsequent zero crossings of the sinusoidal signal of Figure 2A showing differences in the phasevalues from one cycle to the next; Figure 3 is a schematic drawing of a direct digital synthesis circuit according to the invention, having a variable frequency clock, a first and a second frequency control inputs, and a phase accumulator in which phase values are the same from one cycle of the next; and Figure 4 is a more detailed circuit diagram of the phase accumulator of Figure 3.

Figure 1 shows schematically a direct digital synthesis (DDS) circuit 1 according to the prior art. The circuit comprises a clock circuit 2 with an output 4 that provides a fixed frequency square wave output C at 8 MHz to a phase accumulator circuit G. The phase accumulator 6 contains a 32-bit phase counter that increments a phase count (D by a phase increment value nO set by a 32-bit frequency control input 8. The phase accumulator G upon receipt of each clock pulse C generates on an output 10 a 1G-bit phase value OV consisting of the 1G most significant bits of the 32 bits of the phase count 4). Therefore, if the phase increment value is less than the binary value 21G, then on at least some clock pulses C the phase value OV will not change.

The phase value OV is supplied to a lookup table or "wavetable" (WT) 12 which stores in 216 separate memory addresses a digitized waveform with 16-bit resolution. The waveform is loaded into the wavetable 12 via a 16-bit waveform load input (WL) 14. The wavetable 12 uses each 16-bit phase value as an address pointer to place on a wavetable output 16 the 16-bit value of the digitized waveform at the indicated address.

A digital-to-analogue converter (D/A) 18 receives the clock pulses C from the fixed frequency clock 2 and uses these to clock into the D/A converter the 16-bit waveform value from the wavetable 12. The D/A converter 18 then produces on a D/A output 20 a continuously variable analogue voltage representative of the waveform value as 3.0 these are clocked into the D/A converter 18.

Finally, the D/A output 20 is passed through a low-pass filter 22 to a filtered output 24. The purpose of the low-pass filter is to remove unwanted frequency components from the output signal created by the synthesis technique. These include the clock frequency and complex sums and differences of the fundamental frequency and harmonics of the cyclic waveform.

Therefore, as the phase increment value A(D is increased, the repetition rate or frequency of the waveform stored in the wavetable 12 is increased.

The phase accumulator 6 has a 32-bit resolution which exceeds the resolution of the wavetable 12 so that the frequency of the output waveform can be reduced below the value of the clock frequency divided by the number of entries in the wavetable.

As a result, the number of clock cycles over which the phase count 16 most significant bits (MSB) remain the same will in general vary.

Figures 2A and 2B show the case in Figure I when the number of clock cycles is not the same f rom one cycle to the next. The wavetable 12 has been loaded with digital values 26 that represent a waveform, here a sinusoidal waveform. The waveform values 26 may however, represent any type of waveform. Other common waveforms are square, triangle or saw-tooth waveforms.

The typical resolution of the waveform will of course be much higher than that drawn. For example, there may be 64k samples over one cycle of the waveform. However, for clarity far fewer sample are shown in Figure 2A.

The digital samples 26 are then converted by the D/A converter 18 into a continuously varying analogue signal 28.

Figure 2B shows an expanded view of two subsequent zero crossings marked "A" and "B" of the sinusoidal signal of Figure 2A, together with clock pulses "C". In this example, the phase increment value AO is between onethird and one-quarter of the value of the amount needed to increment the most significant bits of the phase count 4) passed to the wavetable 12. Therefore, the number of clock cycles between changes in the wavetable values 26 can vary at a particular phase between subsequent cycles of the waveform. This can result in shifts of zero crossings as shown, or in peak positions, and hence variability in the frequency of the synthesized waveform 28.

Figure 3 shows a schematic drawing of a direct digital synthesis circuit 30 according to the invention, having a variable frequency clock 31 with an output 32 that provides a variable frequency square wave output CV at between 4 MHz and 8 MHz to a phase accumulator circuit 33. The phase accumulator 33 contains a 32-bit phase counter that increments a phase count 0 by a phase increment value ncDC set by a 32-bit frequency control input 34.

The phase accumulator 33 upon receipt of each clock pulse CV generates on an output 35 a 16-bit phase value OV consisting of the 16 most significant bits of the 32 bits 5 of the phase count (D. Therefore, if the phase increment value is less than the binary value 216, then on at least some clock pulses C the phase value (DV will not change.

The phase value OV is supplied to a lookup table or "wavetable" (WT) 37 which stores in 216 separate memory addresses a digitized waveform with 16-bit resolution. The waveform is loaded into the wavetable 37 via a 16-bit waveform load input (WL) 38- The wavetable 37 uses each 16-bit phase value as an address pointer to place on a wavetable output 39 the 16-bit value of thedigitized waveform at the indicated address. As the phase increment value LOC is increased, the repetition rate or frequency of the waveform stored in the wavetable 37 is increased.

A digital-to-analoque converter (D/A) 40 receives the clock pulses CV from the variable frequency clock 31 and uses these to clock into the D/A converter the 16-bit waveform value from the wavetable 37. The D/A converter 40 then produces on a D/A output 41 a continuously variable analogue voltage representative of the waveform value as these are clocked into the D/A converter 40.

Finally, the D/A output 41 is passed through a low-pass filter 42 to a filtered output 43, in order to f ilter out spurious frequency components generated by the D/A converter 40.

To prevent the prevent the phase comparator 33 from exhibiting low frequency instability as illustrated in Figure 2B, the phase increment value AOC is constrained so that the phase values (D in one cycle of the series of phase values produced by the phase accumulator 33 are the same as the corresponding phase values in a subsequent cycle. The most straightforward way to achieve this is if the phase increment value A(DC divides evenly into the maximum value of the least significant bits of the phase count 4) which are not passed to the wavetable 37. If M = YX is the number of entries in the wavetable, N = YZ is the phase increment value, and X and Y areintegers with X! 2 and Y: 2 (in binary, Y=2), then with Z being an integer with Z 2! 0 and Z:!- (X-1), the number of clock cycles for which the phase count most significant bits remain the same will not vary from one cycle to the next.

For example, in a 32-bit binary counter with 16 bits counting as the least significant bits not passed to the wavetable, the phase increment value AOC is constrained to be any of the series 0, 1, 2, 4, 8,... 64k. This, 20 however, means that the frequency adjustment afforded by the phase increment value 60C is not smooth by steps by a factor of two. This frequency adjustment is therefore a coarse frequency adjustment. To fill in the gaps, a fine frequency adjustment is then provided by the variable frequency clock 31, as described below.

The variable frequency clock circuit 31 may be similar to the circuit of Figure 1, with a fixed frequency clock 44 that supplies a fixed frequency square wave clock signal CF to a sine wave generation circuit 45 comprising a direct digital synthesis stage (DSS), that has a phase accumulator and wavetable loaded with the sine waveform, a D/A converter and filter (F) with an output 46. The output of the filtered sine wave goes to a comparator 47 to generate the variable frequency clock signal CV.

The frequency of the sine wave generation circuit 45 is set as follows. The phase accumulator in the DDS circuit has a 16-bit phase counter that increments a phase count as described above by a phase increment value ncDF set by a 16-bit frequency control input 48. The phase accumulator provides a 16- bit phase value output to the wavetable so a different wavetable entry will always be looked up for each of the fixed frequency clock pulses CF. Although phase values in one cycle may not be the same as the corresponding phase values in a subsequent cycle, the f requency of the D/A output will be steady because any shif ts up or down in each phase value f rom one cycle to the next will be always in one direction. This is to be compared with the shifts in phase value as illustrated in Figure 2B, which can alternate up and down from one cycle to the next.

The phase increment value A(DF need only provide a fine frequency adjustment range sufficient to fill in the gaps between the steps in coarse frequency adjustment provided by the phase increment value AcDC. For example, if the coarse frequency adjustment results in steps in frequency of a f actor of two, th en the fine frequency adjustment need only provide a similar factor-of-two adjustment.

The phase accumulator circuit will now be described in 30 more detail with reference to Figure 4. The phase accumulator 33 has an optional external phase offset input (450) 50 which can be loaded into a register 56 via a multiplexer (Mx) 51 on falling edges of an external phase load input 01) 52. Control logic 53 detects the falling edges of input OL, and is synchronized to the clock pulses CV to drive a phase j am output ((DjAM) 54 f or one clock period to load the register 56 synchronously via the multiplexer 51. The effect of this is to synchronize the phase value output 35 to an external repetitive signal of the same frequency to that being output with an adjustable phase offset.

When the register 56 is not being loaded from the phase offset 50, the multiplexer 51 selects a 32 bit adder 55 which takes the register value 60 and adds it to the phase increment AOC. This occurs on each edge of the clock pulses 32 and increments the register value 60 to give the required phase value output 35. Register 59 is not essential but balances the clock delay introduced in the other channels.

A 32 bit digital comparator 57 is used to generate an optional adjustable reference signal (OR) 61 with respect to the output waveform. An adjustable zero point crossing value M 62 is compared with the register value 60 and synchronised by the following flip-flop 58. This can be used to drive an external phase load synchronisation input OL (as described above) of another similar direct digital synthesis circuit so that the circuits can be locked together.

Returning now to Figure 3, the full 32-bit phase count Output 032 is supplied to one or more other stages which can produce in parallel with the circuitry described above the same synthesized waveform shifted in phase to the output 43. The operation of these stages is the similar to that described above, and so similar components are labelled with reference numerals incremented by 100 or 200.

17 - The full 32-bit phase count Output 4)32 is supplied to an input of adders 151,152 along with the corresponding phase offsets 150, 250. The adders 151,251 each introduce an adjustable phase shift or offset VO and cD"O which is applied to the phase inputs 135,235 of the corresponding wavetables 137, 237. This phase shift is then present in the corresponding outputs 143, 243. As these are auxiliary/slave type channels no multiplexer is required, as they will be automatically synchronized to any external synchronization of the main channel within thephase accumulator 33.

In the illustrated embodiment, each adder 151,152 passes the 16 most significant bits to a D-type flip flop 159,259 which clocks these onto an output line to the wavetable 137,237. The wavetables 37,137,237 are all loaded with the same waveform via the same waveform. load input 38.

Optionally, in an embodiment not shown in the drawings, only one wavetable 37 may be used, together with multiplexing interfaces on wavetable address inputs 35,135,235 and wavetable output lines 39,139,239.

The operation of each D/A converter 140,240 and output filter 142,242 is the same as described above.

Therefore, by setting different phase offset values 50,150,250, the circuitry can provide a plurality of different outputs 43,143,243 each with the analogue cyclic waveform. but with different relative phases.

The direct digital synthesis circuit described above provides an essentially continuously variable frequency output of a cyclic waveform. The problems of low frequency instability are avoided by the use of a variable frequency clock which operates over a relatively narrow frequency range but with fine frequency adjustment resolution, and with a variable frequency direct digital synthesis circuit which operates over a much wider frequency range, but with a coarse frequency adjustment. 5 19

Claims

1. A direct digital synthesis circuit f or generating a variable frequency cyclic waveform, comprising a first clock circuit, a f irst phase accumulator circuit, a f irst frequency control input to the first phase accumulator by which a first phase increment value may be supplied to the first phase accumulator circuit, a first waveform circuit, the first waveform. circuit including a first lookup table storing waveform values and a first D/A converter for generating a waveform from the waveform. values, in which:

a) the first clock circuit supplies a first series of clock pulses to the first phase accumulator circuit; is b) the first phase accumulator circuit upon receipt of said clock pulses generates in repetitive cycles a corresponding first series of phase values for addressing the lookup table, the phase values being sequentially incremented according to the first phase increment value and having a resolution exceeding that needed to address uniquely entries in the lookup table; c) the first phase accumulator circuit supplies the cyclical first series of phase values to the first waveform circuit; d) the first waveform circuit upon receipt of each of said phase values looks up from the first lookup table a corresponding waveform value; e) the first waveform circuit supplies said waveform values to the first D/A converter; and f) the first D/A converter upon receipt of said waveform values generates a corresponding cyclic waveform. at a frequency dependent on the first series of clock pulses and first phase increment value; characterised in that: 5 g) the first clock circuit includes a variable frequency clock generator with a second frequency control input for varying the frequency of the first series of clock pulses and hence also of the cyclic waveform; and h) the phase values in one cycle of the f irst series of phase values are the same as the corresponding phase values in a subsequent cycle of the f irst series of phase values.

2. A direct digital synthesis circuit as claimed in Claim 1, in which the variable frequency clock generator comprises a second clock circuit, a second phase accumulator circuit, the second phase accumulator circuit having the second frequency control input by which a second phase increment value may be supplied to the second phase accumulator circuit, a second waveform circuit including a second lookup table storing waveform values, and an output stage, in which:

a) the second clock circuit supplies a second series of clock pulses to the second phase accumulator circuit; b) the second phase accumulator circuit upon receipt of 30 said clock pulses generates in repetitive cycles a corresponding second series of phase values that are sequentially incremented according to the second phase increment value; c) the second phase accumulator circuit supplies the cyclical second series of phase values to the second waveform circuit; d) the second wavef orm circuit upon receipt of each of said phase values looks up f rom the second lookup table a corresponding waveform value; e) the second waveform. circuit supplies said waveform values to the output stage; and f) the output stage upon receipt of said waveform values generates the f irst series of clock pulses at a frequency dependent on the second series of clock pulses and the second phase increment value.

3. A direct digital synthesis circuit as claimed in Claim 2, in which the second phase values in one cycle of the second series of phase values are not necessarily the same as the corresponding phase values in a subsequent cycle of the second series of phase values.

4. A direct digital synthesis circuit as claimed in Claim 2 or Claim 3, in which the second clock circuit is a fixed frequency clock circuit.

5. A direct digital synthesis circuit as claimed in any of Claims 2 to 4, in which the output stage comprises a D/A converter for generating an analogue waveform. from the waveform values, and a comparator for generating a digital waveform. for the variable frequency clock pulses.

6. A direct digital synthesis circuit as claimed in any preceding claim, in which M = YX is the number of entries in the first lookup table where X and Y are integers greater than or equal to 2, and N = YZ is the f irst phase - 22 increment value where Z is an integer greater than or equal to zero and less than or equal to (X-1).

7. A direct digital synthesis circuit as claimed in any preceding claim, in which the first phase accumulator circuit supplies the cyclical first series of phase values to at least one additional waveform circuit, the additional waveform circuit comprising a phase adder, a phase control input to said phase adder by which a phase of f set value may be added to the f irst phase value, a lookup table storing waveform values and a D/A converter for generating a waveform from the waveform. values, in which said lookup table is the first lookup table, means being provided to multiplex phase values in the f irst and additional waveform circuits to the first lookup table and to multiplex waveform values from the lookup table to said D/A converter so that a plurality of phase shifted variable frequency cyclic waveforms may be generated.

8. A method of generating a variable frequency cyclic waveform using a direct digital synthesis circuit, said circuit comprising a first clock circuit, a first phase accumulator circuit, a first frequency control input to the first phase accumulator by which a first phase increment value may be supplied to the first phase accumulator circuit, a first waveform circuit, the first waveform. circuit including a first lookup table storing waveform values and a first D/A converter for generating a waveform. from the waveform values, in which the method comprises the steps of:

vii) using the second frequency control input to set the frequency of the first series of clock pulses and hence also of the cyclic waveform; and viii) in step ii) the phase values are generated in repetitive cycles such that the phase values in one cycle are the same as the corresponding phase values in a subsequent cycle.

9. A direct digital synthesis circuit substantially as herein described, with reference to or as shown in Figures 3 and 4 of the accompanying drawings.

10. A method of generating a variable frequency cyclic waveform using a direct digital synthesis circuit, substantially as herein described with reference to Figures 3 and 4 of the accompanying drawings.