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GB1190904A - Digital Data Receiver - Google Patents

Digital Data Receiver

Info

Publication number
GB1190904A
GB1190904A GB192469A GB192469A GB1190904A GB 1190904 A GB1190904 A GB 1190904A GB 192469 A GB192469 A GB 192469A GB 192469 A GB192469 A GB 192469A GB 1190904 A GB1190904 A GB 1190904A
Authority
GB
United Kingdom
Prior art keywords
counter
bits
register
signal
key
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB192469A
Inventor
Andre Senizergues
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1190904A publication Critical patent/GB1190904A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0637—Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

1,190,904. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 13 Jan., 1969 [16 Jan., 1968], No. 1924/69. Heading H4P. A receiver, fed by a digital signal comprising blocks of d data bits separated by s synchronizing bits, is synchronized by circuitry comprising a comparator, which compares groups of the received signals with locally generated sync. bits, and a counter which is incremented or decremented depending upon the comparator output. In the embodiment described the received signal is in ciphered form. The signal and a key signal are fed to a signal register and a key register, respectively, each of capacity s-bits, the registers' serial outputs being modulo-2 added to provide the clear text. The parallel outputs of the registers pass to a comparator in which corresponding bits are modulo-2 added, a counter giving an output if the number of unlike bits in the compared synchronized sequences is less than, for example, 3. At the end of each cycle of d + s clock pulses the counter output is sampled. If there are less than 3 inequalities, resulting in a " positive " comparison, a second counter having a maximum count of 8 is incremented by one unless the counter is already at count 8. The counter is decremented if there are more than 2 inequalities. Should the counter reach zero loss of sync. is assumed and a resynchronization process takes place. In this process the key signal generator and register are stepped forward very rapidly by 4(d + s) steps and are held in the position attained while comparison is made, at received bit rate, between the contents of the key register and the words successively appearing in the signal register. If no positive comparison occurs during a period of 8(d + s) received bits the key generator and register are stepped rapidly by 8(d + s) steps, and further comparison takes place over a period of 8(d + s) bits. This cycle repeats until a positive comparison occurs, whereupon the second counter is incremented and the resynchronization process stops, it being re-initiated if the counter reverts to zero.
GB192469A 1968-01-16 1969-01-13 Digital Data Receiver Expired GB1190904A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR6008978 1968-01-16

Publications (1)

Publication Number Publication Date
GB1190904A true GB1190904A (en) 1970-05-06

Family

ID=8970688

Family Applications (1)

Application Number Title Priority Date Filing Date
GB192469A Expired GB1190904A (en) 1968-01-16 1969-01-13 Digital Data Receiver

Country Status (3)

Country Link
DE (1) DE1815233B2 (en)
FR (1) FR1582790A (en)
GB (1) GB1190904A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2311457A1 (en) * 1975-05-12 1976-12-10 Gen Electric RADIO-COMMUNICATION SYSTEM
GB2233861A (en) * 1989-05-04 1991-01-16 Stc Plc Sequence synchronisation

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3843893A (en) * 1973-07-20 1974-10-22 Hewlett Packard Co Logical synchronization of test instruments
CH581930A5 (en) * 1975-02-05 1976-11-15 Europ Handelsges Anst
CH603014A5 (en) * 1975-02-05 1978-08-15 Europ Handelsges Anst
US4022973A (en) * 1975-05-12 1977-05-10 General Electric Company Apparatus for indicating synchronization and out-of-synchronization conditions
DE2631823C3 (en) * 1976-07-15 1984-03-01 ANT Nachrichtentechnik GmbH, 7150 Backnang Method for synchronizing key devices for data transmission systems
NL7710503A (en) * 1977-09-27 1979-03-29 Philips Nv DIGITAL TRANSMISSION SYSTEM.
DE3103574C2 (en) * 1981-02-03 1983-06-16 Siemens AG, 1000 Berlin und 8000 München Circuit arrangement for establishing and maintaining synchronization between envelope clock pulses derived from locally generated bit clock pulses and synchronization bits contained in envelopes of a binary-coded signal
JPS59221047A (en) * 1983-05-30 1984-12-12 Victor Co Of Japan Ltd Synchronizing signal detecting circuit for digital signal transmission
DE3484245D1 (en) * 1984-05-29 1991-04-11 Siemens Ag METHOD AND ARRANGEMENT FOR MONITORING THE SYNCHRONOUS RUN OF KEY DEVICES.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2311457A1 (en) * 1975-05-12 1976-12-10 Gen Electric RADIO-COMMUNICATION SYSTEM
GB2233861A (en) * 1989-05-04 1991-01-16 Stc Plc Sequence synchronisation
US5237593A (en) * 1989-05-04 1993-08-17 Stc, Plc Sequence synchronisation
GB2233861B (en) * 1989-05-04 1993-09-01 Stc Plc Sequence synchronisation

Also Published As

Publication number Publication date
FR1582790A (en) 1969-10-10
DE1815233B2 (en) 1976-11-18
DE1815233A1 (en) 1969-08-14

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee