ES2393541T3 - Printhead module with lowered alignment and printer driver to supply data to that - Google Patents

Abstract

A printhead module includes at least one row of printhead nozzles. Each row includes at least one displaced row portion. The displacement of the row portion includes a component in a direction normal to that of a pagewidth to be printed.

Description

Printhead module with lowered alignment and printer driver to supply data to that

Field of the Invention

The present invention relates to inkjet printers with page width.

Background

Page width printheads can be made from multiple head chips butt print with each other. Accordingly, multiple identical printhead chips must be capable of being linked together to form a print head mounted effectively horizontal.

EP-A-1405722 describes a printhead comprising a series of printhead modules. Offset printing with overlapping nozzles.

Summary of the Invention

The present invention discloses a printhead module, a printhead and a controller printer, as defined below in the appended claims.

Brief description of the drawings

Figure 1. Simplex SoPEC A4 single system Figure 2. Simplex SoPEC A4 dual system Figure 3. Dual SoPEC A4 duplex system Figure 4. Dual SoPEC A3 duplex system Figure 5. Simplex SoPEC A3 quad system Figure 6. Simplex SoPEC A4 system with extra SoPEC used as DRAM storage Figure 7. Simplex SoPEC A4 system with network connection to main PC Figure 8. Construction of the impression and position of the nozzles Figure 9. Conceptual horizontal misposition between segments Figure 10. Positioning printhead alignment and projection order alignment by default Figure 11. Projection order of fractionally misaligned segment Figure 12. Example of deviation (“yaw”) in wrong positioning of the print head IC Figure 13. Vertical separation of the nozzles Figure 14. Single printhead chip and second chip connection Figure 15. Two printheads connected to form a larger printhead Figure 16. Color arrangement Figure 17. Displacement of the nozzle at the connection ends Figure 18. Binding diagram Figure 19. Block diagram Figure 20. TDC block diagram Figure 21. TDC waveform Figure 22. TDC construction

Detailed description of the preferred embodiment

Several aspects of the preferred description and other embodiments will be described below. It will be noted that the following description is a very detailed exposition of the hardware and associated methods, which together they provide a printing system capable of relatively high resolution, high speed and low cost printing compared to previously known systems.

Much of this description is based on technical design documents, so the use of such words such as “should be” (“must”), “should be” (“should”) and “will” (“will”), and all others that suggest limitations or Positive performance characteristics of a given product should not be construed to apply to the invention in general. These comments if they do not clearly refer to the invention in general, should be considered as desirable or intended characteristics in a specific design instead of a requirement of the invention. He Desired scope of the invention is defined in the claims.

Also throughout this description, the terms "printhead module" and "printhead" are They also use something interchangeably. Technically, a "printhead" comprises one or more "Printhead modules", but occasionally, the former is used to refer to the latter. It should be clear from the context what meaning should be attributed to any use of the word “head of Print".

In general:

Link printhead (“Linking Printhead”) refers to a page width printhead, constructed from multiple link printhead ICs

CI printhead link to MEMS CI. Multiple ICs link together to form a complete printhead. An A4 page width printhead requires 11 printhead ICs.

1. Introduction

The SoPEC ASIC (Small Office Home Office Print Engine Controller) is suitable for use in economically priced SoHo printer products. The SoPEC ASIC is intended to be a relatively low cost solution for linking printhead control, replacing multiple chip solutions in larger, more professional systems, with a single chip. The increased cost competitiveness is achieved by integrating several systems, such as a pipeline, unique PEC1 printing, CPU control system, peripherals and memory subsystems in an ASIC SoC, reducing the number of components and simplifying the Printed circuit design The SoPEC contains features that make it suitable for multifunction or “all-in-one” devices, as well as specialized printing systems.

This section will facilitate a general introduction to “Memjet” printing systems, present the components that form a link printhead system, describe a series of system architectures and show how several SoPECs can be used to achieve Faster, wider and / or duplex printing. The "SoPEC ASIC" section describes the SoPEC ASIC SoC with subsections describing the CPU, DRAM and duct subsystems of the printing apparatus. Each section provides a detailed description of the blocks used and their operation within the general printing system.

The basic features of the preferred embodiment of SoPEC include:

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Continuous operation at 30 ppm for 1600 dpi of production in A4 / letter

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Linear scaling facility (multiple SoPEC) for increased print speed and / or page width

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192 MHz internal system clock derived from low speed crystal input

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The PEP process pipeline supports up to 6 color channels at 1 point per channel per clock cycle

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Decompression of the color plane by hardware, label supply, halftones and composition

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Data formatting for link printhead

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Flexible compensation of inactive nozzles, misalignment of the printhead, etc.

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Integrated 20 Mbit DRAM (2.5 MByte) for data printing and CPU program storage

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32-bit RISC CPU LEON SPARC v8

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Supervisor and user modalities to support multiple wiring and security software

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1 kB of each of I-cache and D-cache, both directly mapped, with optimized 256-bit fast cache update

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1xUSB 2.0 device port and main USB 2.0 ports (including integrated PHY)

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Supports high speed USB 2.0 (480 Mbit / sec) and full speed (12 Mbit / sec) modes

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Provides interface to main PC, other SoPEC and external devices, for example, digital camera

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Activate alternative interfaces of the main PC, for example, via external USB / Ethernet bridge

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High-speed LVDS serial interface without glueless to multiple link printhead chips

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64 GPIO remapeables, selectable among combinations of integrated system control components:

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2 x LSS interfaces for QA or EEPROM serial chip

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LED controllers, sensor inputs, switch control outputs

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Motor controllers for stepper motors and brushless DC motors

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Microprogrammed multi-protocol media interface for scanner, RAM / external flash memory, etc.

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Unique ID 112 bits and random number 112 bits in each device, combined for security protocol support

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CMOS process IBM Cu-11 0.13 microns, 1.5 V core supply, 3.3 V 10.

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Flat connection (Flat pack) 208 Plastic Quad pin

2 Print quality considerations

The preferred embodiment of the link printhead produces 1600 dpi bi-level dots. On low diffusion paper, each projected droplet forms a point of 22.5 m in diameter. The points are easily produced in isolation, allowing the exploitation of the dispersion points to the maximum possible. Since the preferred shape of the link printhead is page width and operates at a constant paper speed, the color planes are printed with good alignment, allowing point-to-point printing. Point-to-point printing minimizes “dirtying” of the midtones caused by bleeding between colors.

A page layout can contain a mixture of images, graphics and text. Continuous tone images and graphics (contone) are reproduced using stochastic scattered point oscillation. Unlike an oscillation of point clusters, (or amplitude modulated), an oscillation of scattered or frequency modulated points, reproduces high spatial frequencies (i.e., image detail) almost within the limits of point resolution, while which, simultaneously, reproduces lower spatial frequencies in their full color depth, when they are spatially integrated by the eye. A stochastic oscillation matrix is carefully designed so that it is free of objectionable low-frequency drawings when applied to the image. Thus, their dimensions typically exceed the minimum dimensions required to support a specific number of intensity levels (for example, 16 16 8 bits for 257 intensity levels).

The human contrast sensitivity reaches a maximum with a spatial frequency of about 3 cycles per degree of visual field and then falls logarithmically, decreasing by a factor of 100 beyond 40 cycles per degree, becoming immeasurable beyond 60 cycles per degree. At a normal viewing distance of 12 inches (about 300 mm), this translates to approximately 200-300 cycles per inch (cpi) on the printed page or 400-600 samples per inch, according to the Nyquist theorem.

In practice, the contone resolution above 300 dpi is of limited utility outside of special applications such as medical images. Magazine offset printing, for example, uses contone resolutions within a range of 150 to 300 ppi. Higher resolutions contribute slightly to color errors due to oscillation.

Black text and graphics are reproduced directly using bi-level black dots and, therefore, are not smoothed ("anti-aliased") (ie, low-pass filtering) before being printed. The text must, therefore, be oversampled, beyond the perceptual limits explained above to produce softer edges when spatially integrated by the eye. Text resolution up to about 1200 dpi continues to contribute to the perceived definition of the text (assuming low diffusion paper).

A Netpage printer, for example, can use a "contone" resolution of 267 ppi (ie 1600 dpi 6), and black text and graphics resolution of 800 dpi. A printer with high office or department characteristics can use a contone resolution of 320 ppi (1600 dpi / 5) and a resolution of black text and graphics of 1600 dpi. Both formats are able to overcome the quality of commercial printing ("offset") and photographic reproduction.

3 memjet printer architecture

The SoPEC device can be used in various configurations and printer architectures.

In general, any SoPEC-based printer architecture in a preferred embodiment will contain:

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One or more SoPEC devices

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One or more link printheads

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Two or more LSS buses

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Two or more QA chips

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Connection to host computer directly through USB 2.0 or indirectly

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Connections between SoPECs (when multiple SoPECs are used)

Some example printer configurations are outlined in section 4.2. The different system components are briefly outlined in section 4.1.

4.1 System components 4.1.1 SoPEC printing device driver

The SoPEC device contains several systems in a chip component (SoC), as well as the specific logic system of the pipeline control application of the printing apparatus.

4.1.1.1 Duct Logic System (PEP)

The PEP reads compressed page data compressed from the built-in memory, optionally decompresses the data and formats it to be sent to the printhead. The functionality of the pipeline of the printing apparatus includes the expansion of the image of the page, the oscillation of the contone layer, the composition of the black layer on the contone layer, supply of Netpage labels, compensation for inactive nozzles of the print head and sending the resulting image to the link print head.

4.1.1.2 Built-in CPU

The SoPEC contains a built-in CPU for configuration and management of the general system type. The CPU performs the process of the page and the header band, motor control and sensor monitoring (through the GPIO) and other system control functions.

The CPU can perform buffer management or it can report the status of the buffer to the host computer. The CPU can optionally operate with a specific application code from the supplier of the device for general printing control, such as monitoring of ready or ready paper and updating the status of the LED.

4.1.1.3 Built-in buffer

A built-in 2.5 MByte buffer is integrated into the SoPEC device, of which approximately 2 MBytes are available for stored data from compressed pages. A compressed page is divided into one or more bands, with a series of bands stored in memory. When a page band is consumed by the PEP for printing, a new band can be downloaded. The new band may be destined for the current page or the next page.

Using the band layout, it is possible to start printing a page before downloading the entire compressed page, but care must be taken to ensure that the data is always available for printing or a buffer failure may occur.

A storage SoPEC could be used acting as a buffer (section 4.2.6) to ensure a guaranteed supply of data.

4.1.1.4 Built-in USB 2.0 device driver

The built-in single-port USB 2.0 device driver can be used as an interface with respect to the main PC or for communication with another SoPEC such as ISCSlave (slave). Accepts data from compressed pages and controls the instructions of the main PC or SoPEC ISCMaster (master) and transfers the data to built-in memory for printing or downstream distribution.

4.1.1.5 Built-in USB 2.0 host controller

The built-in three-port USB 2.0 host controller enables communication with other SoPEC devices such as ISCMaster (master), as well as interface with external chips (for example, Ethernet connection) and external USB devices, such as digital cameras.

4.1.1.6 Built-in device / motor controllers

The SoPEC contains built-in drivers for a number of printer system components, such as motors, LEDs, etc. which are controlled through the GPIO of SoPEC. This minimizes the need for external circuits with respect to SoPEC to constitute a complete printer system.

4.1.2 Link printhead

The printhead is constructed by the butt arrangement of a series of printhead ICs together. Each SoPEC can drive up to 12 printhead ICs with data rates up to 30 ppm or 6 printhead ICs at data rates of 60 ppm. For higher data rates

or wider printheads should use multiple SoPECs.

4.1.3 LSS interface bus

Each SoPEC device has two LSS system buses for communication with QA devices for system authentication and accounting of ink consumption. The number of QA devices per bus and their position in the system is not restricted except for the PRINTER_QA and INK_QA devices, which must be found on separate LSS buses.

4.1.4 QA devices

Each of the SoPEC systems can have several QA devices. Normally, each print SoPEC will have an associated PRINTER_QA. The ink cartridges will contain a QA chip. The PRINTER_QA and INK_QA devices must be on separate LSS buses. All QA chips in the system are physically identical with flash memory content that PRINTER_QA defines with respect to INK_QA.

4.1.5 Connections between SoPECs

In a multiple SoPEC system, the primary communication channel takes place from USB 2.0. A main port on a SoPEC (the ISCMaster) to the USB 2.0 device of each of the other SoPECs (ISCSlave). If there is more SoPEC and ISCSlave than USB main ports available on the ISCMaster, additional connections could take place through a USB host computer chip or daisy-chain SoPEC chips. Typically, one or more GPIO SoPEC signals would also be used to communicate specific aspects between multiple SoPECs.

4.1.6 Main PC communication without USB

Communication between the host PC and the SoCEC ISCMaster may involve an external chip or subsystem to provide a host interface without USB, such as Ethernet or WiFi. This subsystem may also contain memory to provide additional buffer / page storage in buffer that could provide a guaranteed bandwidth for supplying data to the SoPEC during printing of complex pages.

4.2 Possible SoPEC systems

There are several possible architecture systems based on SoPEC. The following sections summarize some possible architectures. It is possible to have additional SoPEC devices in the system used for DRAM storage. The displayed configurations of the QA chip are indicative of the flexibility of the LSS bus architecture, but are not limited to these configurations.

4.2.1 Simplex A4 at 30 ppm with 1 SoPEC device

In Figure 1 a single SoPEC device is used to control a link printhead with 11 printhead ICs. The SoPEC receives compressed data from the host computer through the USB device port. Compressed data is processed and transferred to the print head. This provision is limited to a speed of 30 ppm. The unique SoPEC also controls all printer components, such as motors, LEDs, push buttons, etc., directly or indirectly.

4.2.2 Simplex A4 at 60 ppm with 2 SoPEC devices

In Figure 2, two SoPECs control a single link printhead, providing A4 printing at 60 ppm. Each of the SoPEC controls 5 or 6 of the printhead ICs that constitute the entire printhead. SoPEC # 0 is the ISCMaster, or SoPEC # 1 is an ISCSlave. The ISCMaster receives all compressed page data for both SoPECs and redistributes them in the form of compressed data for the ISCSlave through a local USB bus. There is a total of 4 MBytes of page storage memory available if necessary. It should be noted that if each page has 2 MBytes of compressed data, the USB2.0 interface to the host computer needs to run at high speed (not full speed) to support printing at 60 ppm. (In practice, many compressed pages will be much smaller than 2 MBytes.) The control of the printer components such as motors, LEDs, pushbuttons, etc., is shared between the 2 SoPECs in this configuration.

4.2.3 Duplex A4 with 2 SoPEC devices

In Figure 3, two SoPEC devices are used to control two printheads. Each printhead prints the opposite sides of the same page to get duplex printing. The SoPEC # 0 is the ISCMaster, the SoPEC # 1 is an ISCSlave. The ISCMaster receives all compressed page data for both SoPEC and redistributes the compressed data for the ISCSlave via a local USB bus. This setting could print 30 double-sided pages per minute.

4.2.4 Simplex A3 with 2 SoPEC devices

In Figure 4, two SoPEC devices are used to control a link head A3 constituted from 16 print head ICs. Each of the SoPEC controls 8 printhead ICs. The system works similarly to the A4 system at 60 ppm in Figure 2, although the speed is limited to 30 ppm for A3, since each SoPEC can control only 6 printhead ICs at speeds of 60 ppm. A total of 4 Mbytes of page storage is available, which allows the system to use compression rates as in a single SoPEC A4 architecture, but with the increased A3 page size.

4.2.5 Duplex A3 with 4 SoPEC devices Figure 5 shows a system of four SoPECs. Contains 2 A3 link printheads, one for each side of an A3 page. Each of the printheads contains 16 CI printheads. Each SoPEC controls 8 printhead ICs. SoPEC # 0 is the ISCMaster with the other SoPEC as ISCSlaves. Note that all USB host ports on SoPEC # 0 are used to communicate with the 3 SoPEC ISCSlave. In total, the system contains 8 Mbytes of compressed page storage (2 Mbytes per SoPEC), so that the increased page size does not degrade the print quality of the system with respect to a simplex A4 printer. The ISCMaster (ISCMaestro) receives all the compressed pages for all SoPECs and redistributes the data compressed by the local USB bus to the ISCSlaves. The configuration could print 30 A3 sheets double-sided per minute. 4.2.6 DRAM SoPEC storage solution: Simplex A4 with 1 print SoPEC and 1 memory SoPEC

Additional SoPECs can be used for DRAM storage, for example, in Figure 6, a simplex A4 printer can be constructed with a single additional SoPEC used for DRAM storage. The SoPEC DRAM can provide guaranteed broadband data supply to the printing SoPEC. SoPEC configurations can have multiple additional SoPECs used for DRAM storage.

4.2.7 Connection without USB to the main PC

Figure 7 shows a configuration in which the connection from the main PC to the printer is an Ethernet network instead of USB. In this case, one of the main USB ports in SoPEC is interconnected to an external device that provides Ethernet-to-USB connection. It should be noted that some support network software in the connection device may be required in this configuration. A flash RAM will be required in this system to provide SoPEC with control software for the Ethernet connection function.

5 Types of wrong printhead placement

5.1 Construction of the printhead

A link printhead is constructed from the ICs of the link printhead, placed on a substrate containing ink supply holes. An A4 page width printer uses 11 link printhead ICs. Each of the printheads is placed on the substrate with reference to registration marks of positioning of the substrate.

Figure 8 shows the arrangement of the print head ICs (also known as segments) on a print head. The union between two ICs is shown in detail. The leftmost nozzles in each alignment are lowered by 10 line-steps to allow continuous printing through the joint. Figure 8 also presents some designations and coordinated conventions used in this document.

Figure 8 shows the anticipated arrangements of the first generation of link printheads with 10 nozzle alignments that support five colors. The SoPEC compensation mechanisms are general enough to cover other nozzle arrangements.

5.2 Types of placement errors

Printhead ICs can be placed incorrectly with respect to their ideal position. This wrong placement may include any combination of:

3. displacement in x

3. displacement in and

3. deviation (rotation around z)

3. pitching (rotation around y)

3. balancing (rotation around z)

In some cases, the best visual results are achieved by considering rotational placement error between adjacent ICs instead of absolute placement error from the substrate. There are some practical limits to the placement error due to the fact that a gross placement error will interrupt the flow of ink from the substrate to the ink channels of the chip.

Correction of placement errors obviously requires measurement of placement error. In general, this can be done directly by head inspection after assembly or indirectly by scanning or examining a printed model test.

6 Compensation for placement error 6.1 X offset

The SoPEC can compensate for the error of placement of link chips in the X direction in the middle of the next point, that is, a placement error of less than 0.5 step-steps or 7.9375 microns is not compensated, an error of placement greater than 0.5 step-points but less than 1.5 step-points is treated as a mistake of placing a step-step, etc.

The error of placement in X without compensation can result in three effects:

3. printed points shifted from their correct position throughout the wrong placement segment

3. missing points in the zone of overlap between segments

3. duplicate points in the zone of overlap between segments

SoPEC can correct each of these three effects.

6.1.1 Correction for the X position as a whole

In preparing line data for printing, the SoPEC places dot data in the buffer for a series of lines in the image to be printed. Compensation for erroneous placement generally involves changing the model in which this point data is passed to the print head ICs.

The SoPEC uses separate buffers for the odd and even dots of each color on each line, since they are printed by different printhead alignments. Thus, the SoPEC appreciation of a line at this stage is like (up to) 12 point alignments, instead of (up to 6 colors). Nominally, the even points of a line are printed by the lower alignment of two alignments for that color in the print head and the odd points are printed by the upper alignment (see figure 8). For the CI of the print head link of the moment, there are 640 nozzles in an alignment. Each buffer in an alignment for the entire printhead would contain 640x11 dots per line to be printed, in addition to some compensation if necessary.

In preparing the image, the SoPEC can be programmed in the DWU module to pre-compensate for the fact that each alignment or CI of the print head is shifted to the left with respect to the upper alignment. In this way, the leftmost point printed for each alignment of a color has the same offset from the beginning of a buffer of an alignment. In reality, programming can support arbitrary forms of the head IC.

The SoPEC has independent records in the LLU module for each segment that determine which point of the prepared image is sent to the leftmost nozzle of that segment. Up to 12 segments are supported. Without placement error, the SoPEC could be programmed to pass points 0 to 639 in an alignment to segment 0, points 640 to 1279 in an alignment to segment 1, etc.

If segment 1 were misplaced by 2 step-points to the right, the SoPEC could be adjusted to pass points 641 to 1280 of each alignment to segment 1 (remembering that each data alignment consists entirely of odd points or even points from a line, and that point 1 of an alignment is printed 2 point positions away from point 0). This means that the dots are printed in the correct position in a general way. This setting is based on the absolute placement of each printhead IC. Point 640 is not printed, since there is no nozzle in this position of the print head (see section 6.1.2 for more details on offsetting missing points).

An error of placing an odd number of step-points is more problematic, because it means that the odd points of the line need to be printed by the lowest alignment of a pair of color and the odd points by the upper alignment of a pair of color by the head segment of a printing pair. In addition, changing odd and even buffers interferes with pre-compensation. This results in the position of the first point to be sent to a segment being different for odd alignments and even alignments of the segment. The SoPEC solves this effect by making independent LLU records specify the first point for the odd and even alignments of each segment, that is, 2 x 12 records. Another register bit determines whether the point data for odd alignments and even alignments should be changed according to a segment-by-segment basis.

6.1.2 Correction for duplicate and missing points

Figure 9 shows the detailed alignment of points at the junction between two CIs of the printhead for several instances of placement error for a single color.

The effects on the joint depend on the relative placement error of the two segments. In the ideal case without placement error, the last three nozzles of the upper alignment of the N segment interlock the three nozzles of the lower alignment of the N + 1 segment, resulting in a single nozzle (and, therefore, a single point printed) at each step-point.

When the N + 1 segment is wrongly placed to the right with respect to the N segment (a positive relative displacement, according to x) there are some positions of points without a nozzle, that is, missing points. For positive displacements of an odd number of step-points there may also be some point positions with two nozzles, that is, duplicate points. The relative negative displacements in X of the N + 1 segment with respect to the N segment are less likely, since they would usually result in a collision of the print head ICs, however, they are possible in combination with a Y displacement. A negative displacement will always cause duplicate points and will cause missing points in some cases. It should be noted that placement and tolerances can be deliberately shifted to the right at the manufacturing stage to avoid negative displacements.

In the case where two nozzles occupy the same point position, the corrections described in section 6.1.1 will result in the SoPEC reading the same point data from the alignment buffer for both nozzles. To avoid printing this data twice, the SoPEC has two records per segment in the LLU that specify a number (up to 3) of points to be deleted at the beginning of each alignment, one record being applied to the odd alignment of points and another to even point alignments.

The SoPEC compensates for the missing points by adding the missing nozzle position to its inactive nozzle map. This indicates the logic of compensation of inactive nozzles in the DNC module to distribute the data from the indicated position to the surrounding nozzles before preparing the buffers of alignments to be printed.

6.2 Y offset

The SoPEC can compensate for the error of placing the printhead ICs in the Y direction, but only halfway with respect to the nearest 0.1 fraction of a line, assuming a 15.875 micron line-step if an IC is incorrectly placed in Y at 0 microns the SoPEC can print perfectly in Y. If an IC is incorrectly placed at 3,175 microns then it can be printed perfectly. If a CI is wrongly placed at Y at 3,175 microns, it can be printed perfectly, but if a CI is badly placed at 3 microns, it is recorded as a placement error of 3,175 microns (mediated to the nearest 0.1 of a line ) and resulting in a Y error of 0.175 microns most likely an imperceptible error.

The uncompensated Y-placement error results in all points of the incorrectly placed segment being printed in the wrong position on the page.

The SoPEC compensation for Y-placement error uses two mechanisms, one directed to the joint line-step placement error and another directed to the fractional line-step erroneous placement. These mechanisms can be applied together to compensate for arbitrary placement errors to the nearest 0.1 of a line.

6.2.1 Compensation for placement error according to complete line-step

Section 6.1 describes the buffers used to preserve the point data to be printed for each alignment. These buffers contain point data for multiple lines of the image to be printed. Due to the physical separation of nozzle alignments from a print head IC, different alignments print data from different lines of the image at any time.

For a printhead, in which all ICs are ideally positioned, alignment 0 of each segment prints data from line N of the image, alignment 1 of each segment prints data of alignment NM of the image, etc., where N is the separation of alignments 0 and 1 in the printhead. The separate SoPEC registers in the LLU for each alignment specify the intended separations of alignments in the print head, so that the SoPEC tracks the current image printed by each alignment.

If a segment is incorrectly placed in a complete line-step, the SoPEC can compensate for it by adjusting the line of the image sent to each alignment of that segment. This is achieved by adding an additional offset of the buffer address of the alignment used in this segment for each buffer buffer. This shift causes the SoPEC to provide the point data to each alignment of said segment from a line located later in the image than the point data provided to the same alignment in the other segments. For example, when correctly placed segments are printing the line, of an image with alignment 0, the NM line of the image with alignment 1, etc., then the misplaced segment is printing the N + 1 line of the image with the alignment 0, line N-M + 1 of the image with alignment 1, etc.

The SoPEC has one record per segment to specify that complete line-step offset. The displacement can be of multiple lines-steps compensating multiple lines of placement error. It should be noted that the displacement can take place only in the forward direction, corresponding to a negative displacement of Y. This means that the initial arrangement of the SoPEC must be based on the highest (most positive) segment on the Y axis, and Offsets for other segments must be calculated from this baseline. Offset compensation in Y requires additional lines of dot data buffer in the SoPEC equal to the maximum relative offset in Y (in step lines) between any two segments of the print head. For each misplaced segment, each line of placement error requires approximately 640x10, that is, 6,400 extra bits of memory.

6.2.2 Compensation for fractional line-step placement error

The compensation for fractional line-step displacement of a segment is achieved by a combination of SoPEC and logical activation system CI printhead.

The nozzle alignments of the printhead are positioned by design with vertical separations in step lines that have an entire component and a fractional component. Fractional components are expressed with respect to alignment 0 and are always some multiple of 0.1 of a line-step. The alignments are sequentially actuated in a certain order and the fractional component of the alignment separation is adapted to the distance in which the paper will travel between the activation or activation of one alignment and the next. Figure 10 shows the alignment position and drive order of the current implementation of the print head IC. Observing the first two alignments, the paper shifts from 0.5 of a line-step between alignment 0 (first operated) and alignment 1 (operated sixth). Receive data from points on a line that is located 3 lines before the data provided to alignment 0. This data ends on paper exactly with a 3-step line separation, as required.

If a print head IC is erroneously positioned vertically on a non-integer number of lines, the alignment 0 of that segment no longer aligns with the alignment 0 of other segments. However, in 0.1 of a closer line, there is an alignment in the segment with placement error that is a whole number of line-steps away from the alignment 0 of the ideally located segments. If this alignment is activated at the same time as the alignment 0 of other segments and receives the data feed of points from the correct line, then its points will be aligned with the points of alignment 0 of the other segments within 0.1 of a line-step. Subsequent alignments can then be activated on the printhead with placement error in the usual order, going back to alignment 0 after alignment 9. This activation order results in the activation of each alignment at the same time as the alignments of other printheads closer to an integer line-step away.

Figure 11 shows an example in which the segment with placement error is shifted by 0.3 of a step line. In this case, segment alignment 5 with placement error is exactly 24.0 lines steps from alignment 0 of the ideal segment. Therefore, alignment 5 is activated first in the segment with placement error, followed by alignment 7, 9, 0 etc., as shown. Each alignment is activated at the same time as the alignment in the ideal segment, which is an integer number of lines in distance. This selection of the initial alignment of the activation sequence is controlled by a register of each printhead IC.

The role that SoPEC plays in compensating for the fractional line-step placement error is to provide correct point data for each alignment. Looking at Figure 11, it can be seen that to print correctly, the alignment 5 in the printhead with placement error requires data from points of a line located 24 lines earlier in the image than the data supplied to alignment 0. In the ideal printhead, alignment 5 requires dot data from a line located 23 lines earlier in the image than the data provided in alignment 0. In general, when a non-skip start alignment is used for a segment, some Alignments for that segment need to shift their data on a line with respect to the data they would receive for a skipped start alignment. The SoPEC has an LLU record for each alignment of each segment that specifies whether a line offset must be applied when searching for data for that segment alignment.

6.3 Balancing (rotation around X)

This type of wrong displacement by rotation means that all the nozzles will end up pointing higher on the page in the Y direction or lower on the page in the Y direction. The effect is the same as that of the Y-placement error, except that there is a different effect on Y for each medium thickness (since the magnitude of the placement error depends on the distance the ink has to travel.

In some cases it may happen that the thickness of the media does not cause an effective visual difference with the result and this form of placement error can simply be incorporated into the Y placement error compensation.

If the media thickness does not make a difference that can be characterized, then the programming of the wrong Y placement can be adjusted for each print, based on the media thickness.

It will be appreciated that the correction for balancing is particularly of interest when more than one printhead module is used to form a printhead, since it is the discontinuities between bands printed by adjacent modules that are most objectionable in this context.

6.4 Pitch (rotation around Y)

In this rotation, one end of the IC enters more into a substrate than the other end. This means that printing on the page will be far away at a certain number of points at the end of what is far away from the media (i.e. lower optical density) and the points will be closer together to the nearest end. to the media (more optical density) with a linear reduction of the effect from one end to the other. If this produces any type of visual artifact, it is unknown, but it is not compensated in the SoPEC.

6.5 Deviation (rotation around Z)

This type of erroneous rotation displacement means that the nozzles at one end of the IC will print the Y-page lower than the other end of the IC. There may also be a slight increase in optical density depending on the magnitude of the rotation.

The SoPEC can compensate for this effect by providing first order continuity, although not second order continuity in the preferred embodiment. First-order continuity (in which the Y position of adjacent line ends is compensated) is achieved using the Y offset mechanism, but considering relative placement error instead of absolute. Second-order continuity (in which the slope of the lines in adjacent printing modules is at least partially matched) can be affected by applying a compensation of Y-offset based on a pixel basis. Although a person skilled in the art will have few difficulties from the timing difference that such compensation allows, the SoPEC does not compensate for it and, therefore, is not described in detail in this document.

Figure 12 shows an example in which the IC of the print head number 4 is positioned with deviation, as shown in Figure 12, while all other ICs of the print head are perfectly positioned. The deviation effect is that the left end of segment 4 of the printhead has an apparent Y-deviation of -1 line-pass with respect to segment 3, while the right end of segment 4 has an apparent deviation in And of a line-step with respect to segment 5.

To provide first-order continuity in this example, SoPEC records would be programmed so that segments 0 to 3 have a Y offset of 0, segment 4 has a Y offset of -1 and segments 5 and above have a Y offset of -2. It should be noted that the displacements in Y accumulate in this example, although segment 5 is perfectly aligned with segment 3, different deviations in Y are programmed.

It will be appreciated that a certain compensation is better than none and it is not necessary in all cases to perfectly correct the balancing and / or deviation. Partial compensation may be appropriate depending on the specific deviation. As with balancing, the correction of a deviation is particularly applicable to multi-module printheads, but can also be applied to single-module printheads.

7 Requirements for printheads

7.1 Number of colors

The printhead will be designed for 5 colors. Currently the intended use is:

(i)

 cyano

(ii)

 magenta

(iii) yellow

(iv)

 black

(v)

 infrared

However, the design methodology must be able to propose a number other than 5 if the current number of colors changes. In case of change, it would be 6 (adding fixative) or 4 (eliminating infrared).

The print head chip does not imply any particular order of the 5 color channels.

7.2 nozzle channels

The print head will contain 1280 nozzles of each color -640 nozzles of one alignment projecting even points and 640 nozzles of another alignment projecting odd points. This means that 11 link printheads are required to assemble an A4 / letter printhead.

However, the design methodology must be able to propose a number other than 1280 if you change the current number of nozzles per color. Any different length may need to be a multiple of 32 or 64 to allow the routing of the ink channels.

7.3 Nozzle separation

The printhead will be intended for 1600 dpi printing. This means that the ink droplets must be deposited on the page separated by a distance of 15,875 microns.

The distance between points of 15,875 microns together with the requirements of MEMS means that the horizontal distance between two adjacent nozzles in a single alignment (for example, projecting even points) will be 31.75 microns.

All 640 points in an odd or even color alignment are exactly aligned vertically. The alignments are projected sequentially, so that a complete alignment is projected in a small fraction (nominally one tenth) of a line time, with the projection of individual nozzles distributed within this alignment time. As a result, the stitches may end on paper with a vertical placement error of up to one tenth of the step of a dot. This is considered acceptable.

The vertical distance between alignments is adjusted based on the order of alignment projection. The projection can start with an alignment and then follow a fixed rotation. Figure 13 shows the default projection order from 1 to 10, starting at the upper even alignment. The alignments are separated by an exact number of dotted lines, plus a fraction of a dotted line that corresponds to the distance the paper will travel between alignment projection times. This allows an exact point-to-point impression of each color. The starting alignment can be varied to correct the lack of vertical alignment between chips to the nearest 0.1 pixel. The SoPEC appropriately delays the data of each alignment to allow separation and order of projection.

An additional limitation is that odd and even alignments for a given color must be placed close enough to allow them to share an ink channel. This results in the vertical separation shown in Figure 364, in which L represents a point step.

7.4 Chip Link

Multiple identical printhead chips must be able to be linked together to form a printhead effectively assembled horizontally.

While there are several possible internal arrangements, construction and assembly tolerance issues have constituted an internal arrangement of a recessed triangle (i.e., a set of alignments) of nozzles within a series of nozzle alignments, as shown in figure 14. These printheads can be displaced from each other, as shown in figure 15.

The compensation for the triangle is preferably carried out in the printhead, but if the storage requirements are too large, the triangle compensation can take place in the SoPEC. However, if the compensation is carried out in the SoPEC, it is required in the present embodiment that there be an even number of nozzles on each side of the triangle.

It will be appreciated that the triangle disposed adjacent at the end of the chip provides the minimum storage requirements in the printhead. However, when storage requirements are less critical, other forms can be used. For example, lowered alignments may take the form of a trapezoid.

The union between adjacent heads has an angle of 45 ° with respect to the upper and lower edges of the chip. The binding edge will not be straight, but will have a sawtooth profile or similar. The nominal separation between tiles is 10 microns (measured perpendicular to the edge). The SoPEC can be used to compensate for both horizontal and vertical misalignments of the print heads with a certain cost in terms of memory and / or print quality.

It should also be noted that the movement of the paper is fixed for this specific design.

7.5 Print speed

A print speed of 60 A4 pages / letter per minute is possible. The printhead will adapt to the following:

3. page length = 297 mm (A4 is the longest page length)

3. a gap between pages of 60 mm or less (the best current estimates are more or less 15 +/- 5 mm). This implies a line speed of 22,500 lines per second. It should be noted that if the page gap does not have to be taken into account in the page speed calculations, then a line speed of 20 KHz is sufficient.

Assuming that interstitium of pages is required, the printhead should be able to receive the data for a complete line during the time of the line, that is, 5 colors 1280 points 22,500 lines = 144 MHz or more (173 MHz for 6 colors ).

7.6 Pins

A global requirement is to minimize the number of pins.

The number of pins is determined primarily by the number of feed and ground pins for Vpos. There is a lower limit for this number based on average current and electromigration standards. There is also a significant impact of the routing area due to the use of fewer feed pins.

As a summary, a projection energy of 200 nJ implies approximately an average consumption of 12.5 W for 100% ink coverage or 2.5 W per chip with a 5 V supply. This would determine a minimum of 20 Vpos / Gnd pairs. However, increasing this number to about 40 pairs could save approximately 100 microns of chip height due to easier routing.

In this phase, the print head assumes 40 pairs of Vpos / Gnd plus 11 Vdd (3.3 V) pins plus 6 signal pins making a total of 97 pins per chip.

7.7 Ink supply hole

At the CMOS level, the ink supply hole for each nozzle is defined by a rectangle-shaped metal seal ring (with square corners), which measures 11 microns horizontally by 26 microns vertically. The center of each ink supply hole is directly below the center of the MEM nozzle, that is, the horizontal and vertical separation of the ink supply is the same as the separation of the corresponding nozzles.

7.8 ESD

The printhead will most likely be inserted into a print cartridge for insertion into the printer, similar to the way a laser printer toner cartridge is inserted into a laser printer.

In the home / office environment, ESD discharges up to 15 kV may occur during driving. It is not feasible to provide protection against these discharges as part of the chip, so some type of protection will be needed during handling.

The printhead chip itself will be provided for MIL-STD-883 class 1 (2 kV model for human body) that is suitable for assembly and testing in an ESD controlled environment.

7.9 EMI

There are no specific requirements for EMI currently apart from minimizing emissions as much as possible.

7.10 Active plug / unplug

It may be necessary to disassemble the cartridge (and therefore the printhead) to replace the cartridge or cause a paper jam.

There are no demands on the print head to resist an active or "hot" plug / unplug situation. This will be taken into account by the cradle and / or the electromechanical part of the cartridge.

7.11 Power sequencing

The print head has no specific requirement for the sequencing of 3.3V and 5V supply. However, there is a requirement to keep the reset (“reset”) activated (low) when applying power.

7.12 Reset (“reset”) in power situation

It will be supplied to the printhead. There are no requirements for replacement circuits in a power situation for the circuits inside the printhead.

7.13 Output voltage range All output pins (which typically go to SoPEC) will work at 3.3 Vdd + -5%.

7.14 Temperature range The CMOS of the printhead will be verified for its operation in a range of -10C to 11 10C.

7.15 Reliability and service life

The CMOS of the printhead will be provided for a minimum useful life of 10 billion projections per nozzle.

8 Physical summary

The SRM043 is an integrated CMOS and MEMS chip. MEMS structures / nozzles can project ink that has passed through the CMOS substrate through small holes made by chemical attack.

The SMR043 has nozzles arranged to create 1600 dots per inch placed with precision printing. The SRM043 has 5 colors, 1280 nozzles per color.

The SRM043 is designed to link to a similar SRM043 with perfect alignment, so that the printed image has no artifacts through the junction between the two chips.

The SRM043 contains 10 nozzle alignments arranged in the form of pairs of upper and lower alignments of 5 different inks. Paired alignments share a common ink channel at the back of the matrix. The nozzles, in one of the paired alignments are horizontally separated from each other between two point steps and are offset relative to each other.

8.1 Color layout

1600 dpi has a step of DP points 15,875 m. The unit cell of MEMS printing nozzles is 2 DP wide by 5DP (31.75m x 79.375m). To achieve 1600 dpi per color, two horizontal alignments of nozzles (1280/2) are located with a horizontal displacement of 5DP (2.5 cells). The vertical offset is 3.5DP between two alignments of the same color and 10.1DP between alignments of different color. This slope continues between colors and results in a print area that is a trapezoid, as shown in Figure 16.

Within an alignment, the nozzles are perfectly aligned vertically.

8.2 Link nozzle arrangement

For reasons of sealing the ink, an important area of silicone is required beyond the extreme nozzles of each alignment at the base of the die near the place where the chip binds to the next chip. To achieve this effect, the first nozzles of each alignment are displaced vertically DP. The data for the nozzles of the triangle must be delayed in the times of 10 lines to adapt to the vertical displacement of the triangle. The correct number of data bits at the beginning of each alignment is placed in a FIFO. FIFO output data is used alternately. The rest of the alignment data deviates from the FIFO.

9 Block diagram and summary of CMOS modules

Figure 19 shows the upper levels of the block diagram and by extension the list of interconnections of the upper layer for the print head.

The modules that comprise the CMOS of the link printhead are: 9.1 Core

The kernel contains a set of unit cells and the column shift register (columnSR).

The Unitary Cell is the base structure of the printhead consisting of a bit of the alignment data offset register, an electronic scale for double buffering of the data, the ink projection MEMS mechanism, a large transistor to activate MEMS and some doors to activate the transistor at the right time.

The column offset register is at the bottom of the set of unit cells in the core. It is used to generate synchronization for the projection of the unit cells, together with the fpg.

9.2 Triangle Delay Compensation (TDC)

The TDC module controls the loading of data in the offset logs of the core alignments.

The triangle lowered on the left side of the core impressions of the bottom 10 lower lines on the page than the volume of each alignment. This implies that the data has to be delayed by 10 times the time of a line before the projection of the ink. To minimize the overload on the print driver and to make the interface more concrete, this delay is provided on chip.

The TDC block connects to a FIFO used to store the delayed data and routes the data of the first nozzles in a specific alignment with data through the FIFO. All subsequent data is passed directly through the alignment records.

The TDC also serializes data with 8-bit width at the symbol rate of 28.8 MHz to 2-bit groups at a speed of 144 MHz, routes this data to all alignment registers and synchronously generates closed clock signals for the alignment shift register accessed.

9.3 FPG

The “Fire and Profile Generation” controls the projection sequence based on the nozzles of an alignment and a column and the amplitude of the projection pulses applied to each actuator.

Produces synchronized profile pulses for each core alignment. It also generates clock and data signals to activate the ColumnSR. The column updates, coming from the ColumnSR, the alignment profile and the data within the core are added together to project the unit cell actuators and, therefore, to inject the ink.

The FPG sequences the activation to produce an exact placement of the points, compensating the position of the print head and generating profiles of correct amplitude.

9.4 DEX

The “Data Extractor” converts the input data stream into an instruction with bit amplitude and data symbols to the CU. It acts in interface with a fully adapted Datamux to sample data presented to the chip in the optimum aspect. These data are then decoded, the symbols are aligned and deserialized and then decoded. The data and the type of symbol are passed to the figure.

9.5 CU

The "Command Unit" contains most of the control registers. The person responsible for implementing the instruction protocol and routes the control and data and clock signals to the rest of the chip, as appropriate. The CU also contains all the BIST functionality.

The CU synchronizes reset_n for the rest of the chip. The reset is eliminated synchronously, but is applied to the flip flops of the asynchronous erase pin. Projection activation is overridden with an asynchronous reset signal.

9.6 IO

The chip has a high-speed clock and LVDS data connections connected to the DEX module.

There is a reset_n input and a modal tristate / open drain output managed by the CU.

There are also a series of ground connections, VDD connections and also VPOS connections for the unit cell.

The design must not have power sequencing requirements, but requires the reset application in the power application.

The sequencing of the lack of power requires that the ESD protection of the connections be grounded, there can be no diodes between the VPOS and VDD pathways.

10 Similarly, the unit cell level translator must ensure that the PMOS switching transistor is disconnected in the event that VPOS are activated before VDD.

9.7 Normal operation

15 The normal operation of the link print head is as follows: reset (“reset”) the head program the records to control the projection sequence and parameters load data for a single print line (up to) 10 print head alignments , send a projection instruction (“FIRE”), which retains the loaded data and starts a projection cycle while the cycle

Projection 20 is running, load data for the next print line if the page has not been finished, turn to 4.

It should be noted that the separation of projection instructions ("FIRE") determines the printing speed (in lines / second). The printhead would be adjusted normally, so that a projection cycle extends to all available time between projection instructions ("FIRE").

10 Detailed description of the TDC module

10.1 TDC 10 30 Table 1. TDC 10

Signal

Drn to / from Description

say [7: 0]

entry from: CU 8 8-bit alignment data at a symbol rate (clk28)

data_valid

entry from: CU Activate for clk28 domain data

clk

entry from: IO 288 MHz clock signal

phi9

entry from: DEX Clk signal synchronization

tdc_bypass

entry from: CU Disable triangle delay compensation

ld_n

entry from: CU Start projection cycle

do [1; 0]

exit towards: core Send data to core alignment offset records

rclk [9: 0]

exit towards: core Clock signals from the core offset register alignment. Clock signals at 144 MHz, no more than one running at the same time

row [3: 0]

entry from: CU Core alignment to write to

newrow

entry from: CU The core alignment has changed, recalculate

fifo_di [1: 0]

exit to: TDC_FIFO First ascending delayed data

fifo_do [1: 0]

entry from: TDC_fifo Delayed fifteenth data

fifo_clk

exit to: TDC_fifo Fifth clock signal. Clock signal at 144 MHz, aligned to rclks

Single_r

entry from: CU Generates a single rclk event when activated

Clk

Used for core reading

10.2 Functionality

The TDC receives alignment data from the CU, partially serializes it and writes it to the head alignment of

35 print addressed at the time. It also removes the required number of bits from the beginning of the alignment and stores them in the TDC_fifo by replacing them with offset bits of the tdc_fifo. This occurs transparently to the master SoPEC.

The TDC generates a local symbol phase clock signal using phi9. This signal phase information of

40 clock, together with the data_valid level, is used to generate fifteen clock and alignment signals. These clock signals are timed, as shown in Figure 21. The precise number of clock signals fifo per alignment is shown in Table 3.

The CU indicates when the alignment addressed at the time changes. This alignment is mapped to get

45 the number of bits to pass through the FIFO and also if the number of bits of the FIFO is odd. [The current FIFO is never odd, but this has not always been the case, so the logical system remains in RTL]. A counter is charged with a total number of clocks required and then counting is allowed. When the terminal count is reached, an indicator is available. This indicator is used to indicate if the alignment data has been delayed through the FIFO or passed directly to the core. There is a single indicator of completion, so an alignment can be addressed only once for each projection cycle.

5 If the number of bits to be delayed is odd and the counter has reached the terminal count, then a bit for the core is taken from the FIFO and a bit of the byte presented at the time. The FIFO bit used is always fifo_do [0]. fifo_do [1] is ruled out in this chaos.

A tdc_bypass bit always causes the data to derive the fifteenth and pass directly to the core. This mode can be used for a print test, to unlock a nozzle and potentially if the SoPEC has to be used to compensate for the delay of the triangle.

This design allows the core to be randomized if necessary. All lines on a page must be written in the same order of alignment. Once an alignment has begun writing, it must be completed. At a minimum, sufficient symbols to fill the fifteenth fragment of the TDC must be sent for each alignment for each line. If less than 80 are sent, but a minimum of the number shown in table 3, center column, the TDC will work correctly, but errors for lesser quantity will be reported by the CU.

Despite the above, if the single_rclk input is activated, then it will be generated for the alignment indicated at the time, rclk []. This rclk can be activated in the next odd phase of clk. This rclk is a unique cycle of clk in amplitude and there is only one. There is no control of the two bits written to the kernel in this mode.

10.3 TDC FIFO

25 10.3.1 TDC FIFO IO

Table 2. TDC FIFO IO

Signal

Drn To / from Description

fifo_di [1: 0]

entry from: tdc Fifteen data entry

fifo_do [1: 0]

exit up to: tdc Fifteen data output

fifo_clk

entry from: tdc Fifth clock at 144 MHz. This clock is generated as a pulse clock signal in the TDC module

10.3.2 TDC FIFO functionality

To allow the printheads to be butt without joints, there is a section in the leftmost part of the core, in which a triangular group of nozzles, some of each alignment, is displaced downwards. This increases the linear distance between consecutive nozzles in the same logical alignment through the joint, allowing easier ink sealing between the print head and the ink distribution system.

35 It will be noted that the dimensions and shape of the lowered alignments are arbitrary, but that making them triangular and of minimal dimensions has the desirable impact of reducing the amount of memory required to retain the data in the lowered alignments.

The number of nozzles in the lowered triangle differs from each alignment and has been shown in Table 3. These nozzles will project cycles of 10 projections after inaction or rest of the alignment, with the result that the ink is aligned on the paper. with most of the alignment. To facilitate this effect, the bits to be delayed are written in a fifteenth called tdc_fifo. This delays these bits in 10 alignments.

Since the core offset records are basically 2 bits wide, the fifteenth is made

45 is also 2-bit and is synchronized at the same speed as the alignment shift registers, 144 MHz. The inventors have chosen the synchronization of both fifteenth alignments with a common clock signal for implementation. This requires the addition of some extra locations to the fifteenth if the fifteenth location number is odd for a specific alignment.

320 clock signals are generated per alignment to load a complete core alignment. The fifteenth is synchronized for a variable number of clock signals at the beginning of an alignment, as shown in table 3.

Table 3. Triangle alignments

Alignment

Nozzles in lowered triangle FIFO clock signals at the beginning of the alignment

0

4 2

one

6 3

2

12 6

3

14 7

4

twenty 10

5

22 eleven

6

28 14

7

30 fifteen

8

36 18

9

38 19

Subtotal 1

210

The triangle is lowered in 10 alignments, so 2100 flip flops are required in the TDC_fifo. This must be conformed as 2X1050. 5

10.3.4 TDC FIFO implementation

The FIFO TDC is implemented as a hard macro to minimize area requirements.

10 A list of verilog interconnections is written using flip flops specifically instantiated as examples. The flipflop used is the same as that used in the shift register. It is optimized in terms of dimensions, with approximately one third of TSMC standard flipflop being optimized in size. It has limited power and requires clock signal and clock_bar to work.

15 The design uses a repeated set of 8 columns in which the data oscillates up and down, a pair on the left and a pair on the right. These two columns are connected in the lower left to form a shift register with a width of 2 bits. The entrances and exits are all in the lower right corner.

20 This implementation facilitates a synchronized IO, with reference to a local clock signal and also allows the regular buffering of clock signals along the matrix. “Space” is used to verify the configuration and retention times are met in all cases.

The closed clock signal (“gated”) is chosen for power reasons. This clock signal is generated in the TDC

25 using a 288 MHz clock signal. The FIFO TDC can circulate data at 144 MHz and has a delay of 1050 clock signals (for a 10-alignment printhead). The fifo raises the activated edge clock signal.

10.3.5 Synchronization

30 The tdc fifo has a latency of 1050 clock signals.

Printing a smaller number than the total number of channels available in the printhead

35 It is possible to use SoPEC to send dot data to a printhead that is using less of its total complement of alignments. For example, the fixing channels (“FIXATIVE”) IR and black may be omitted from a simple, low-cost type printer. Instead of designing a new printhead that has only 3 channels, it is possible to select which channels are active in a printhead with a larger number of channels, such as the currently preferred channel version. It may be desirable to use

40 a printhead that has one or more defective nozzles in up to three alignments as a printhead (or printhead module) in a three color printer.

It would be disadvantageous to have to load empty data on each empty channel, so it is preferred to allow one or more alignments to be deactivated in the print head.

45 The printhead already has a register that allows each alignment to be activated or deactivated individually (ENABLE register) in the 0 direction. Currently, all this results in projection suppression (“firing”) for an alignment not activated .

50 To prevent the SoPEC from sending blank data for unused alignments, the functionality of these bits extends to:

one.

 jump over disabled alignments when writing the DATA_NEXT record;

2.

 force false bits in the FIFO TDC for a deactivated alignment corresponding to the number of nozzles of the lowered triangle section for said alignment. These false bits are written immediately following the writing of the first alignment to the fifteenth following a projection instruction (“firing”).

Using this arrangement, it is possible to operate a 6 color printhead as a 1 to 6 color printhead, depending on the intended mode. The mode can be provided by the printer control (SoPEC); once set, the SoPEC needs to send only dot data for the active channels of the print head.

Claims (10)

one.

Printhead module comprising a series of alignments of printhead nozzles, each alignment including a corresponding part of displaced alignment, including the displacement of each alignment part a component in a normal direction to the page width to be printed, characterized in that: the offset alignment parts of at least some of the alignments have different lengths than the offset alignment parts of at least some of the other alignments and the displaced alignment parts are arranged adjacent to one end of the head module of Print.

2.

 Printhead module according to claim 1, wherein the dimensions of the respective parts of offset alignment increase from alignment to alignment in the normal direction to the width of the page to to print.

3.

 Printhead module according to claim 1, wherein the aligned alignment parts jointly they comprise a general trapecial form, in plan.

Four.

 Printhead module according to claim 1, wherein the aligned alignment parts together they comprise a general triangular shape, in plan.

5.

Printhead module according to any of the preceding claims, wherein the module Printhead is an integrated printhead circuit.

6.

 Printhead comprising a series of printhead modules, including at least one of the printhead modules, according to any of the preceding claims.

7.

 Printhead according to claim 6, wherein the printhead modules have the same shape and configuration one another and are arranged, end to end, across the intended width of Print.

8.

 Printhead according to claim 6 or 7, wherein the printhead modules define jointly a page width printhead.

9.

 Printer driver to supply data to a printhead module, according to any of the claims 1 to 5, the printer driver being configured to control order and synchronization of the data supplied to the printhead module, so that the aligned alignment parts they are compensated during printing with the printhead module.

10.

 Inkjet printer comprising the printhead, according to any of the claims 6 to 8, and the printer driver according to claim 9.