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EP0996981A1 - High-voltage edge termination for planar structures - Google Patents

High-voltage edge termination for planar structures

Info

Publication number
EP0996981A1
EP0996981A1 EP99917767A EP99917767A EP0996981A1 EP 0996981 A1 EP0996981 A1 EP 0996981A1 EP 99917767 A EP99917767 A EP 99917767A EP 99917767 A EP99917767 A EP 99917767A EP 0996981 A1 EP0996981 A1 EP 0996981A1
Authority
EP
European Patent Office
Prior art keywords
voltage
edge termination
floating
semiconductor body
termination according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99917767A
Other languages
German (de)
French (fr)
Inventor
Jenö Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0996981A1 publication Critical patent/EP0996981A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

Definitions

  • the present invention relates to a high-voltage edge termination for planar structures, with a semiconductor body of the one conduction type, on the edge region of which at least one field plate separated from it by an insulator layer is provided.
  • a long-established procedure to increase the breakdown strength of the edge area of semiconductor components provides for the use of field plates.
  • Other measures to increase the dielectric strength of edge structures of semiconductor components relate to the use of protective rings, which can possibly be connected to the field plates, the avoidance of pn junctions with a large curvature in order to prevent field strength peaks, etc. (cf. e.g. also EP 37 115 A).
  • the present invention is also based on the object of creating a high-voltage edge termination for planar structures with which the breakdown strength of semiconductor components in their edge region can be further improved.
  • This object is achieved according to the invention in a high-voltage edge termination for planar structures of the type mentioned at the outset in that floating (or potential-free) regions of the second conduction type are provided in the edge region of the semiconductor body, the spacing of which from one another is dimensioned such that even one in Breakdown voltage of the semiconductor body to the floating areas small applied voltage the zones between the floating areas are cleared.
  • the floating areas which can be provided in a plurality of essentially parallel planes in an island-like or also contiguously wedge-shaped manner with a thickness that becomes narrower towards the edge, have the effect when the voltage is applied as if the edge area itself were undoped. This means that a breakthrough no longer occurs in the edge region, but rather in the middle of a semiconductor component for the first time.
  • island-like regions of the second conduction type When island-like regions of the second conduction type are used, they can have an essentially identical shape, for example spherical or ellipsoidal. However, it is also possible in the same way that the floating areas are designed differently. Also, the floating areas do not need to be completely cleared out when voltage is applied; this applies in particular to voltages which are clearly below the breakdown voltage in the central region of the semiconductor component.
  • the island-like floating areas can also be designed in a coherent manner. They then have the shape of a network or grid. Furthermore, the island-like areas can also extend into the central region of the semiconductor body of the semiconductor component.
  • the wedge-shaped shape of the floating areas it is also possible to provide them with the same layer thickness and to have the area doping decrease in the direction of the edge from, for example, 10 12 cm -2 to 0. Such weaker doping towards the edge can also be provided for island-like floating areas. In the same way, it is also possible to have the number of the floating regions decrease towards the edge with the same or even weakening doping. It is therefore essential that the amount of doping introduced by the floating regions decreases towards the edge of the semiconductor component.
  • an injector or a Schottky contact can be provided which is capable of injecting weak charge carriers of the second conduction type in order to prevent the current path from being completely stalled when the space charge zones are emptied in the switched-on state.
  • the field plate provided in the insulator layer can be designed in such a way that its distance from the semiconductor body gradually or continuously increases as it approaches the edge of the semiconductor component. It is also possible to provide step-shaped field plates made of several materials and these 4 if necessary to connect with protective rings. If the one line type is the n line type, the guard rings are formed by p-type guard rings.
  • the floating areas are in several planes that are essentially parallel to one another, when a voltage is applied to the semiconductor component, for example between anode and cathode in an n-conducting semiconductor body, the space charge zone in the semiconductor region between the cathode-side surface of the semiconductor body and the first level becomes first floating areas cleared. If the space charge zone reaches the floating areas, the potential remains at the value V pth then assumed. The space charge zone then forms between the first level of the floating regions and the second level. If the second level is reached by the space charge zone, the potential remains at a value of approximately 2 V pth , provided that the individual levels are essentially equally spaced from one another.
  • the entire edge region is successively cleared out, so that the breakdown voltage can be increased to approximately N + 1 times the normal value determined by the doping, if it is assumed that the number of levels is given by N.
  • an injector which may be present serves as a hole supplier for the discharge of the p-type floating regions in the switched-on state.
  • Suitable dimensions for the floating areas are a diameter of the spherical floating areas of approximately 5 ⁇ m with a mutual spacing of likewise approximately 5 ⁇ m, the surface area 5 tion in the floating areas can be around 10 12 to 10 13 cm " '.
  • FIG. 1 shows a first embodiment of the edge closure according to the invention
  • FIG. 2 shows a second exemplary embodiment of the edge closure according to the invention
  • FIG. 3 shows a third exemplary embodiment of the edge closure according to the invention
  • Fig. 4 shows the course of field lines in a fourth
  • FIG. 5 shows a fifth exemplary embodiment of the edge termination according to the invention for a super high-voltage IGBT
  • FIG. 6 shows a sixth exemplary embodiment of the edge termination according to the invention for a super high-voltage IGBT
  • Fig. 7 shows a seventh embodiment of the edge termination according to the invention for a high-voltage field effect transistor with injector and 8 shows an eighth exemplary embodiment of the edge termination according to the invention for a high-voltage field-effect transistor with an injector.
  • a first n-type epitaxial layer 2 with a doping concentration i, a second n-type epitaxial layer 3 with a doping concentration n 2 and a third n-type epitaxial layer 4 are located in succession on an n-type semiconductor substrate 1 with a doping concentration n 0 with a doping concentration n 3 .
  • island-like p-type regions 5 are embedded, the doping of which is in each case before Application of the subsequent epitaxial layer is introduced.
  • These p-type regions 5 can optionally also be designed contiguously in the manner of a grid or network. In any case, these areas 5 are present in three levels in the present exemplary embodiment. 7
  • the substrate 1 is connected to a cathode electrode K, to which a voltage + U is applied.
  • P-type protective rings 6 are embedded in the third epitaxial layer 4, each of which is connected to field plates 7 made of polycrystalline silicon.
  • the outermost field plate 7 can be at the same potential with the third epitaxial layer 4.
  • a p-type anode zone 8 is connected to an anode electrode A.
  • a space charge zone first forms between the surface of the semiconductor body adjoining an insulator layer 9 made of silicon dioxide, i.e. the surface of the third epitaxial layer 4 and the island-like regions 5 between the second epitaxial Layer 2 and the third epitaxial layer 4.
  • V pth the potential of the island-like regions 5 of the top level remains at the value V pth .
  • the space charge zone then forms between the regions 5 of the third level and the regions 5 of the second level, that is to say the regions which lie between the epitaxial layers 2 and 3. If the second level is reached, the potential remains at about 2 V ptri etc.
  • the diameters of the floating regions 5 can be approximately 5 ⁇ m, while their spacing from one another in the same plane can also be 5 ⁇ m.
  • the area doping of the floating areas is about 10 12 to 10 13 cm -3 . 8th
  • Fig. 2 shows a similar embodiment as Fig. 1, which differs from the latter only in that only one field plate 17 is used together with a channel or channel stopper 16 which is connected to the potential of the semiconductor body.
  • FIG. 3 shows an exemplary embodiment of the edge termination according to the invention with an edge 11 and wedge-shaped, floating p-conducting regions 15, which are arranged here in two planes.
  • the space charge zones build up here in the same way between the individual levels, as was explained above with reference to FIG. 1.
  • a cathode contact 14 can be made of aluminum and be weakly injecting in order to act as a hole supplier for the discharge of the p-type regions 15 in the switched-on state.
  • a lattice-like structure of floating regions 5 can continue toward the center of the semiconductor component in the planes formed by the regions 15 (not shown in FIG. 3). The same applies to the following examples.
  • the channel stopper 16, which is also provided in the embodiment 3, can optionally be omitted.
  • FIG. 4 shows, as a further exemplary embodiment, an edge termination with a wedge-shaped region 15 in only one plane, the potential line profile (equi- 9 potential lines) is shown, which occurs after a voltage is applied.
  • This can be a voltage value of, for example, 2000 V.
  • FIG. 5 shows, as a further exemplary embodiment, a high-voltage edge termination for a super-high-voltage IGBT.
  • a high-voltage edge termination for a super-high-voltage IGBT instead of the wedge-shaped p-type regions 15, floating p-type layer-like regions 25 are provided here, the doping of which decreases towards the edge 11.
  • the doping of these areas 25 can decrease from an area doping of approximately 10 13 to 10 12 cm -2 from their right edge (cf. dashed line 24) to a value 0 at the edge 11.
  • the layers 25 can continue towards the component side, that is to say opposite to the edge 11, as regions 5, which can optionally be connected to one another in the form of a grid.
  • FIG. 5 also shows a source metallization 23, a gate electrode 22 made of polycrystalline silicon, polycrystalline silicon layers 21, n-type source regions 20 and p-type regions 19.
  • a drain contact D with a p-type layer 18 is provided.
  • FIG. 7 and 8 show two exemplary embodiments of the high-voltage edge termination according to the invention for a high-voltage field-effect transistor with an injector.
  • These exemplary embodiments are similar to the exemplary embodiment in FIG. 3 and have an inclined field plate 17 in the insulator layer 9, wherein a channel stopper 16 can also optionally be provided.
  • wedge-shaped p-type regions 15 are provided here, which merge into island-like regions 5 in the central region.
  • a source contact S is connected to n-type regions 26 and p-type regions 27 and is grounded.
  • a drain electrode D is connected to the semiconductor substrate 1 via an aluminum contact 14.
  • a p-type injector layer 28 is also present here, which reinforces the weakly injecting injector of the exemplary embodiment in FIG. 3. If necessary, a Schottky contact can also be provided instead of the p-type layer 28. Part of the aluminum contact 14 is still covered by an insulator layer 29.
  • FIG. 8 differs from the embodiment of FIG. 7 in that the insulator layer 29 is omitted here. Instead of the p-type layer 28, a Schottky contact can also be provided in the exemplary embodiment in FIG. 8.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to a high-voltage edge termination for planar structures which comprise a semiconductor body (1 to 4) of a first conduction type. At least one of the magnetoresistors (7, 17) which is separated from the semiconductor body by an insulating layer (9) is provided on the same in the edge area thereof. Floating regions (5, 15, 25) of the second conduction type are provided in the edge area of the semiconductor body (1 to 4). The floating regions are separated from one another in such a way that the zones between the floating regions (5, 15, 25) are cleared when a voltage which is lower in comparison to the breakdown voltage of the semiconductor body (1 to 4) is applied to the floating regions (5, 15, 25).

Description

1 1
Beschreibungdescription
Hochvolt-Randabschluß für PlanarstrukturenHigh-voltage edge seal for planar structures
Die vorliegende Erfindung betrifft einen Hochvolt-Randabschluß für Planarstrukturen, mit einem Halbleiterkorper des einen Leitungstyps, auf dem in dessen Randbereich wenigstens eine von diesem durch eine Isolatorschicht getrennte Feldplatte vorgesehen ist.The present invention relates to a high-voltage edge termination for planar structures, with a semiconductor body of the one conduction type, on the edge region of which at least one field plate separated from it by an insulator layer is provided.
Bereits seit Jahrzehnten werden /Anstrengungen unternommen, um bei Halbleiterbauelementen, wie beispielsweise Dioden, den im Halbleiterkorper herrschenden Feldstärkenverlauf so zu gestalten, daß ein Durchbruch nicht im Randbereich, sondern in der Hauptstruktur oder - bei integrierten /Anordnungen - im Zellenfeld erfolgt. Denn die Randstruktur ist infolge der dort zwangsläufig herrschenden Krümmungen des elektrischen Feldes besonders durchbruchsanfällig, so daß mit der Verlagerung des Durchbruches in die Hauptstruktur bzw. das Zellenfeld gleichzeitig die Durchbruchsfestigkeit des Halbleiterbauelementes erhöht wird.For decades, efforts have been made to design the field strength curve in the semiconductor body in the case of semiconductor components, such as diodes, in such a way that a breakthrough does not occur in the edge area, but in the main structure or - in the case of integrated / arrangements - in the cell field. Because the edge structure is particularly susceptible to breakthrough due to the inevitable curvature of the electric field there, so that the breakdown strength of the semiconductor component is increased at the same time as the opening is shifted into the main structure or the cell field.
Ein seit langem gängiges Vorgehen zur Steigerung der Durchbruchsfestigkeit des Randbereiches von Halbleiterbauelementen sieht den Einsatz von Feldplatten vor. /Andere Maßnahmen zur Erhöhung der Spannungsfestigkeit von Randstrukturen von Halbleiterbauelementen betreffen die Verwendung von Schutzringen, die gegebenenfalls mit den Feldplatten verbunden sein können, die Vermeidung von pn-Übergängen mit großer Krümmung, um Feldstärkespitzen zu verhindern, usw. (vgl. z.B. auch EP 37 115 A) .A long-established procedure to increase the breakdown strength of the edge area of semiconductor components provides for the use of field plates. / Other measures to increase the dielectric strength of edge structures of semiconductor components relate to the use of protective rings, which can possibly be connected to the field plates, the avoidance of pn junctions with a large curvature in order to prevent field strength peaks, etc. (cf. e.g. also EP 37 115 A).
Obwohl so an der Erhöhung der Durchbruchsfestigkeit des Randbereiches von Halbleiterbauelementen seit langem intensiv gearbeitet wird, liegen bisher immer noch keine vollständig be- 2 friedigenden Ergebnisse vor. Noch immer wird darüber nachgedacht, wie gegebenenfalls die Durchbruchsfestigkeit von Randstrukturen von Halbleiterbauelementen in einfacher Weise gesteigert werden kann.Although intensive work has been carried out to increase the breakdown strength of the edge area of semiconductor components for a long time, there are still no fully 2 peaceful results. It is still being considered how, if necessary, the breakdown strength of edge structures of semiconductor components can be increased in a simple manner.
So liegt auch der vorliegenden Erfindung die Aufgabe zugrunde, einen Hochvolt-Randabschluß für Planarstrukturen zu schaffen, mit dem die Durchbruchsfestigkeit von Halbleiterbauelementen in deren Randbereich weiter verbessert werden kann.The present invention is also based on the object of creating a high-voltage edge termination for planar structures with which the breakdown strength of semiconductor components in their edge region can be further improved.
Diese Aufgabe wird bei einem Hochvolt-Randabschluß für Planarstrukturen der eingangs genannten Art erfindungsgemäß dadurch gelöst, daß im Randbereich des Halbleiterkorpers floatende (bzw. potentialfreie) Gebiete des zweiten Leitungstyps vorgesehen sind, deren Abstand voneinander derart bemessen ist, daß bereits bei einer im Vergleich zur Durchbruchsspannung des Halbleiterkorpers zu den floatenden Gebieten kleinen anliegenden Spannung die Zonen zwischen den floatenden Gebieten ausgeräumt sind.This object is achieved according to the invention in a high-voltage edge termination for planar structures of the type mentioned at the outset in that floating (or potential-free) regions of the second conduction type are provided in the edge region of the semiconductor body, the spacing of which from one another is dimensioned such that even one in Breakdown voltage of the semiconductor body to the floating areas small applied voltage the zones between the floating areas are cleared.
Die floatenden Gebiete, die in mehreren, im wesentlichen zueinander parallelen Ebenen inselartig oder auch zusammenhängend keilförmig mit zum Rand hin schmäler werdenden Dicke vorgesehen sein können, wirken sich bei anliegender Spannung so aus, als ob der Randbereich selbst undotiert wäre. Dies führt dazu, daß ein Durchbruch nicht mehr im Randbereich, sondern vielmehr in der Mitte eines Halbleiterbauelementes erstmals auftritt.The floating areas, which can be provided in a plurality of essentially parallel planes in an island-like or also contiguously wedge-shaped manner with a thickness that becomes narrower towards the edge, have the effect when the voltage is applied as if the edge area itself were undoped. This means that a breakthrough no longer occurs in the edge region, but rather in the middle of a semiconductor component for the first time.
Bei der Verwendung von inselartigen Gebieten des zweiten Leitungstyps können diese eine im wesentlichen gleiche Gestalt, beispielsweise kugelförmig oder ellipsoidförmig, haben. Es ist aber in gleicher Weise auch möglich, daß die floatenden Gebiete unterschiedlich gestaltet sind. Auch brauchen die floatenden Gebiete bei anliegender Spannung nicht vollständig ausgeräumt zu werden; dies gilt insbesondere für Spannungen, die deutlich unterhalb der Durchbruchsspannung im Mittenbereich des Halbleiterbauelementes liegen.When island-like regions of the second conduction type are used, they can have an essentially identical shape, for example spherical or ellipsoidal. However, it is also possible in the same way that the floating areas are designed differently. Also, the floating areas do not need to be completely cleared out when voltage is applied; this applies in particular to voltages which are clearly below the breakdown voltage in the central region of the semiconductor component.
Die inselartigen floatenden Gebiete können gegebenenfalls auch zusammenhängend gestaltet werden. Sie haben dann die Form eines Netzes oder Gitters. Weiterhin können sich die inselartigen Gebiete auch bis in den Mittenbereich des Halbleiterkorpers des Halbleiterbauelementes erstrecken.If necessary, the island-like floating areas can also be designed in a coherent manner. They then have the shape of a network or grid. Furthermore, the island-like areas can also extend into the central region of the semiconductor body of the semiconductor component.
Es ist auch möglich, anstelle der keilförmigen Gestalt der floatenden Gebiete diese mit gleicher Schichtdicke auszustatten und dafür die Flächendotierung in Richtung auf den Rand hin von beispielsweise 1012 cm-2 bis auf 0 abnehmen zu lassen. Eine solche schwächere Dotierung in Richtung auf den Rand hin kann auch bei inselartigen floatenden Gebieten vorgesehen werden. In gleicher Weise ist es auch möglich, die Anzahl der floatenden Gebiete bei gleicher oder auch schwächer werdenden Dotierung zum Rand hin abnehmen zu lassen. Wesentlich ist also, daß die durch die floatenden Gebiete eingebrachte Dotierungsmenge zum Rand des Halbleiterbauelementes hin abnimmt.Instead of the wedge-shaped shape of the floating areas, it is also possible to provide them with the same layer thickness and to have the area doping decrease in the direction of the edge from, for example, 10 12 cm -2 to 0. Such weaker doping towards the edge can also be provided for island-like floating areas. In the same way, it is also possible to have the number of the floating regions decrease towards the edge with the same or even weakening doping. It is therefore essential that the amount of doping introduced by the floating regions decreases towards the edge of the semiconductor component.
Gegebenenfalls kann noch ein Injektor oder ein Schottky-Kon- takt vorgesehen werden, der in der Lage ist, schwach Ladungsträger des zweiten Leitungstyps zu injizieren, um so eine vollständige Abwürgung des Strompfades bei ausgeleerten Raumladungszonen im eingeschalteten Zustand zu verhindern.If necessary, an injector or a Schottky contact can be provided which is capable of injecting weak charge carriers of the second conduction type in order to prevent the current path from being completely stalled when the space charge zones are emptied in the switched-on state.
Die in der Isolatorschicht vorgesehene Feldplatte kann so gestaltet sein, daß deren Abstand vom Halbleiterkorper mit nnäherung an den Rand des Halbleiterbauelementes stufenweise oder stetig größer wird. Ebenso ist es möglich, stufenförmige Feldplatten aus mehreren Materialien vorzusehen und diese ge- 4 gebenenfalls mit Schutzringen zu verbinden. Wenn der eine Leitungstyp der n-Leitungstyp ist, so werden die Schutzringe durch p-leitende Schutzringe gebildet.The field plate provided in the insulator layer can be designed in such a way that its distance from the semiconductor body gradually or continuously increases as it approaches the edge of the semiconductor component. It is also possible to provide step-shaped field plates made of several materials and these 4 if necessary to connect with protective rings. If the one line type is the n line type, the guard rings are formed by p-type guard rings.
Liegen die floatenden Gebiete in mehreren, im wesentlichen zueinander parallelen Ebenen vor, so wird bei Anlegen einer Spannung an das Halbleiterbauelement beispielsweise zwischen Anode und Kathode bei einem n-leitendem Halbleiterkorper zuerst die Raumladungszone im Halbleiterbereich zwischen der kathodenseitigen Oberfläche des Halbleiterkorpers und der ersten Ebene der floatenden Gebiete ausgeräumt. Erreicht die Raumladungszone die floatenden Gebiete, so bleibt das Potential auf dem dann eingenommenen Wert Vpth stehen. Danach bildet sich die Raumladungszone zwischen der ersten Ebene der floatenden Gebiete und der zweiten Ebene aus. Wird die zweite Ebene von der Raumladungszone erreicht, so bleibt das Potential auf einem Wert von etwa 2 Vpth stehen, sofern die einzelnen Ebenen im wesentlichen gleich voneinander beabstandet sind.If the floating areas are in several planes that are essentially parallel to one another, when a voltage is applied to the semiconductor component, for example between anode and cathode in an n-conducting semiconductor body, the space charge zone in the semiconductor region between the cathode-side surface of the semiconductor body and the first level becomes first floating areas cleared. If the space charge zone reaches the floating areas, the potential remains at the value V pth then assumed. The space charge zone then forms between the first level of the floating regions and the second level. If the second level is reached by the space charge zone, the potential remains at a value of approximately 2 V pth , provided that the individual levels are essentially equally spaced from one another.
Auf diese Weise wird der gesamte Randbereich nacheinander ausgeräumt, so daß die DurchbruchsSpannung auf etwa das N+l- fache gegenüber dem von der Dotierung bestimmten Normalwert erhöht werden kann, wenn angenommen wird, daß die Anzahl der Ebenen durch N gegeben ist.In this way, the entire edge region is successively cleared out, so that the breakdown voltage can be increased to approximately N + 1 times the normal value determined by the doping, if it is assumed that the number of levels is given by N.
Ein gegebenenfalls vorhandener Injektor dient bei n-leitendem Halbleiterkorper als Löcherlieferant für die Entladung der p- leitenden floatenden Gebiete im Einschaltzustand.In the case of an n-type semiconductor body, an injector which may be present serves as a hole supplier for the discharge of the p-type floating regions in the switched-on state.
Geeignete Abmessungen für die floatenden Gebiete sind, wenn diese inselartig gestaltet sind, ein Durchmesser der kugelförmigen floatenden Gebiete von etwa 5 um bei einem gegenseitigen Abstand von ebenfalls etwa 5 um, wobei die Flächendo- 5 tierung in den floatenden Gebieten bei etwa 1012 bis 1013 cm"' liegen kann.Suitable dimensions for the floating areas, if they are designed in an island-like manner, are a diameter of the spherical floating areas of approximately 5 μm with a mutual spacing of likewise approximately 5 μm, the surface area 5 tion in the floating areas can be around 10 12 to 10 13 cm " '.
Der erfindungsgemäße Randabschluß ist in vorteilhafter Weise beispielsweise bei Super-Hochvolt-IGBTs (IGBT = Bipolartransistor mit isoliertem Gate) oder Hochvolt-Feldeffektransisto- ren usw. einsetzbar.The edge termination according to the invention can advantageously be used, for example, in the case of super-high-voltage IGBTs (IGBT = bipolar transistor with insulated gate) or high-voltage field-effect transistors, etc.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:
Fig. 1 ein erstes Ausführungsbeispiel des erfindungsgemäßen Randabschlusses,1 shows a first embodiment of the edge closure according to the invention,
Fig. 2 ein zweites Ausführungsbeispiel des erfin- dungsgemäßen Randabschlusses,2 shows a second exemplary embodiment of the edge closure according to the invention,
Fig. 3 ein drittes Ausführungsbeispiel des erfindungsgemäßen Randabschlusses,3 shows a third exemplary embodiment of the edge closure according to the invention,
Fig. 4 den Verlauf von Feldlinien bei einem viertenFig. 4 shows the course of field lines in a fourth
Ausführungsbeispiel des erfindungsgemäßen Randabschlusses,Embodiment of the edge closure according to the invention,
Fig. 5 ein fünftes Ausführungsbeispiel des erfindungsgemäßen Randabschlusses für einen Super- Hochvolt-IGBT,5 shows a fifth exemplary embodiment of the edge termination according to the invention for a super high-voltage IGBT,
Fig. 6 ein sechstes Ausführungsbeispiel des erfindungsgemäßen Randabschlusses für einen Super- Hochvolt-IGBT,6 shows a sixth exemplary embodiment of the edge termination according to the invention for a super high-voltage IGBT,
Fig. 7 ein siebentes Ausführungsbeispiel des erfindungsgemäßen Randabschlusses für einen Hochvolt-Feldeffekttransistor mit Injektor und Fig. 8 ein achtes Ausführungsbeispiel des erfindungsgemäßen Randabschlusses für einen Hochvolt-Feldeffekttransistor mit Injektor.Fig. 7 shows a seventh embodiment of the edge termination according to the invention for a high-voltage field effect transistor with injector and 8 shows an eighth exemplary embodiment of the edge termination according to the invention for a high-voltage field-effect transistor with an injector.
Obwohl die Figuren an sich Schnittdarstellungen zeigen, sind zur besseren Übersichtlichkeit Schraffuren der einzelnen Halbleiterbereiche bzw. Metallisierungen usw. teilweise weggelassen. Auch werden in den Figuren für einander entsprechende Bauteile jeweils die gleichen Bezugszeichen verwendet.Although the figures themselves show sectional representations, hatching of the individual semiconductor regions or metallizations etc. has been partially omitted for better clarity. The same reference numerals are also used in the figures for corresponding components.
Fig. 1 zeigt ein erstes Ausführungsbeispiel des erfindungsgemäßen Randabschlusses, wobei hier - wie auch in den übrigen Figuren - auf der linken Seite der Randbereich und auf der rechten Seite der Bereich des eigentlichen Bauelementes, auch Zellenfeld genannt, gelegen ist. Auf einem n-leitenden Halbleitersubstrat 1 mit einer Dotierungskonzentration n0 befinden sich nacheinander eine erste n-leitende epitaktische Schicht 2 mit einer Dotierungskonzentration i, eine zweite n-leitende epitaktische Schicht 3 mit einer Dotierungskonzentration n2 und eine dritte n-leitende epitaktische Schicht 4 mit einer Dotierungskonzentration n3. Zwischen dem Halbleitersubstrat 1 und der ersten epitaktischen Schicht 2, zwischen der ersten epitaktischen Schicht 2 und der zweiten epitaktischen Schicht 3 sowie zwischen der zweiten epitaktischen Schicht 3 und der dritten epitaktischen Schicht 4 sind jeweils inselartige p-leitende Gebiete 5 eingebettet, deren Dotierung jeweils vor Aufbringen der nachfolgenden epitaktischen Schicht eingebracht wird. Diese p-leitenden Gebiete 5 können gegebenenfalls auch zusammenhängend nach der Art eines Gitters oder Netzes gestaltet sein. Jedenfalls liegen im vorliegenden Ausführungsbeispiel diese Gebiete 5 in drei Ebenen vor. 71 shows a first exemplary embodiment of the edge termination according to the invention, with the edge region being located on the left-hand side and, as in the other figures, the region of the actual component, also called the cell field, on the right-hand side. A first n-type epitaxial layer 2 with a doping concentration i, a second n-type epitaxial layer 3 with a doping concentration n 2 and a third n-type epitaxial layer 4 are located in succession on an n-type semiconductor substrate 1 with a doping concentration n 0 with a doping concentration n 3 . Between the semiconductor substrate 1 and the first epitaxial layer 2, between the first epitaxial layer 2 and the second epitaxial layer 3, and between the second epitaxial layer 3 and the third epitaxial layer 4, island-like p-type regions 5 are embedded, the doping of which is in each case before Application of the subsequent epitaxial layer is introduced. These p-type regions 5 can optionally also be designed contiguously in the manner of a grid or network. In any case, these areas 5 are present in three levels in the present exemplary embodiment. 7
Das Substrat 1 ist mit einer Kathodenelektrode K verbunden, an der eine Spannung +U liegt. In die dritte epitaktische Schicht 4 sind p-leitende Schutzringe 6 eingebettet, die jeweils mit aus polykristallinem Silizium bestehenden Feldplatten 7 verbunden sind. Die äußerste Feldplatte 7 kann dabei mit der dritten epitaktischen Schicht 4 auf gleichem Potential liegen. Schließlich ist noch eine p-leitende Anodenzone 8 mit einer Anodenelektrode A verbunden.The substrate 1 is connected to a cathode electrode K, to which a voltage + U is applied. P-type protective rings 6 are embedded in the third epitaxial layer 4, each of which is connected to field plates 7 made of polycrystalline silicon. The outermost field plate 7 can be at the same potential with the third epitaxial layer 4. Finally, a p-type anode zone 8 is connected to an anode electrode A.
Wird bei dieser Anordnung eine Spannung zwischen Anode A und Kathode K gelegt, so bildet sich eine Raumladungszone zuerst zwischen der an eine Isolatorschicht 9 aus Siliziumdioxid angrenzenden Oberfläche des Halbleiterkorpers, also der Oberfläche der dritten epitaktischen Schicht 4 und den inselartigen Gebieten 5 zwischen der zweiten epitaktischen Schicht 2 und der dritten epitaktischen Schicht 4 aus. Wenn die Raumladungszone die floatenden Gebiete 5 dieser obersten Ebene bei einer Spannung Vpth erreicht, so bleibt das Potential der inselartigen Gebiete 5 der obersten Ebene auf dem Wert Vpth stehen. Danach bildet sich die Raumladungszone zwischen den Gebieten 5 der dritten Ebene und den Gebieten 5 der zweiten Ebene, also den Gebieten, die zwischen den epitaktischen Schichten 2 und 3 liegen. Wird die zweite Ebene erreicht, dann bleibt das Potential bei etwa 2 Vptri stehen usw.If a voltage is applied between anode A and cathode K in this arrangement, a space charge zone first forms between the surface of the semiconductor body adjoining an insulator layer 9 made of silicon dioxide, i.e. the surface of the third epitaxial layer 4 and the island-like regions 5 between the second epitaxial Layer 2 and the third epitaxial layer 4. When the space charge zone reaches the floating regions 5 of this top level at a voltage V pth , the potential of the island-like regions 5 of the top level remains at the value V pth . The space charge zone then forms between the regions 5 of the third level and the regions 5 of the second level, that is to say the regions which lie between the epitaxial layers 2 and 3. If the second level is reached, the potential remains at about 2 V ptri etc.
Auf diese Weise wird die gesamte Randstruktur ausgeräumt, so daß dort die DurchbruchsSpannung bei drei Ebenen um etwa das vierfache erhöht ist.In this way, the entire edge structure is cleared out, so that the breakdown voltage is increased about four times at three levels.
Die Durchmesser der floatenden Gebiete 5 können etwa 5 um betragen, während deren Abstand voneinander in der gleichen Ebene ebenfalls 5 um sein kann. Die Flächendotierung der floatenden Gebiete liegt bei etwa 1012 bis 1013 cm-3. 8The diameters of the floating regions 5 can be approximately 5 µm, while their spacing from one another in the same plane can also be 5 µm. The area doping of the floating areas is about 10 12 to 10 13 cm -3 . 8th
Gegebenenfalls ist es auch möglich, die floatenden Gebiete 5 zu der Mittenstruktur des Halbleiterbauelementes, also in den Figuren zur rechten Seite hin, fortzusetzen.If necessary, it is also possible to continue the floating regions 5 to the center structure of the semiconductor component, that is to say to the right in the figures.
Fig. 2 zeigt ein ähnliches Ausführungsbeispiel wie Fig. 1, das sich von letzterem nur dadurch unterscheidet, daß nur eine Feldplatte 17 zusammen mit einem Kanal- bzw. Channel-Stopper 16 verwendet wird, der an das Potential des Halbleiterkorpers angeschlossen ist.Fig. 2 shows a similar embodiment as Fig. 1, which differs from the latter only in that only one field plate 17 is used together with a channel or channel stopper 16 which is connected to the potential of the semiconductor body.
Fig. 3 zeigt ein Ausführungsbeispiel des erfindungsgemäßen Randabschlusses mit einem Rand 11 und keilförmigen, floatenden p-leitenden Gebieten 15, die hier in zwei Ebenen angeordnet sind. Die Raumladungszonen bauen sich hier in gleicher Weise zwischen den einzelnen Ebenen auf, wie dies oben anhand der Fig. 1 erläutert wurde.3 shows an exemplary embodiment of the edge termination according to the invention with an edge 11 and wedge-shaped, floating p-conducting regions 15, which are arranged here in two planes. The space charge zones build up here in the same way between the individual levels, as was explained above with reference to FIG. 1.
Ein Kathodenkontakt 14 kann aus Aluminium bestehen und schwach injizierend sein, um als Löcherlieferant für die Entladung der p-leitenden Gebiete 15 im Einschaltzustand zu wirken.A cathode contact 14 can be made of aluminum and be weakly injecting in order to act as a hole supplier for the discharge of the p-type regions 15 in the switched-on state.
Ahnlich wie bei den Ausführungsbeispielen der Fig. 1 und 2 kann sich in den durch die Gebiete 15 gebildeten Ebenen eine gitterartige Struktur von floatenden Gebiete 5 zur Mitte des Halbleiterbauelementes hin fortsetzen (in Fig. 3 nicht gezeigt) . Ahnliches gilt auch für die folgenden Ausführungsbei- spiele .Similar to the exemplary embodiments in FIGS. 1 and 2, a lattice-like structure of floating regions 5 can continue toward the center of the semiconductor component in the planes formed by the regions 15 (not shown in FIG. 3). The same applies to the following examples.
Der Kanal-Stopper 16, der auch beim Ausführungsbeispiel 3 vorgesehen ist, kann gegebenenfalls weggelassen werden.The channel stopper 16, which is also provided in the embodiment 3, can optionally be omitted.
Fig. 4 zeigt als weiteres Ausführungsbeispiel einen Randabschluß mit einem keilförmigen Gebiet 15 in nur einer Ebene, wobei hier zusätzlich noch der Potentiallinienverlauf (Äqui- 9 potentiallinien) dargestellt ist, der sich nach Anlegen einer Spannung einstellt. Dies kann ein Spannungswert von beispielsweise 2000 V sein.4 shows, as a further exemplary embodiment, an edge termination with a wedge-shaped region 15 in only one plane, the potential line profile (equi- 9 potential lines) is shown, which occurs after a voltage is applied. This can be a voltage value of, for example, 2000 V.
Aus der Fig. 4 ist zu ersehen, daß die Potentiallinien weitgehend senkrecht zur Oberfläche verlaufen, so daß im Randbereich ein Durchbruch nicht auftritt.From Fig. 4 it can be seen that the potential lines run largely perpendicular to the surface, so that a breakthrough does not occur in the edge area.
Fig. 5 zeigt als weiteres Ausführungsbeispiel einen Hochvolt- Randabschluß für einen Super-Hochvolt-IGBT. Anstelle der keilförmigen p-leitenden Gebiete 15 sind hier floatende p- leitende schichtförmige Gebiete 25 vorgesehen, deren Dotierung zum Rand 11 hin abnimmt. So kann die Dotierung dieser Gebiete 25 von einer Flächendotierung von etwa 1013 bis 1012 cm-2 von ihrem rechten Rand aus (vgl. Strichlinie 24) bis auf einen Wert 0 am Rand 11 sinken.5 shows, as a further exemplary embodiment, a high-voltage edge termination for a super-high-voltage IGBT. Instead of the wedge-shaped p-type regions 15, floating p-type layer-like regions 25 are provided here, the doping of which decreases towards the edge 11. Thus, the doping of these areas 25 can decrease from an area doping of approximately 10 13 to 10 12 cm -2 from their right edge (cf. dashed line 24) to a value 0 at the edge 11.
Die Schichten 25 können sich zur Bauelementeseite hin, also entgegengesetzt zum Rand 11, inselartig als Gebiete 5 fortsetzen, die gegebenenfalls in der Form eines Gitters miteinander verbunden sein können.The layers 25 can continue towards the component side, that is to say opposite to the edge 11, as regions 5, which can optionally be connected to one another in the form of a grid.
Fig. 5 zeigt noch eine Sourcemetallisierung 23, eine Gateelektrode 22 aus polykristallinem Silizium, polykristalline Siliziumschichten 21, n-leitende Sourcebereiche 20 und p- leitende Bereiche 19. Außerdem ist ein Drainkontakt D mit einer p-leitenden Schicht 18 vorgesehen.5 also shows a source metallization 23, a gate electrode 22 made of polycrystalline silicon, polycrystalline silicon layers 21, n-type source regions 20 and p-type regions 19. In addition, a drain contact D with a p-type layer 18 is provided.
Fig. 6 zeigt ein weiteres Ausführungsbeispiel des erfindungsgemäßen Hochvolt-Randabschlusses, wobei hier aber die p- leitenden Gebiete 25 durch inselartige p-leitende Gebiete 5 ersetzt sind, deren Dotierung zum Rand 11 hin sinkt, was durch eine immer kleiner werdende Darstellung dieser Schichten 5 schematisch angedeutet ist. 106 shows a further exemplary embodiment of the high-voltage edge termination according to the invention, but here the p-type regions 25 are replaced by island-type p-type regions 5, the doping of which decreases towards the edge 11, which is due to the fact that these layers 5 are becoming ever smaller is indicated schematically. 10
Die Fig. 7 und 8 zeigen noch zwei Ausführungsbeispiele des erfindungsgemäßen Hochvolt-Randabschlusses für einen Hochvolt-Feldeffekttransistor mit Injektor. Diese Ausführungsbeispiele sind ähnlich zu dem Ausführungsbeispiel der Fig. 3 und weisen eine schräggestellte Feldplatte 17 in der Isolatorschicht 9 auf, wobei gegebenenfalls auch noch ein Channel- Stopper 16 vorgesehen werden kann. Jedenfalls sind hier keilförmige p-leitende Gebiete 15 vorgesehen, die im Mittenbereich in inselartige Gebiete 5 übergehen.7 and 8 show two exemplary embodiments of the high-voltage edge termination according to the invention for a high-voltage field-effect transistor with an injector. These exemplary embodiments are similar to the exemplary embodiment in FIG. 3 and have an inclined field plate 17 in the insulator layer 9, wherein a channel stopper 16 can also optionally be provided. In any case, wedge-shaped p-type regions 15 are provided here, which merge into island-like regions 5 in the central region.
Ein Sourcekontakt S ist mit n-leitenden Bereichen 26 und p- leitenden Bereichen 27 verbunden und geerdet. Eine Drainelektrode D ist über einen Aluminiumkontakt 14 mit dem Halbleitersubstrat 1 verbunden. Außerdem ist hier noch eine p-leitende Injektorschicht 28 vorhanden, die den schwach injizierenden Injektor des Ausführungsbeispiels der Fig. 3 noch verstärkt. Gegebenenfalls kann auch ein Schottky-Kontakt anstelle der p-leitenden Schicht 28 vorgesehen werden. Ein Teil des Aluminiumkontaktes 14 ist noch durch eine Isolatorschicht 29 abgedeckt.A source contact S is connected to n-type regions 26 and p-type regions 27 and is grounded. A drain electrode D is connected to the semiconductor substrate 1 via an aluminum contact 14. In addition, a p-type injector layer 28 is also present here, which reinforces the weakly injecting injector of the exemplary embodiment in FIG. 3. If necessary, a Schottky contact can also be provided instead of the p-type layer 28. Part of the aluminum contact 14 is still covered by an insulator layer 29.
Das Ausführungsbeispiel von Fig. 8 unterscheidet sich von dem Ausführungsbeispiel von Fig. 7 dadurch, daß hier auf die Isolatorschicht 29 verzichtet wird. Anstelle der p-leitenden Schicht 28 kann auch beim Ausführungsbeispiel der Fig. 8 ein Schottky-Kontakt vorgesehen werden. The embodiment of FIG. 8 differs from the embodiment of FIG. 7 in that the insulator layer 29 is omitted here. Instead of the p-type layer 28, a Schottky contact can also be provided in the exemplary embodiment in FIG. 8.

Claims

11 Patentansprüche 11 claims
1. Hochvolt-Randabschluß für Planarstrukturen, mit einem Halbleiterkorper (1 bis 4) des einen Leitungstyps, auf dem in dessen Randbereich wenigstens eine von diesen durch eine Isolatorschicht (9) getrennte Feldplatte (7, 17) vorgesehen ist, d a d u r c h g e k e n n z e i c h n e t , daß im Randbereich des Halbleiterkorpers (1 bis 4) floatende Gebiete (5, 15, 25) des zweiten Leitungstyps vorgesehen sind, deren Abstand voneinander derart bemessen ist, daß bereits bei einer im Vergleich zur Durchbruchspannung des Halbleiterkorpers (1 bis 4) zu den floatenden Gebieten (5, 15, 25) kleinen anliegenden Spannung die Zonen zwischen den floatenden Gebieten (5, 15, 25) ausgeräumt sind.1. High-voltage edge termination for planar structures, with a semiconductor body (1 to 4) of one conduction type, on which in the edge region at least one of these by an insulator layer (9) separate field plate (7, 17) is provided, characterized in that in the edge region of the semiconductor body (1 to 4) floating areas (5, 15, 25) of the second conduction type are provided, the distance from each other of which is dimensioned such that in comparison to the breakdown voltage of the semiconductor body (1 to 4) to the floating areas (5 , 15, 25) small applied voltage the zones between the floating areas (5, 15, 25) are cleared.
2. Hochvolt-Randabschluß nach Anspruch 1, d a d u r c h g e k e n n z e i c h n e t , daß die floatenden Gebiete (5; 15; 25) in mehreren, im wesentlichen zueinander parallelen Ebenen vorgesehen sind.2. High-voltage edge termination according to claim 1, so that the floating regions (5; 15; 25) are provided in a plurality of planes which are essentially parallel to one another.
3. Hochvolt-Randabschluß nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die floatenden Gebiete (5) inselartig in den Randbereich des Halbleiterkorpers (1 bis 4) eingebettet sind.3. High-voltage edge termination according to claim 1 or 2, so that the floating regions (5) are embedded in the edge region of the semiconductor body (1 to 4) in an island-like manner.
4. Hochvolt-Randabschluß nach einem der Ansprüche 1 bis 3, d a d u r c h g e k e n n z e i c h n e t , daß sich die floatenden Gebiete (5, 15, 25) im Mittenbereich des Halbleiterkorpers (1 bis 4) fortsetzen.4. High-voltage edge termination according to one of claims 1 to 3, so that the floating areas (5, 15, 25) continue in the central region of the semiconductor body (1 to 4).
5. Hochvolt-Randabschluß nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die floatenden Gebiete (15) keilförmig mit schmäler werdender Dicke zum Rand (11) des Halbleiterkorpers hin gestaltet sind. 125. High-voltage edge termination according to claim 1 or 2, characterized in that the floating areas (15) are wedge-shaped with narrowing thickness towards the edge (11) of the semiconductor body. 12
6. Hochvolt-Randabschluß nach Anspruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die floatenden Gebiete (25) schichtförmig mit zum Rand (11) des Halbleiterkorpers (1 bis 4) hin schwächer werdender Dotierung gestaltet sind.6. High-voltage edge termination according to claim 1 or 2, d a d u r c h g e k e n n z e i c h n e t that the floating areas (25) are designed in layer form with the edge (11) of the semiconductor body (1 to 4) weakening doping.
7. Hochvolt-Randabschluß nach Anspruch 3, d a d u r c h g e k e n n z e i c h n e t , daß die floatenden Gebiete (5) zum Rand (11) des Halbleiterkorpers hin kleiner werden.7. High-voltage edge termination according to claim 3, so that the floating regions (5) become smaller towards the edge (11) of the semiconductor body.
8. Hochvolt-Randabschluß nach einem der Ansprüche 1 bis 7, d a d u r c h g e k e n n z e i c h n e t , daß die Flächendotierung der floatenden Gebiete (5, 15, 25) zum Rand (11) des Halbleiterkorpers hin von etwa 1012 bis etwa 1013 cm-2 auf 0 abnimmt.8. High-voltage edge termination according to one of claims 1 to 7, characterized in that the area doping of the floating areas (5, 15, 25) to the edge (11) of the semiconductor body decreases from about 10 12 to about 10 13 cm -2 to 0 .
9. Hochvolt-Randabschluß nach einem der Ansprüche 1 bis 8, d a d u r c h g e k e n n z e i c h n e t , daß mehrere Feldplatten (7) mit Schutzringen (6) des zweiten Leitungstyps vorgesehen sind.9. High-voltage edge termination according to one of claims 1 to 8, d a d u r c h g e k e n z e i c h n e t that several field plates (7) with protective rings (6) of the second conduction type are provided.
10. Hochvolt-Randabschluß nach einem der Ansprüche 1 bis 9, d a d u r c h g e k e n n z e i c h n e t , daß zusätzlich ein Injektor (14 bzw. 28) oder ein Schottky- Kontakt zum Injizieren von Ladungsträgern des zweiten Leitungstyps vorgesehen ist.10. High-voltage edge termination according to one of claims 1 to 9, d a d u r c h g e k e n z e i c h n e t that in addition an injector (14 or 28) or a Schottky contact is provided for injecting charge carriers of the second conduction type.
11. Hochvolt-Randabschluß nach Anspruch 3, d a d u r c h g e k e n n z e i c h n e t , daß die floatenden Gebiete (5) im wesentlichen kugelförmig sind.11. High-voltage edge termination according to claim 3, d a d u r c h g e k e n n z e i c h n e t that the floating areas (5) are substantially spherical.
12. Hochvolt-Randabschluß nach Anspruch 11, 13 d a d u r c h g e k e n n z e i c h n e t , daß der Durchmesser der floatenden Gebiete (5) etwa 5 um beträgt .12. High-voltage edge termination according to claim 11, 13 characterized in that the diameter of the floating areas (5) is about 5 µm.
13. Hochvolt-Randabschluß nach Anspruch 11 oder 12, d a d u r c h g e k e n n z e i c h n e t , daß der Abstand der floatenden Gebiete voneinander etwa 5 um beträgt .13. High-voltage edge termination according to claim 11 or 12, so that the spacing of the floating regions from one another is approximately 5 μm.
14. Hochvolt-Randabschluß nach einem der Ansprüche 12 und 13, d a d u r c h g e k e n n z e i c h n e t , daß die Flächendotierung der floatenden Gebiete etwa 1012 bis 1013 cm-2 beträgt. 14. High-voltage edge termination according to one of claims 12 and 13, characterized in that the area doping of the floating areas is approximately 10 12 to 10 13 cm -2 .
EP99917767A 1998-04-08 1999-03-03 High-voltage edge termination for planar structures Withdrawn EP0996981A1 (en)

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