DE4115399C1 - Integrated circuit - having ion-sensitive liq. sensor and reference electrode having gold@ layer - Google Patents

Abstract

Integrated circuit (I) has an ion-sensitive liq. sensor and a reference electrode (II) which has an Au layer bordering on the liq. The improvement is that a) (I) is enclosed in a housing (III); b) (III) has a window within which (II) is positioned; c) (I) is covered with a protective layer (IV); d) (II) has, below its Au layer, a layer of Ni or Ni/Cr which is positioned on layer (IV); e) (II) is positioned on the front side of (I) and is photolithographically structured; f) (II) extends to a contacting area outside the window of (III); and g) (I), with the exceptions of contact surfaces of (II) and of the active sensor surfaces of the liq. sensor, is so covered, at least within the area defined by the window of (III), that a contact of the soln. can be effected only with the Au layer of (II), whereas a contact of the soln. with the Ni or Ni/Cr layer of (II) is prevented. ADVANTAGE - New circuit is simple to produce and easy to handle.

Description

The present invention relates to an integrated scarf with an ion sensitive liquid sensor and a reference electrode according to the preamble of the patent saying 1.

In particular, the present invention relates to a manufacture Development process for an integrated ion-sensitive sensor detection circuit based on field effect transistor of ions in the sample liquid to be examined. Typi integrated ion-sensitive sensor scarf with ion-sensitive field effect transistors (ISFET) realized an evaluation for the signal evaluation circuit is assigned which MISFETs (Metal Insulator Semiconductor field effect transistor).

With such an integrated ion-sensitive sensor scarf The sample liquid is processed via a separate ref renzelektrode set to a defined potential, whereby the ions it contains, for example H⁺ ions can form a charge on the sensor surface. Like the gate potential in a MOS Transistor inside the ISFET an electric field, wel ches the field effect. When the ISFET is operating can be measured its gate-source voltage, which over a calibration curve for the ISFET used Assignment of the ion concentration in the liquid enables light, which in the case of H von ions the pH Is worth. To detect other ions, ionophores or other layers on the surface of the ISFET are used the.

Is the active gate area of the ISFET with a biological or biochemical membrane, so the ISFET can  Biosensor for the detection of biological and / or biochemical Substances used in the liquid. These substances bring with the help of biologically active components, such as for example microbes, or with the help of biochemical acting components, such as enzymes, antibodies per, receptors, etc., physical effects that for their part, directly or indirectly via other intermediate freaks an electrical output signal within the sensors Generate nal as the gate-source voltage of the ISFET.

The separate reference electrode described above has übli significant dimensions, which is particularly the case with mes solutions in small sample volumes is undesirable. In the the reference electrode contained according to the prior art Reference liquid is in a direct ion exchange with the measuring solution and must therefore be regenerated. The ty pical life of the reference electrode until it rains generation is only about twelve hours.

From the professional publication J. Kimura, et al., "An Inte grated SOS / FET multi-biosensor "Sensors and Actuators, 9 (1986), pages 373 to 387 is already an integrated one Circuit with an ion sensitive liquid sensor in Form of an ISFET known, the integrated circuit in SOS technology (Silicon on Sapphire) is realized. On the back of the sapphire carrier of this structure is one Gold plating applied with the sample liquid is connected as a reference electrode. This shape device of a reference electrode is limited to the SOS Technology because one directly on the semiconductor substrate applied gold electrode for gold diffusion into the Semiconductor structure that would result in the properties of the integrated circuit in an unpredictable manner would change.

The invention is based on this prior art the task of an integrated circuit with a ion sensitive liquid sensor and a reference  to further develop the electrode so that it is easier to manufacture Integrated circuit makes it easy to handle is achieved, the life of the Refe reference electrode should be increased without the integrated Circuit in SOS technology must be realized.

This task is accomplished by an integrated circuit Claim 1 solved.

Preferred developments of the circuit according to the invention are specified in the subclaims.

Below are with reference to the accompanying Drawings preferred embodiments of the Invention according to the integrated circuit explained. Show it:

FIG. 1a to 1e is a flow chart of a first method for Her make the circuit of the invention;

FIGS. 2a to 10b-sectional illustrations of exemplary CMOS scarf invention obligations with integrated reference electrode according to respectively after execution of individual process stages of the procedure according to the invention, with the figures labeled A to an n-channel device and the figures indicated by b p a Obtain the channel circuit of the CMOS circuit;

FIG. 11a and 11b flow diagrams of the modifications of GE in Fig 1 showed first embodiment for a two-tes and third embodiments.

Represent 12A to 13B are cross sectional views of a second and drit th embodiment of the CMOS circuit with an integrated reference electrode, again with a designated Figures n-channel devices and the b figures referred to p-channel devices of the CMOS circuit. and

Fig. 14 is a plan view of the inte grated circuit according to the invention.

In the following description of a first embodiment example, reference is made simultaneously to the flow diagram of FIG. 1 and to the cross-sectional representations of the semiconductor structure of the integrated CMOS circuit according to the invention according to FIGS. 2a to 10b.

The process uses a Sili as the starting material zium disc with a diameter of 100 mm, which in the Floating zone crystal growing process with one orientation (100) is produced, is doped with boron and has a specifi resistance of 17 to 33 ohm cm.

The Fig. 2a, 2b, the components division for the MISFET, the ISFET and in the case of Fig. 2b show a BUILT-IN solution contact.

A first to eleventh process step is described below with reference to FIGS . 3a, 3b. LOCOS technology is used to define the components.

In a first process step, a prenitride oxidation is carried out as dry oxidation at a temperature of 950 °. An SiO ₂ layer with a thickness of 40 nm is produced.

In the subsequent second process step, a 100 nm thick Si ₃ N ₄ layer 2 is deposited on the substrate 1 . In a third process step, the photo technique of a field oxide mask is carried out. This defines the active areas. In a fourth step, the nitride is structured accordingly by dry etching in a plasma reactor. The photoresist is removed in a fifth process step.

In a sixth process step, an n-well phototechnology for determining an n-well 3 ( FIG. 3b) is carried out as a so-called bulk for a p-channel MISFET or a p-channel ISFET, the photoresist for the successive serves the ion implantation.

In a seventh process step, the n-well implantation with P ⁺⁺ ions takes place with an implantation energy of 150 keV and an implantation dose of 6 × 10 ¹² cm ^-2 . In the subsequent eighth process step, the p-channel stop implantation with As⁺ ions takes place at an energy of 100 keV and a dose of 6 × 10 ¹² cm ^-2 . After the removal of the photoresist in a ninth process step and a wet chemical etching of the prenitride oxide in a tenth process step, in an eleventh process step, the tub collection of the n-tub 3 at 1150 ° C. in a nitrogen atmosphere follows. It is advisable to carry out a standard cleaning and subsequent dry oxidation at 950 ° C before collecting the tub.

For the following explanation of the following process steps, reference is now made to FIGS. 4a, 4b. In a twelfth process step, a maskless boron implantation takes place to increase the field threshold voltage in the substrate region as a so-called n-channel stop implantation. The parameter setting (B⁺, 16 keV, 3 × 10 ¹³ cm ^-2 ) allows the ions to penetrate only in the nitride-free areas. In the subsequent wet oxidation at 1000 ° C., field oxide regions 4 grow locally with a thickness of approximately 650 nm.

In a fourteenth process step, wet etching takes place, around the residual nitride left over from the wet oxidation remove.

In a fifteenth process step, the prenitride oxide initially oxidized, the oxynitride being converted into oxide delt is. This so-called "sacrificial oxide" is then wet etched.  

As shown in particular in the detailed illustration of the gate insulator according to FIG. 4b, this is realized in a two-layer construction. The substrate 1 is successively coated with a silicon dioxide layer 5 and a silicon nitride 5 a. In contrast to the oxide, the nitride as the top layer of the gate insulator is hydrophobic and prevents absorption of H⁺ ions, which would falsify the sensor measurement result if they were installed in the gate insulator. However, since the adhesiveness of silicon nitride to silicon is restricted by mechanical stresses, the silicon dioxide layer 5 is used as an intermediate layer. In addition, the impurity density at the interface between the silicon substrate 1 and the silicon dioxide 5 is reduced.

In a sixteenth process step, there is a Stan dry cleaning and an HF dip 950 ° C to generate a gate oxide thickness of 30 nm.

This is followed by the seventeenth process step in the form of a maskless channel implantation (enhancement implantation) of boron with an energy of 20 keV. By splitting the ion dose (0; 2.5 × 10 ¹¹ cm ^-2 ; 5.0 × 10 ¹¹ cm ^-2 ; 7.5 × 10 ¹¹ cm ^-2 ) the threshold voltage of the transistors can be set and their classification as enrichment type or Depletion type.

In an eighteenth process step, a nitride separator in an LPCVD reactor to produce a nitride layer thickness of 70 nm. This step will be a Standard cleaning upstream.

After executing this process step, the construction element picture results according to FIGS. 4a, 4b.

In a nineteenth process step, the photo technique of a poly contact mask is used to define the areas of the buried contacts. For this purpose, the gate nitride 5 a is dry-etched in a plasma etching process in a twentieth process step at the locations identified by reference number 6 .

In the subsequent process step, the photoresist is removed distant. After removing the photoresist, this remains bene nitride as a mask for wet etching of the gate oxide in one twenty-second process step, creating the contact areas be exposed.

In a twenty-third process step, after a Standard cleaning and an HF dip a polysilicon separator in an LPCVD reactor to produce a result the total thickness of 500 nm instead.

In a twenty-fourth process step, the doping of the polysilicon layer 7 takes place in a coating and diffusion process within a POCl ₃ furnace at 950 ° C. with phosphorus. This results in a sheet resistance of the polysilicon layer 7 of 17 to 31 ohms / sq. At the same time, the phosphorus diffuses at the contact areas 6 into the monocrystalline p-silicon 1 underneath, where a highly doped n⁺ region 8 is formed, which forms an ohmic contact with the polysilicon 7 and thus the current transport from through the polysilicon layer 7 ge formed conductor path to the source or drain area enables light. The phosphor silicate glass is then removed by etching. The resulting structure is shown in FIGS. 5a, 5b.

In the description of the following process steps, reference is made to FIGS. 6a, 6b. In a twenty-fifth process step, a photo-technical definition of a polysilicon mask takes place. In the next process step, the polysilicon layer 7 is structured wet-chemically, whereupon the photoresist is removed in a twenty-seventh process step.

As will be explained below, the structured polysilicon layer 7 serves as a mask for the implantation of the source regions and drain regions of the transistors and sensors in the n-channel and p-channel version in the self-adjusting silicone version, which will be explained later. Gate technology, also known as polysilicon technology.

After an HF dip for surface cleaning and a standard cleaning, an annealing or baking step at 850 ° C takes place in a twenty-eighth process step. After a further standard cleaning, a TEOS deposition (Si (OC ₂ H ₅ ) ₄ ) takes place in a twenty-ninth process step within an LPCVD reactor to produce a 50 nm thick SiO ₂ layer. A thirtieth phototechnical process step is used for the phototechnical definition of the mask for the subsequent implantation of the source / drain regions of the n-channel transistors or sensors. With the mask referred to as the SN mask, the areas of the p-channel transistors are covered, whereupon after the wet etching of the TEOS layer in a thirty-first method step, the source / drain islands of the n-channel transistors and sensors are implanted . The P⁺ implantation takes place with an energy of 110 keV at a dose of 5 × 10 ¹⁵ cm ^-2 in a thirty-second process step.

After the photoresist removal in a thirty-third process step and the TEOS removal in a thirty-fourth process step, the implanted phosphor regions are driven in and activated in a thirty-fifth REOX process step after standard cleaning by dry oxidation at 975 ° C., with a 120 nm thick oxide 9 grows on the polycrystalline surfaces 7 , but not on the gate nitride 5 a.

This thermal oxide layer or SiO ₂ layer 9 protects the gate electrodes against the penetration of boron atoms into the polysilicon in the p-channel source / drain implantation with B⁺- following the photo-technical definition of a so-called SP mask. Ions at 60 keV and a dose of 3 × 10 ¹⁵ cm ^-2 . Here it serves for reasons of symmetry simultaneously as a "spacer". With the so-called spacer technique, oxidation of the polysilicon gate edges reduces the amount of underdiffusion in Borato men compared to phosphorus atoms, thereby reducing the length of the channels during the healing process. The resulting structure is shown in Figures 6a, 6b.

With the process steps described so far, the development of the components below the silicon surface is completed. As can be seen in FIGS . 6a, 6b, the MISFETs and ISFETs are identical until the process described now.

The structuring of the semiconductor superstructure is explained below with reference to FIGS. 7a, 7b.

After removing the photoresist in a thirty-eighth process step, the phototechnical definition of a mask for the active sensor areas takes place in a thirty-ninth process step. This mask is used to define the active sensor FET areas, in which the gate insulator comes into contact with the sample liquid above the channel area and causes the field effect. For this purpose, the oxide layer is wet-chemically etched in a forty-th process step and the polysilicon layer 7 is wet-chemically etched in a forty-first process step, and the gate insulator is uncovered at the active sensor region designated by reference number 10 .

In a forty-third process step, after removal of phosphorus silicate glass by etching, a standard cleaning is carried out, whereupon a TEOS deposition is carried out in an LPCVD reactor to produce a layer having a thickness of 100 nm. This TEOS layer 11 serves to protect the gate insulator in the active sensor region 10, for example against polymerisation reactions with photo lacquers and as an etching stop layer, and remains there until the end of the process. In preparation for a getter method used for cleaning the semiconductor structure, which forms the forty-fifth process step, a back-etching of the semiconductor structure is carried out in a forty-fourth process step. For this purpose, the front of the pane is covered with photoresist before the TEOS layer, the gate nitride layer and the gate oxide layer are successively etched on the back. Then the photo varnish is removed.

Gettering is carried out after standard cleaning in a POCl ₃ doping furnace at 900 ° C, which means that the last high-temperature step has been carried out before the passivation to be explained. Finally, a phosphor silicate glass etching is carried out, whereupon the surface resistance should be 18 to 20 ohms / sq.

In a forty-sixth and forty-seventh process step, after standard cleaning of the structure, nitride deposition is carried out in an LPCVD reactor. The resulting Si ₃ N ₄ layer 12 has a thickness of 100 nm. This nitride layer, which is used as a high-temperature passivation, thus covers the polysilicon conductor tracks and means a liquid protection.

One instead of the LPCVD nitride passivation layer at an their CMOS processes usual coverage with PECVD nitride (Plasma Enhanced Chemical Vapor Deposition) indicates its non-stoichiometric bond relationships as well a lower density, a larger number of defects len as LPCVD nitride and would as a liquid protection to fail.

Using a phototechnically defined mask for the active sensor area, which is formed in the forty-eighth method step, the active sensor area is dry-etched using a plasma etcher in the forty-ninth method step. Here, the TEOS layer 11 serves as an etch stop. FIGS. 7a, 7b show the resultant structure after removing the photoresist in a fiftieth process step.

To realize contact holes both to the polysili Zium tracks as well as the diffusion tracks are used for a measurement tall contact mask that in a fifty-first and a Fifty-second process step defined photo-technically becomes.

In a fifty-third, fifty-fourth, fifty-fifth and fifty-sixth process step, a nitride dry etching and an oxide dry etching take place alternately, the passivation nitride layer, the oxide layer, the gate nitride layer and the gate oxide being dry and thus anisotropically etched. The resulting contact holes 13 are shown in Figs. 8a, 8b.

After removing the paint in a fifty-seventh procedural step, a 1 micron thick aluminum layer 14 with a 1% silicon content is deposited as part of a fifty-eighth process step after performing standard cleaning and an HF dip for surface cleaning.

In the following process step, a mask becomes phototechnically defined for the definition of metallic conductor tracks. The Structuring of the metal conductor tracks takes place in a six umpteenth process step by dry aluminum etching using a plasma etcher instead.

After the photoresist has been stripped off in a sixty-first process step, an alloy is joined by forming gas tempering in a sixty-second process step. To protect against corrosion of the aluminum, a 100 nm thick oxide layer 15 is deposited in a plasma reactor (PECVD reactor). The resulting structure is shown in Figures 8 a, 8 b.

The generation of an integrated solution contact according to the invention is described below with reference to FIGS . 9a, 9b, which brings the sample liquid to ground potential and is intended to set an additionally required reference electrode. For this purpose, an adhesive layer 16 made of nickel or nickel / chromium is first deposited in a spatter system with a thickness of 100 nm in a sixty-fourth process step, before a step in a sixty-fifth process is also applied with a gold layer of 500 nm thickness by sputtering.

In a sixty-sixth process step, a solution contact mask is photo-technically defined. In the following sixty-seventh and sixty-eighth process steps, the gold layer and the nickel layer are patterned wet-chemically, whereupon the photoresist is removed in a sixty-ninth process step. The resulting structure is shown in Figures 9a, 9b.

Since nickel or nickel / chrome, unlike gold, is not resistant to aggressive sample liquids, the edges of the solution contact must be covered. With this cover, the oxide-covered aluminum sheets 14 are to be protected independently of the housing. For this purpose, in a process step seventy a, a mask for defining the liquid sensor regions is generated, which is used to structure a photopolymer layer 18 , with which the entire surface of the integrated circuit is covered.

In a seventieth process step, which usually concludes the process, the bond pads, the solution contact 16 , 17 and the active sensor region 10 are opened using the mask formed by the photopolymer layer 18 , from which the TEOS protective layer 11 required during the semiconductor process is passed through Etching is removed. However, the photoresist or the photopolymer layer 18 remains on the surface of the integrated circuit as an additional passivation layer. The resulting finished structure of the integrated circuit according to the invention is shown in FIGS. 10a, 10b.

The gate insulator of the transistors of the CMOS circuit is in contrast to conventional MOS transistors, which are produced in poly silicon technology, in sandwich technology. As mentioned, the gate insulator on the silicon substrate 1 comprises a double layer consisting of 30 nm thermally oxidized SiO ₂ 5 and 70 nm LPCVD-Si ₃ N ₄ 5a.

Nitride has a high chemical load compared to liquids steadfastness and is in particular due to its counter Set resistant to thermal oxide hydrophobic property against H⁺ ions and also forms a barrier against Na⁺ ions.

The sensor components are therefore of a high breakthrough strength with low leakage current. Soon if the structure has a small gate insulator thickness, as it is aimed at MOS transistors.

The property of the LPCVD nitride is also used for the Passivation exploited. According to the temperature profile the entire process is done for reasons of adhesive strength and surface tension after the high temperature passivation of polysilicon oxidation and gettering as well as before Metallization with aluminum.

With the exception of the active sensor area and the area of the solution contact, the integrated circuit according to the invention can be encapsulated in a housing. This must be done in such a way that all aluminum sheets are enclosed by the housing and cannot be exposed to the liquid. In contrast, diffusion paths and polysilicon paths to the drain and source regions can be brought up directly to the active region 10 , since they receive the necessary protection through the high temperature passivation with LPCVD nitride 12 or LPCVD nitride layer of the gate insulator.

The second embodiment of the present invention Ver procedure in accordance with Fig. 11 then differs from the previously described embodiment in that the Kon clocking of the n-channel FETs by diffusion paths and not by polysilicon lines. Accordingly, the nineteenth to twenty-second process steps can be omitted.

As shown in FIG. 13, which shows a detail of the integrated circuit according to the invention, the integrated circuit lies within a housing 33 which has a window 34 , within which, on the one hand, four active gate areas 21 , 22 , 23 , 24 of four ISFETs and on the other hand, two reference electrodes 25 , 26 are arranged. With the exception of the active gate areas 21 to 24 of the ISFETs and partial window areas 27 , 28 of the integrated reference electrodes 25 , 26 , the integrated circuit is covered with a protective layer which is formed by a photopolymer film 29 . The reference electrodes 25 , 26 are therefore only connected to the sample liquid at their gold layers in the area of the window cutouts 27 , 28 .

The reference electrodes 25 , 26 merge into a conductor connection 30 , which first extends under the photopolymer layer 29 to the area which is covered by the housing 33 . The conductor connection extends up to a bond pad 31 , which serves for a bond connection with a bond wire 32 .

Claims (6)

1. Integrated circuit with an ion-sensitive liquid sensor and a reference electrode which has a gold layer adjacent to the liquid, characterized in that
that the integrated circuit is closed by a housing ( 33 ),
that the housing ( 33 ) has a window ( 34 ) within which the reference electrode ( 25 , 26 ) is arranged,
that the integrated circuit is covered with a protective layer ( 15 ),
that the reference electrode ( 25 , 26 ) has a layer of nickel or nickel / chrome below its gold layer, which in turn is arranged on the protective layer ( 15 ),
that the reference electrode ( 25 , 26 ) is arranged on the front of the integrated circuit and is structured photolithographically,
that the reference electrode ( 25 , 26 ) extends to a contacting area ( 31 ) outside the window ( 34 ) of the housing ( 33 ), and
that the integrated circuit with the exception of contact surfaces ( 27 , 28 ) of the reference electrode ( 25 , 26 ) and the active sensor surfaces ( 21 , 22 , 23 , 24 ) of the liquid sensor at least within the window ( 34 ) of the housing ( 33 ) defined area is covered in such a way that contact of the solution can only take place to the gold layer of the reference electrode ( 25 , 26 ), but contact of the solution to the layer of nickel or nickel / chromium of the reference electrode ( 25 , 26 ) prevents it becomes. 2. Integrated circuit according to claim 1, characterized in that
that the layer consisting of nickel or nickel / chromium is arranged on an oxide layer ( 15 ) which forms part of the protective layer. 3. Integrated circuit according to claim 2, characterized in that
that the oxide layer is the uppermost layer of a layer consisting of a gate insulator nitride layer, a protective layer for the gate nitride, a passivation layer made of nitride and the oxide layer itself. 4. Integrated circuit according to claim 3, characterized in that
that the layer sequence is arranged on a field oxide region ( 4 ) in the immediate vicinity of the liquid sensor. 5. Integrated circuit according to one of claims 1 to 4, characterized in
that the thickness of the gold layer is approximately 500 nm and that of the nickel or nickel / chromium layer is approximately 100 nm. 6. Integrated circuit according to one of claims 1 to 5, characterized in
that the ion sensitive sensor is an ISFET.