DE3125783C2 - Circuit arrangement for logical links of a ternary number system - Google Patents

Abstract

The invention relates to a circuit arrangement for logic gates (AND, OR, inverter, anti and insulating), which are formed from at least one switching element of a first type (K) and / or at least one switching element of a second type (KΔ) . The switching elements of both types (K and KΔ) are implemented by optoelectronic coupling devices, the inputs and outputs (1, 2 and 3, 4) of which are electrically decoupled. The half and full adding devices (HAD and VAD) formed from the logic elements (FIGS. 7b and 8b) are used for the computational processing of data of a ternary number system. Such adders are used in commercial computing systems. these compounds and biocidal agents containing them, in particular with f

Description

N = a 0 - 3 "+ a 1 ■ 3> + a 2 - 3 ² + a 3 3K ..

Technically implemented, the valence of a can assume +1.0 or - 1 or H (high), 0 (zero) or L (low). With a one-byte memory, that is to say with a memory with η = 8 memory cells, each of which can assume three mutually different switching states, 3 "= 6561 different characters can therefore be represented.

Compared to the well-known binary logic in which the memories only create two different sound / .states can assume that with a similar memory there are only 2 "= 256 different characters map.

For the practice of the use of the ternary logic to perform arithmetic operations is compared currently iw usual binary logic that the character set for the same storage volume is higher by a factor of 1.5 "and the memory can be reduced by this factor with the same volume of calculation.

From the literature, e.g. B. Proc of the llishlh Intern. Symp. On Multiple-Valued Logic, Rosemont. Illinois. 1978, pp. 1-6, are already switching modules with so-called Tristateverhaltcn proposed from which logic elements for the implementation of Addicr switching devices for the application of the ternary logic and would have to be built from switching elements of different types exist, / .. B. DE-DS 22 03 875. However, these known switching modules have under among other things, the disadvantage that their input and output circuits are galvanically coupled to each other, so that, for example a clear evaluation through voltage tolerances and / or corresponding component tolerances the individual switching states is difficult and possibly due to major deviations Error calculations cannot be ruled out.

The object of the invention is that the disadvantages of the previously known Schaltbaustei ^'- to avoid e and as simple as possible to build up the necessary arithmetic operations gates and beyond in terms of their structural composition with the least possible effort. According to the invention, this is achieved through the combination of features 1.1 to 1.5.

The use of switching elements with differently directed control behavior is essential to the invention if the input conditions are the same, their inputs and outputs are electrically completely different from each other are separated, so that a current coupling of the input and output circuits of the respective switching elements is excluded from the outset. This achieves in a simple manner that the otherwise usual direct current components is practically no longer available, as the information is statistically the same contain many positive and negative impulses.

According to an advantageous embodiment of the invention it is provided that the switching elements of the first and the second type are implemented as optoelectronic coupling devices. This is how the individual links are to be implemented in a simple manner with regard to their structural design and can be can be integrated into the currently used module technology without any particular difficulty.

Optoelectric coupling devices are for the Structure of binary logic elements known, DE-OS 23 10 053, DE-AS 25 27 520, radio television electronics, 27 (1 978) issue 3.page 197.

Further advantageous embodiments of the invention are defined by claims 3 to 7, which in detail the structure of the different links - the AND link by claim 3, the OR logic element by claim 4, the inverter logic element by claim 5, the anti-linker by claim and the isolating link by claim 7 - indicate.

With the claim 8, an advantageous development of the invention is given the claimed by claim 7. Insulating Vcrkniipfungsglicdes, wherein the insulating function now both the concerns of the po- ^r i sitiven potential at the Positivpoienlial live terminal as well as upon application of the negative potential to the negative potential leading terminal can take effect.

Further advantageous configurations of the invention

to are due to the combination of features 9.1 to 9.3, which describe the half adding device, and through the combination of features 10.1 to 10.5, which describe the full adding device, is given.

The invention is illustrated by FIGS. 1 to 8 explained in more detail, Fig. t shows the basic circuit diagram of the switching element of the first and second type, the F i g. 2a to 6a show the respective structure and FIG. 2b to 6b the respective circuit symbols of the various logic elements (And, or, inverter, anti and isolation link) represent and the F ι g. 7a and 8a the respective circuit symbol and the F i g. 7b and 8b, respectively specify the specific embodiment of the half adding device or the full adding device.

2a shows the AND logic element in which the switching elements of the first type (K 12, K .32) as optoelectronic coupling devices of the "pnp" type and the switching elements of the second type (K'22, K'42) as optoelectronic Coupling facilities of the type »npn« are implemented. The inputs (1, 2) from the switching element of the first type K 12 and from the switching element of the second type K'22 are connected in anti-parallel to the input terminal £ 12 and to the terminal 0 carrying zero potential. Analogously, the inputs of the switching element of the first type K 32 and of the j5 switching element of the second type K'42 are connected to the input terminal £ 22 and the connection terminal 0 carrying zero potential. To implement the AND function, the outputs of the first and second switching element of the first type K 12 and K 32 or the outputs of the first and second switching element of the second type K'22 and K'42 are connected in series.

The AND logic element shown here with its two input terminals (E 12, £ 22) can also have any number of input terminals through appropriate extensions, so that this embodiment is not limited to an AND gate with two input terminals.

The so-called truth table for the AND-logic element is given below for the functionality. It can be seen that only if the two values at input terminals £ 12 and £ 22 are identical, this value also appears at output terminal A 2 , while in all other cases zero potential is applied to output terminal A 2.

Truth table for the AND logic element

£ 1 £ 2 A = Ei AE2 W) 0 0 0 0 H 0 H L. 0 H 0 0 H H H 65 0 L. 0 L. H 0 L. 0 0 L. L. L.

ίο

The F i g. 2b indicates the symbol of the AND logic element, the input terminals being labeled E12 and £ 22 and the output being labeled A 2.

The OR logic element, shown in FIG. 3a, is connected on the input side like the AND logic element in FIG. La. Only on the output side do the first and second switching elements of the first and second type K 13, K 33, K'23 and K'43 work with the same working resistance, the first resistor R 13 and the second resistor R 23, on the common output of the output terminal A 3 As can be seen from the truth table shown below. If the input potentials at the first input terminal £ 13 and the second input terminal £ 23 are opposite, either the first and second switching elements of the first type K 13, K 33 or the first and 2, wide switching elements of the second type K'23, K '43 are on the output side switched through, so that when the first and second resistors R 13, R23 are equal, zero potential is again established at the output terminal A 3.

In the case of the OR link, too, is appropriate Extensions to expand the number of input terminals as required.

K'25, K'35 realized, K '45, that is, here optoelectronic KoppeWinrichtungen type "NPN" are used that are not equal polarity connected in series and basically N potential switch through.

Truth table

of the anti-linker

IO

15th

20th

FA E2 AE \ ~ £ 2 0 0 0 0 H 0 H L. L (H) H 0 0 H H 0 0 L. 0 L. H L (H) L. 0 0 L. L. 0

Truth table El A-egg v £ 2 for the OR link 0 0 E \ H H 0 L. 0 0 0 H H H H H L. L. H H 0 0 0 L. L. L. L. L. L.

JO

35 The F i g. 5b shows the circuit symbol of the anti-link with the first input terminal £ 15 and the second input terminal £ 25 and the output terminal Λ 5.

The F i g. Figure 6a shows the isolating link which implemented the blocking input known from the binary logic gates.

As can be seen from the following truth table of the isolating link, the output terminal A always has the same value as the input terminal E. as long as zero potential is present at the blocking input S. In all other cases there is zero potential at output terminal A.

Truth table

of the isolating linkage

5F

40

The F i g. 3b shows the circuit symbol of the upper link element with the first and / or wide input H terminal £ 13, £ 23 and the common output H terminal A3. H

4a shows the Inverter linkage element with 45 a switching element of the first type K 14 and an L switching element of the second type K'24. For the inversion L in three-valued logic, compared to the negation in the binary system, the conventions that H -L and C = H and 0 = 0 are agreed.

4b shows the circuit symbol for the inverter link with the input terminal £ 4 and the output terminal A 4.

The Figure 5a shows the anti-link, at 0
H
L.
0
H
L.
H
0
L.

0 0 0 H 0 0 0 L 0

50 As possible variants of this isolation linkage quality, it would be conceivable to let the blocking function also become effective with the potentials H or L at the blocking input S. The Fig.6a shows the circuit of the isolating link, which all three of the

the following radio conditions 55 above are optionally fulfilled according to the truth table. Of the eruptions apply: The anti-function is then and only the first locking gear S! 6 acts when the positive is applied H or L, if the inputs to be linked are at ven potential, while the second blocking input S 26 the first input line £ 15 and on the second input when the negative potential is applied, the output line is effective £ 25 different and switched from zero potential. By connecting the two locking devices in parallel have different values. In all other cases t> o inputs 516 and S26, the isolating function is both

there is zero potential at output terminal A 5. This means that, depending on the choice of circuit, an anti (H) or an anti (L) link can be implemented. However, the restriction to one of these types is irrelevant, since a potential reversal is possible at any time by means of the inverter link (Fig. 4a). The structure of the anti-linkage song is here by means of four switching elements of the second type K '15.

effective at the positive as well as at the negative potential. The third switching element of the first type K 36 and the switching element of the second type K'46 are connected to the connection between the input terminal £ 6 and the output terminal A 6, of which the second switching element of the first type K 36 is connected by the optoelectronic coupling device of the pnp- Type «and the switching element of the second type K'46

is implemented by the optoelectronic coupling device of the •> npn type «. The inputs 1, 2 of these two switching elements are connected in series and form nv · the resistor /? 66 the working resistance of the pitp ' transistor T. The transistor Γ is conductive in the idle state and thus the input terminal £ 6 to the output terminal A 6 is open regardless of polarity.

The base of the transistor T is connected to the respective input 3 of the first and second switching elements of the first type K 16, K 26. If one of these two switching elements K 16, K 26 becomes conductive, the transistor is blocked and thus the third switching element of the first type K 36 and the switching element of the second type K'46 are also switched to non-conductive. The output terminal A 6 is "isolated" from the input terminal 6 and the zero potential is effective at the output terminal A 6 via the third resistor 36. The first and second blocking input terminal 516 and S 26 are connected to the first and second switching elements of the first type K 16 and K 26 in such a way that the first element of the first type K 16 is switched through when positive potential at the first blocking input terminal 516 and the second switching element of the first type K 26, if negative potential is applied to the second blocking input terminal 526.

6b shows the symbol of the isolating link with the input terminal £ 6 and the output terminal A 6 as well as the first and second blocking inputs 5 16 and 5 26.

For performing the arithmetic operations in digital data processing, the so-called half and full adding devices are used as basic circuits, which are shown in FIGS. 7a and 8a are shown in detail with regard to their composition from the corresponding logic elements, while FIGS. 7b shows the circuit symbol of the half- adding device HAD with the corresponding total inputs AB, the transfer output Q and the total output 5. FIG. 8b shows the circuit symbol of the full adding device with the sum inputs A and β as well as the carry input Ü 1 and the carry output Ü2 and the sum output 5.

For the in F i g. 7a, the following truth table results.

Truth table

for the half adder

Linking the inputs HH and LL with the Ys'truth table of the OR link. For the half -adding device HAD , the above-mentioned links at the sum output 5 result in the inversion of the OR link. Since the inversion of the desired result is also present at the carry output 0 in these links, the sum output is connected to the carry output by the inverter link so that the half adder HAD can be implemented according to the circuit according to FIG. 7a.

The symbol of the full adding device VAD is shown in FIG. h "of the conditions from the two sum inputs A and B, the carry input Ü 1 and the carry output Ü2 and the sum output 5, indicates.

Truth table 1

Ü \

Ü2

0
H
0
HLL 0 LH

0 0 0 0 H 0 0 0 L.

(1) 0 0 0 0 0 (2) 0 0 H H 0 (3) 0 H 0 H 0 (4) H 0 0 H 0 ο (5) 0 0 L. L. 0 (6) 0 L. 0 L. 0 (7) L. 0 0 L. 0 (8th) 0 L. H 0 0 (9) L. 0 H 0 0 15 (10) L. H 0 0 0 (H) 0 H L. 0 0 (12) H 0 L. 0 0 C ' ³ ) H L. 0 Λ
υ 0 (14) 0 H H L. H to (15) H 0 H L. H (16) H H 0 L. H (17) 0 L. L. H L. (18) L. 0 L. H L. . (19) L. L. 0 H L. »5 (20) L. L. H L. 0 (21) L. H L. L. 0 (22) H L. L. L. 0 (23) H H L. H 0 (24) H L. H H 0 50 (25) L. H H H 0 (26) H H H 0 H (27) L. L. L. 0 L.

The F i g. 8a shows the complete structure of the full-loading device, which essentially corresponds to a half-adding device which has been modified with a view to eliminating logic errors and is supplemented by corrective logic elements. The OR link O 1 in combination with the OR link 60 links O 2 and O 3 and the AND link 1/2, the isolating links / 1 and / 3 and the inverter link IN practically correspond to How to get through Comparison with the truth table in FIG. 7a can be recognized with the same symbols for the AND-logic element, logic elements of the half-adding device, while the linkage of the sum inputs A and B 65 rend all other logic elements - the OR to carry over with the AND-logic element after logic element O 4 with the anti-logic element Realize claim 3. Furthermore, the sums ANX to AN3 and the isolating logic element value in this truth table agree with the ver / 3 as well as the AND logic element t / l with the iso-

Down logic element / 2 - only used for »error correction«.

For a better understanding and to explain the complete full adding device according to FIG. The truth table 1 is also shown in FIG. 8a, which, compared to the truth table i, has two additional columns - one for "correcting" the sutnmenwert S 'and another for "correcting" the carry output UT.

Truth table 2

OX

S '

0) 0 0 0 0 0 (2) 0 0 H H 0 (3) 0 H 0 H 0 (4) H 0 0 H 0 (5) 0 0 L. L. 0 (6) 0 L. 0 L. 0 (7) L. 0 0 L. 0 (8th) 0 L. H 0 Π (9) L. 0 H 0 0 (10) L. H 0 0 0 (H) 0 H L. 0 0 (12) H 0 L. 0 0 03) H L. 0 0 0 (14) 0 H H H H (15) H 0 H H H C-6) H H 0 H H (17) 0 L. L. L. L. (18) L. 0 L. L. L. (19) L. L. 0 L. L. (20) L. L. H L. L. (21) L. H L. L. 0 (22) H L. L. L. L. (23) H H L. H H (24) H L. H H 0 (25) L. H H H H (26) H H H H H (27) L. L. L. L. L.

When zero is set The described combination of these five additional logic elements switches the carry output Ü7f to zero potential in twelve different combinations of A, B and OI (lines 8 to 13 and lines 20 to 25 of truth table 2). An error does not arise, because in all these cases, according to the Wahrheitsubelle 1, the zero potential is desired on the upper carry output U2 To the desired correction in the sum output S ίο to get ', two different corrections are required. First of all, the last two lines of truth table 2 show that the combination of A ν B ν C each results in the value H or L, while the sum output S according to truth table 1 must have the value zero. Since these errors only occur when the link A λ Β λ C assumes the value H or L, the appropriate error correction can be made by using the AND logic element U 1 in conjunction with the isolating logic element / 2.

A further correction concerns lines t4 to 19 in truth table 2, where the inverted value must be in each case for the sum output S '. Since the values at the carry output Ö2 are not equal to zero with these six links, the undesired value is first "blocked" with the aid of the isolating link / 1 and then the inverted value is generated using the inverter link W

For the links AaB 0 1 - H or L - lines 26 and 27 of the truth table 2 - the carry output Ü2 is also not equal to zero. However, this does not result in an error at the sum output S ' , since Kir this combination, the Isolicr logic element / 2 becomes effective and the sum output 58 switches to the desired value zero.

With the full adding device described, the known arithmetic operations with the ternary information quantities are carried out.

In order to realize the sum values S ', an attempt has been made to use an OR link A ν S ν Cc. The second column for the implementation of the transmission output Ü2 ' provides for a link (A ν B) λ (B ν Ü I) to be used. A comparison of the carry output Ü 2 in both truth tables 1 and 2 shows that the values in lines 20, 22, 23 and 25 do not match. Instead of L or H, there would have to be an Ostehen.

The situation is similar with the total values of lines 14 to 19 as well as lines 26 and 27. Here is note that, first, the values in lines 14 through 19 should be inverse; i.e., L instead of H or H instead of L correctly and secondly, the values in lines 26 and 27 must be zero instead of H or L.

With regard to the carry output Ü2 ' to be corrected, it should be noted with regard to the truth table of the anti-logic element that the logic operation (A ν B) λ (B ν oil) is only faulty. if w> at least one of the values at the sum inputs A, ß or 01 assumes the value H, another one assumes the L and the carry input Ol assumes the value H or L. The in F i g. Combination of anti-gates AN 1. AN2 AN3 and 8a shown with the OR gate OA and the insulating gate / 3 yeasts the desired result, with the carry output t / 2 in the error cases, the

In addition 5 sheets of drawings

Claims (10)

Patent claims: 1.! Circuit arrangement for logical connections, especially for formed from AND, OR, inverter, anti and isolating links Half and full adding devices for the computational processing of data of a ternary Number system, marked by combining the features 1.1 the logic gating circuits have at least one switching element of a first type (K) and / or at least one switching element of a second type (K ') , the switching elements of both types (K and K') each via their inputs (1, 2) are controllable, 1.2 the inputs (1, 2) and output. (3, 4) of each contact element of both types (K and K ') are electromagnetically, electrostatically and galvanically not coupled to one another, with the same control conditions at the! inputs (1,2) of the switching elements (K and K ') hießt at the outputs (3,4) of the two switching elements (K and K') either no current or depending on the type of the switching element (K and K ') a stream in different directions, 1.4 the inputs (1, 2) of the switching elements (K. K ') are connected in anti-parallel or in series, with one of the inputs (1, 2) being connected to a fixed potential, 1.5 the outputs (3, 4) of the switching elements (K, K ') : are connected to a fixed potential and / or to one another in parallel or in series. j5 2. Circuit arrangement according to claim 1, characterized by the feature 2.1 the switching elements of the first and the second type (K and K ') represent optoelectronic coupling devices. 3. Circuit arrangement for the AND logic element according to claim 1 and / or claim 2, characterized by the combination of features 3.1 the AND logic element has two switching elements of the first type (K 12, K 32) and two switching elements of the second type (K'22, K'42) , the inputs (1,2) of the first switching element of the first type ( K 12) and the first switching element of the second type (K'22) as well as the inputs (1, 2) of the second switching element of the first type (K 32) and the second switching element of the second type (K'42) are each connected in antiparallel and the Input (1) of the first switching element of the first type (K 12) via a fourth resistor (R 42) with a first input terminal (T 12) and the input (1) of the second switching element of the first type (K 32) via a fifth resistor (R 52) are connected to a second input terminal (£ 22) and the inputs (1) of the first and the second b ^r> switching element of the second type (K '22, K '42) having a nullpotentiuHührenden terminal (0) in compound stand, the outputs (3, 4) of the first and second sound element of the first type (K 12 and K 32) connected in series, the output (3) of the first switching element of the first type (K 12) via a first resistor (R 12) to an output terminal (A 2) and the output (4) of the second switching element of the first type (Ti 32 ) is connected to a terminal (P, J) carrying positive potential, the outputs (3, 4) of the first and second switching element of the second type (K'22 and K '42) are connected in series, the output (3) of the first switching element of the second type (K'22) via a second resistor (R 22) can be connected to the output terminal (A 2) and the output (4) of the second switching element of the second type (K ' '42) can be connected to a negative potential-carrying terminal (N) , the output terminal (A 2) is connected to the zero-potential-carrying terminal (0) via a third resistor (R 32) _r which is much larger than the first to fifth resistor (R 12, R 22, R 42, R 52) is connected. 4. Circuit arrangement for the OR logic element according to claim 1 and / or 2, characterized by combining the features 4.1 the OR link has two switching elements of the first type (K 13, K 33) and two switching elements of the second type (K'23, K'43) . wherein the inputs (1,2) of the first switching element of the first type (K 13) and of the first switching element of the second type (K'23) and the inputs (1, 2) of the second switching element (K'33) and the second switching element of the second type (K'43) connected in antiparallel and the input (1) of the first switching element of the first type (K ^; 3) via a fourth contradiction (R 43) with a first input terminal (E 13) and the input (1) of the second switching element of the first type (K 33) are connected to a second input terminal (£ 23) via a fifth resistor (R 53) and the inputs (1) of the first and second switching elements of the second type (K'23. K ' 43) are connected to a terminal (0) carrying zero potential. 4.2 the outputs (3, 4) of the first and the second switching element of the first type (K 13 and K 33) are connected in parallel, the output (3) of the first switching element of the first type (K 13) via a first resistor (R 13) with an output terminal (A 3) and the output (4) of the second switching element of the first type (K 33) can be connected to a terminal (fy carrying positive potential, the outputs (3, 4) of the first and second switching element of the second type (K '23 and K'43) are connected in parallel, the output (3) of the first switching element of the second type (K'23) via a second resistor R. 23) can be connected to the output terminal (A 3) and the output (4) of the second switching element of the second type (K'43) to a terminal (N) carrying negative potential, 4.3 the output terminal (A 3) is connected to the terminal (0) carrying zero potential via a a third resistor (R 33), which is much larger than the first to fifth resistor (R 13, R 23, R 43, R 53) is connected,
4.4 the first to fifth resistance (R 13, /? 23, R 43, R 53) are the same size. 5. A circuit arrangement ÜR ^r the! Nverter-Verknüpfungsglicd according to claim 1 and / or 2, characterized by the combination of features 5.1 the inverter link has a switching element of the first type (K 14) and a switching element of the second type (K'24) , the inputs (1, 2) of the switching element of the first type! 5 (K 14) and the inputs (1 , 2) of the switching element of the second type (K'24) connected anti-parallel and the connection (2) of the switching element of the first type (K 14) via a fourth resistor (R 44) with an input terminal (E4) and the input (2) of the switching element of the second type (K'24) are connected to a nuüpoientiaifleitenden connecting terminal (0), the output (3) of the switching element of the first type (K 14) is connected to an output terminal (A 4) via a first resistor (R 14) and the output (4) of this switching element (K 14) is connected to a terminal carrying positive potential (/ ^, the output (3) of the switching element of the second type (K'24) is connected to the output terminal (A 4) via a second resistor (R 24) and the output (4) of this switching element (K'24) is connected to a terminal (N ) connected, j5 the output terminal (A 4) is connected to the zero potential-carrying connection terminal (0) via a third resistor (R 34). 6. Circuit arrangement for the anti-logic element according to claim 1 and / or 2, characterized by combining the features 6.1 the anti-link element has four sound elements of the second type (K '15, K'25, K'35, K'45) , the inputs (1, 2) of the first and second switching elements (K' \ 5, K'25) and the third and fourth switching elements (K'35, K '45) each connected in anti-parallel and the input (1) of the first switching elements (K'15) via a fourth resistor (R 45) having a first input terminal (e 15) and the input (1) of the third switching element (K'35) are connected via a fifth resistor (R 55) to a second input terminal / £ 25) and the inputs (1) of the second and fourth switching element (K '25, K '45) are connected to a terminal (N) carrying negative potential, 6.2 the outputs (3, 4) of the first and fourth to switching elements (K '15, / C'45) and the outputs (3, 4) of the second and third switching elements (K'25, K'35) are each in series switched, whereby output (3) of the first and second switching element (K '\ 5. K'25) via a common first resistor (R 15) with an output terminal (A 5) and output (4) of the fourth switching element (K'45 ) can be connected to the terminal (N) carrying negative potential, the output terminal (A 5) is connected to an output terminal (0) carrying zero potential via a third resistor (R 35), 6.4 the four switching elements of the second type (K'15, K'25. K'35. K'45) can be replaced by four switching elements of the first type, the negative potential being replaceable by a positive potential. 7. Circuit arrangement for the isolating link according to claim 1 and / or 2, characterized by the combination of features 7.1 the isolating link has three switching elements of the first type (K 16, K 26, K 36) and one switching element of the second type (K'46) , the inputs (1,2) of the first and second switching elements of the first type (K 16, K 26) and the input · .- {i, 2) of the third switching element of the first type (K 36) and the switching element of the second type (K'46) are each connected in series and the input (1) of the first switching element (K 16) via a four resistor (R 46) with a first blocking connection terminal (S 16) and the input (2) of the second switching element (/ C 26) via a fifth resistor (R 56) with a second blocking connection terminal (S 26) and the input (1) of this switching element (K 26) are connected to a terminal (0) carrying zero potential, the outputs (3, 4) of the first and second switching element of the first type (K 16, K 26) and of the third switching element of the first type (K 36) and of the switching element of the second type (K'46) are each connected in parallel, with the output (4) of the first and two-tone switching element (K 16, K 26) with a terminal (P) carrying positive potential and the output (4) of the third switching element of the first type (K 36) and the switching element of the second type (K'46 ) with an input cycle (E6) and the outputs (3) of the third switching element of the first type (K 36) and the switching element of the second type (K'46) are connected to an output terminal (A 6), the input (2) of the Switching elements of the second type (K'46) are connected to the terminal (0) carrying zero potential via a sixth resistor (R 66) and to the output terminal (A 6) via a third resistor (R 36), 7.4 the isolating link has a transistor (T) , the emitter and base connection of which is connected via a first and second resistor (R 16, /? 26) to the terminal (0) carrying zero potential and its collector connection to the input (1) of the third switching element of the first type (K 36) can be connected. 7.5 the first and the second switching element of the first type (K 16, K 26) influence the input and output terminals (E6 and A 6) of the third switching element of the first type (K 36) and the switching element of the second type (K'46) via the respective blocking connection terminals (S 16, S 26) such that when positive potential is applied to the first blocking terminal (S 16) and / or when negative potential is applied to the second blocking terminal ^ 1S 26) at the output terminal (A 6), zero orientation is always effective. 8. Circuit arrangement according to claim 7, characterized by the feature IO 8.1 the first and second blocking connection terminal (S 16 and 526) can be switched in parallel. 9. Circuit arrangement for the half adding device according to claim 1 and / or 2, gekennzcichnet by combining the features 9.1 the half-adding device (HAD) has an AND link according to claim 3, an OR link according to claim 4, an isolating link according to claim 7 and an inverter link according to claim 5. the respective inputs (E 1 .... E 2) of the AND and OR gates are connected in parallel and each have a first and a second sum input (A 7 and ß7) of the half adder fH / 4D; form, 9.2 the output (A 2) of the AND logic element is identical to a transmission output (Ü7) jo of the half adder (HAD) , which is also identical to the input (EA) of the inverter logic element and the blocking connection terminals (S 16. S 26) of the Isolier Link is connected. « 9.3 the output (A 3) of the OR link forms the input (ES) of the isoüer link. whose output (A 6) is connected to the output (AA) of the inverter link and forms a sum output (S7) of the half adder (HAD) . 10. Circuit arrangement for the full adding device according to claim 1 and / or 2. marked * ■ -, net by the combination of the features Anti-link (AN 1) and the respective input (E 1 ...) of the third OR link (O 3) and the second anti-link (AN 2) are connected to the second sum input (B 8),
the input (EZ ...) of the first and logic link (U I) and the respective input (E 2) of the third OR link (O 3) and the second and third anti-logic link (AN2, AN3) are connected to the carry input (O 18 ) tied together, 10.3 the respective output (A 3) of the second and third OR logic element (O 2, O 3) forms the respective input (E 1 ..., E2 ...) of the second AND logic element (U 2), its output (A 2) is identical to the input (Ef>) of the third inverter link element (/ 3), of which the output (A 6) with the blocking terminals, '5 56, S 26) of the first isolating link ( 1 1) and is connected to the input (EA) of the inverter link (IN) and also represents a carry output (Ü28) of the full adding device (VÄDJ. 10.4 the output ^ 4 3) of the first OR logic element (O 1) is connected to the input (E 6) of the first isolating logic element (1 1), the output (A 6) of which is connected to the output (AA) of the inverter Linking element (IN) and the input (E 6) of the second isolating link (! 2) is in connection, the output (A 6) of the / wide isolating link (12), its blocking terminals (S 16, 526) with the Output (A 2) of the first AND logic element (U \) is connected, forms a sum output (58) of the Voüaddieinrichtung (VA Dl 10.5 the respective output (A 5) of the three anti-logic elements (AN 1 to AN3) form the respective inputs (Ei, E2, EZ) of the fourth OR-logic element (OA), the output (A 3) with the second blocking connection terminal (526) of the third isolating link (1 3) is connected. 10.1 the full adding device (VAD) has four OR links (Oi to OA) according to claim 4, two AND links (Ui, V2) according to claim 3, three anti-link elements (AN 1 to AN3) according to claim 6 and three insulating Logic elements (Ii to / 3) according to claim 7, wherein the OR and AND logic elements fOI and £ / l) each have three inputs (E 1 ... to £ 3 ...) which are each connected in parallel and with the input (E 1 ...) a first sum input (A 8). with the input (E2 ...) represent a second sum input (BS) and with the input (Ei ...) represent a transfer input (0 18) of the full adding device fV / 4, D ^, 10.2 the respective input (Ei ...) of the Odcr linking element (O 2) and the two anti-linking elements (ANi and AN3) is connected to the first sum input (A 8), the respective input (E2 ...) of the second OR -Linking element (O 2) and the first The invention relates to a circuit arrangement for logic gating elements, in particular for from And-, Or-. Inverter, anti and Isolierverknupfungsglicdern formed half and full adding devices, for the computational processing of data of a ternary number system,
ν; From number theory it is known to represent every whole number as a connection of powers of three. Any whole number N must therefore be defined as follows: