DE2651745A1 - MESSAGE SYSTEM WORKING IN TIME MULTIPLEX WITH IMPULSE CODE MODULATION - Google Patents

Description

MANITZ, FINSTERWALD

Munich, November 12, 1976 P / £ / mü-N 2101

NORTHEElT TELECOM LIMITED 1600 Dorchester Blvd. Vest, Montreal, Quebec, Canada

Subject system working in the time division multiplex with

Pulse code modulation

The invention relates generally to a time division multiplex system, employing pulse code modulation signals, and in particular a method and apparatus for information exchange between different user terminals of a time division multiplex system with pulse code modulation.

Time division multiplex telephony systems operate on a time division basis, that is, a series of calls share a single communication path. The calls are each assigned or fed to the message switching path for short, periodically recurring time intervals. Part-DR. C. MANlTZ. · D1PL.-ING. M. FINSTERWALD DIP L. -IN GW CRAMKOW ZENTRALKASSE BAYER. VOLKSBANKEN MÖNCHEN 22. ROBERT-KOCH-STRASSE I 7 STUTTGART SO (BAD CANNSTATT) MÖNCHEN. ACCOUNT NUMBER 7270 TEL. 1089) 22 42 U. TELEX β-29672 PATMF SEELBERGSTR. 23/25, TEL. (0711) 56 72 6! POST CHECK! MONKS 77Ο62 - 60S

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ORIGINAL INSPECTED

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Pieces or samples of the conversation are listed under Use of the pulse modulation technique in appropriate Binary words encoded. These words are transmitted over the message exchange during the assigned time window transmitted and then in the receiving stations in the original Conversations decoded. A time-division switching system usually has two outgoing and two incoming paths between a network in the switching system and the associated user message terminals are switched. A conversation between two user terminals is allocated to a time window bzxtf. assigned and transmitted over the incoming and outgoing routes. Both the incoming and outgoing routes will be used to keep each side of the conversation separate from the other to keep. The network determines the incoming and outgoing routes of the two user terminals and the signal on the incoming path of one is transmitted to the outgoing path of the other. The user ends will be under the control of a link memory in the Switching system enabled or controlled. The memory includes a word memory location which is allocated to each of the time slots in a time slot group (time slot frame). The memory word at each memory location contains both the Address of the two end points to be connected as well as the identification of the routes that have to be released, to make the connection.

If the capacity of such a system is expanded, so will additional pairs of incoming and outgoing paths are required and space-time switching is required in order to for the conversation the den. to release or control user terminals assigned to different pairs of routes.

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This requires a corresponding expansion in the storage capacity. In addition to this, an extension or increase the length of the memory words themselves. Every word must now have time slot information included in order to enable a data memory to store sections or samples between time windows to be transmitted, and it must contain room switching information

•, hj. / (space switch)

ten to put a space switch ± n in a position to different to connect the incoming and outgoing routes in the required manner. As a result, the increased The cost of the storage capacity is usually disproportionately large compared to the growth of the Number of user terminals.

An example of a time division multiplex switching system is described in U.S. Patent 3,573,381. This system has a Variety of combination space switching and data storage devices, the data between different time channels during their transmission between multi-channel time division multiplexed lines realize. Although this system is quite flexible and has a high traffic performance, it requires a significant amount of memory both for controlling the operation of the switching network and also for the storage of the data to be transmitted.

Another example of a time division multiplex switching system is disclosed in U.S. Patent 3,694,580. This system switches individual bits of information from pulse code modulated words between different time windows and time division multiple lines. Figures 4A and 4B show pulse shifters each of which has two shift registers and one Gate or logic matrix, which is connected between the shift register, includes. The gate or linkage

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matrix is controlled by the memory in such a way that it contains a new pole of the information bits in each group (frame) selects. This system is relatively flexible and "has a high traffic performance; however, it becomes a very." large memory required for controlling the impulse slide.

Prior art requires time division multiplexed pulse code modulation switching systems generally large memory and result in high traffic -Handling performance. In a situation where there are only a few hundred telephones and relatively few Traffic requirements are present, the known pulse code modulation time division multiplex systems are too expensive to be a practical alternative for other forms of time division multiplexing systems, such as e.g. B. Pulse Amplitude Modulation Systems or to form delta modulation systems. On the other hand, phone systems tend to show themselves expand over time. Pulse amplitude modulation systems or delta modulation systems are used because of their cost advantages · Χη acceptable to a small system despite its known component parts. In larger systems where their cost advantage is slight or nonexistent, they are unacceptable.

The private branch exchange user is currently prepared made the decision to use an prohibitively expensive time-division multiplexed pulse code modulation system from the start install that is far larger than it meets its current requirements, or one that is far less expensive System, which is only enlarged or at high cost

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cannot be expanded at all. It is not uncommon for the less expensive system to be chosen that meets the current requirements corresponds but not in an economical way can satisfy future needs * Above with a certain system size, however, the expansion costs rise unprecedentedly. At a certain time a must New and larger system will be put in place of the old system, of course the purchase and the set-up have to be taken care of A new system incurs significant expense, adding to the cost and inconvenience of removal and the sale of the old system.

The invention provides an extensible time division multiplexed pulse code modulation messaging system which is cost competitive even with very small capacities, and at which the cost of adding more Lines are relatively small compared to the increase in system size. A connection memory in a network circuit is assigned to a group of user terminals. The memory only has so many word storage spaces how time slots exist, and the word in each memory location only needs to be long enough to contain a user terminal address and accommodate a network circuit address. If the system is expanded, additional Network circuits connected to one another via a network trunking, but without any enlargement required in the word length of the connection memory is. A single time slot exchange circuit operates in the network circuit a sequential time slot exchange function that allows another conversation between excludes two user terminals as in opposite time slots from pairs of fixed time slots.

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A variety of user communication terminals is connected to a network circuit via an incoming and an outgoing transmission path. In the network circuit, the time slot exchange circuit is for exchanging information bits between the time windows of a fixed pair of time windows are connected in series between the two paths. A memory that has η word storage locations corresponding to η time windows is provided with user terminal addresses loaded. A time slot address generator cyclically generates time slot addresses in response to the clock signals. The time slot addresses cause the memory to provide user terminal addresses on a one-per-time slot basis submit. The individual user terminals respond to the specified .Endstelle addresses in that them an information bit. received from the outgoing path and transmitted an information bit on the incoming path .

To expand the system, a large number of network circuits are connected to one another via a network multiple line. Each network circuit includes a space switch. The room switch has a plurality of inputs that are connected to a plurality of paths in the network trunking. The space switch is responsive to a plurality of bits in an endpoint address from the memory in the manner that it comprises a I _n formations bit which appears on one of its inputs, transmits to its output.

According to the invention, a time division multiplex pulse code modulation message system is provided created that a wide variety of user

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end parts, a switching network and a control circuit device to control the production of transmission paths between the user terminals and the switching network for the transmission of information between specified user terminals. An incoming one Path or path carries information bits from the user terminal to the switching network and an outgoing one Path carries information bits from the switching network to the user terminals. The circuit tnetzxverk includes devices for transmitting individual bits of information, from which each is in a time window interval, from the incoming path to the outgoing path. The transmission devices comprise an exchange device for effecting a two-way exchange of information bits in fixed Pairs of time window intervals, whereby according to the requirements the control circuit device paths for the information bit transmission periodically between certain User terminals are created.

The invention also provides a method for operating a time-division pulse modulation communication system created as generally described above. Sequences of an even number η of time slot addresses are generated continuously. During the interval of occurrence of each time slot address, an information bit received from the incoming path. The received information bits are bilateral between fixed pairs exchanged at time slot intervals and transmitted on the outgoing path. One and the other user terminal become when one or the other of the time slot addresses occur

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fixed pair τοη time windows selected or enabled. Each selected user end is made to have one the information bits transmitted on the outgoing path to receive and to transmit an information bit on the incoming path in the order or priority the bit significance in the pulse code modulation word format advanced one place with respect to the significance of the information bit received from the outgoing path or is advanced. This procedure creates pulse code modulation words with m bits between the selected User terminals exchanged bit for bit in fixed pairs of time window intervals.

In one arrangement, the time slots of each fixed pair in each group (frame) become an even number η of time windows separated in time by n / 2 - 1 time window intervals. Each from a user terminal transmitted bit is delayed by n / 2 time slot intervals before it is received by a user terminal will.

In another arrangement, the time slots of each fixed pair are "adjacent" each other. Each of one Bit transmitted to the user terminal is delayed by η time window intervals plus or minus one time window interval, depending on whether the current time window is an even or odd number before this bit from a user terminal Will be received.

The invention is described below, for example, with reference to the drawing; in this shows:

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Pig. 1 is a block diagram of an invention according to en im Time-division multiplex switching system with pulse code demodulation,

Pig. Figure 2 is a detailed block diagram of part of Pig. 1,

Pig. Figure 3 is a detailed block diagram of part of Pig. 1,

Pig. Figure 4 is a detailed block diagram of a portion of Pig. 1,

Pig. Figure 5 is a detailed block diagram of a portion of Pig. 1 and.

Pig. 6 is a graphic representation of a pulse code modulation format; the one with the system from Pig. 1 is compatible.

The embodiment chosen as an example is shown with the help reproduced and described by functional circuit blocks, as each of the individual circuit functions is known and through integrated circuits available from stock or others readily known to the pachmann Circuits can be realized.

According to Pig. 1 is a central processing unit (CPU) 200 with network complexes 0 to 4 and a network trunk multiplexer 100 via a system address trunk 201, a system data subline 202, and a control subline 203 connected. The system address multiple

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Fachleitung 201 conveys address words τοπ of the central unit 200 to the rest of the system. The different parts of the system respond to individual addresses in such a way that that they establish a connection with the central processing unit 200 via the system data VJelfachleitung 202. The system data multiple line conveys command data words from central processing unit 200 to the rest of the system and conveys also data that arise or are formed in different parts of the system, back to the central unit 200. The control trunk line 203 is a group of lines, each of which has a specific signaling function exercises. For example, some lines in this multiple line are used for the central processing unit 200 the completion of various functions in the network complexes and the network trunking multiplexer 100 display. The central processing unit 200 may be a special purpose computer specific to the use has been designed in this system, or may be a suitably programmed general purpose computer.

Each network complex comprises groups of network circuits 10 and a peripheral interface unit (peripheral interface unit) 210. In Fig. 1, eight (0 to 7) Network circuits 10 from a peripheral interface unit (PIU) 210 served. The smallest possible system would be a peripheral interface unit 210 and network circuitry 10 own. A network trunking 16 is used to connect the network circuits 10 and one or to connect multiple service circuits like it for example in Pig. 5 is shown. The network trunk line 16 provides an output transmission path for each network circuit 10; in this case it goes up

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to a maximum τοη 16 paths. Are more than a network complex then there is a multiplicity of the network processing multiplexer 100 is required for a room and Delay holding between two or more Network multiple lines 16 to take care.

Pig. Figure 6 shows the pulse code division multiplexing IOrmat developed by System from Pig. 1 is used. A main frame "consists of m groups and each group consists of η individual time windows, each time window having first and last halves. Any path in the network trunk 16 is capable of 2n pulse code modulation words to be promoted in a main group. Each pulse code modulation word has a single information bit, which is in a prescribed half-time window in each of the groups. All network circuits 10 are able to transfer bits of information each to a path on the network trunk during the first half of a time slot, and are able to receive a bit of information from the network trunk to be received during both halves of a time window.

In a basic system, a peripheral interface unit (PIU) 210 generates system clock signals and group synchronization signals. In an extended system that includes more than one network complex, the Network multiplexer 100 takes these signals and provides them for each network complex over the system synchronization trunk 204 available. The communication between each peripheral interface unit 210 and the central processing unit (CPU) 200 takes place via the system address multiple line 201, the system

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Data trunk line 202 and control trunk line 203. Each peripheral interface unit 210 is for the central unit since 200 individually in response to a given one Address accessible, transmitted by the central processing unit on the system address trunk line 201 will.

Since the network complexes are identical, there is only one network complex described in detail. The time slot synchronization and the main group synchronization for the network circuits 10 are controlled by the peripheral interface unit (PIU) 210 via a synchronization Multiple line 217 accomplished. In addition to this timing function, the peripheral interface unit performs 210 also has a memory-buffer puncture for the transmission of signaling and monitoring information between the network circuits 10 and the central processing unit 200. Signaling is the network circuits 10 supplied in serial form via signaling lines 214 and 213 or from the network circuits 10 promoted away. Signaling information is between the peripheral interface unit 210 and the Central unit 200 in parallel via the system data multiple line 202 exchanged. The peripheral interface unit 210 performs at the same time a network circuit signaling scanning function the end. Access to each network circuit 10 is on an iterative basis under the control of a network address instead, which is generated in the peripheral interface unit 210. The network addresses are on the network circuits 10 are distributed over a network address trunk line 215. If access is made to a

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ner network circuit 10 by its unique or identifying network address, so it can display for signaling to the peripheral interface unit 210 via the signaling line 213 deliver. If this occurs, the scanning or query function is stopped at this loop address, until the signaling signals serially over the signaling line 213 are transferred.

Each network circuit 10 in a network complex is connected to the central processing unit 200 via the system address trunk 201, via the system data trunk line 202 and the control trunk line 203. Every Network circuitry 10 is also on line 12 with an incoming transmission device and over line 13 connected to an outgoing transmission device. Lines 12 and 13 carry pulse code modulation information bits between network circuits 10 and terminal control and buffer circuits 70 (TCB). Each terminal control and buffer circuit transmits the pulse code modulation information bits to and from the Terminal Interface Units (TIU) 301 and 302 or a bearer interface unit 400 via the Lines 12a and 13a. Terminal addresses and additional control signals are supplied by each network circuit 10 each of the terminal control and buffer circuits 70 via terminal control highways H. The terminal control and buffer circuits 70 decode the terminal addresses and the additional control signals around selected terminal interface units to select or control via the multiple line 71. Each of the terminal interface units 301 and 302

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has a user terminal assigned directly or indirectly to it. The maximum number of user terminals which can be actively linked in this way is through the number of available time windows limited, while the total number of user terminals is only limited by the smallest, acceptable quality of service is limited at the maximum expected traffic level.

Each of the terminal interface units serves to provide an interface for a special type of telecommunications equipment, such as e.g. B. analog and digital telecommunications offices, and for telecommunications terminals such. B. subscriber sets, key telephones and data terminals to form. For example, the terminal interface units 301 are shown in such a way that they are connected to a subscriber telephone station 500 and to a central office telephone line device 313. A terminal interface unit 302 and a button call station 311 were developed to take advantage of the features of the present embodiment. The keypad intercom 311 is connected to the terminal interface unit 302 via an analog voice loop ( ^J tvoice loop) and a double data line 304. However, this device is not the subject of the present disclosure and is described in greater detail in Canadian Patent Application Serial No. 211,515.

If required, two terminal interface units Exchange information, their respective terminal addresses are

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adjacent time window intervals by an assigned Network circuitry or circuits Information from line 13 and transmits information on line 12 during the time slot allotted to it. In a system that has η channels, the network switching is delayed effectively the information in each time window by η time window intervals plus or minus a time window interval. For example, the information received in time window two is sent to line 13 during the time window three applied, and the information received in time window 3 to line 13 during the time window two created.

Pig. 2 is a block diagram of a network circuit 10 from Pig. 1. The network circuit accomplishes the exchange of time slot information and room switching and supplies terminal addresses under the direction of the central unit (CPU) 200. In the present specific embodiment, the network circuit 10 may be comprised of two Parts are considered consisting of a network control circuit and a network switching circuit.

The control circuit part includes one. Counter 20 for the Generation of the time slot addresses, and a memory 23 and associated circuitry for the provision of the terminal addresses in response to the time slot addresses. The terminal addresses are stored in memory 23 written by the central processing unit 200 in response to changes in the state of the user terminals which the Network circuit 10 are assigned. The counter 20 is driven by system clock signals having a frequency of

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• Approximately 2 MHz, and of main group sync signals with a sub-resonance frequency of about 8 kHz from the synchronization trunk 217. The main group synchronization signals ensure that all network circuits 10 with one another are synchronized. The counter 20 counts the system clock signals and derives from them thirty-two time slot addresses at>. The appearance of thirty-two. Time slot addresses correspond to a group. Eight groups occur in the interval between two main group synchronization signals and thus ensure the transmission of pulse or demodulation words with eight bits. An address match comparator 21 is connected to a fixed network address determined by the spatial The arrangement of the network circuit OK in the system is determined, The fixed address is provided by fixed address lines 201a in all cases. The time slot addresses that are supplied via the lines 27 from the counter 20 in combination with the fixed address, are through the Comparator 21 is compared with a portion of the system address on system address trunk 201 to determine when a match occurs. Another part of the system address is in the input circuit of the comparator 21 is decoded to determine whether the system address is acceptable to a network circuit is. If the address is acceptable and a match occurs, the comparator 21 supplies a match signal to a logic memory selection circuit 22. Logic circuit 22 also takes 1 bit from system address trunk 201 and a read and Write request from central processing unit 200 via control multiple line 203.

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A memory 23 stores the terminal addresses, the required for controlling the operation of the network circuit 10 and the associated user terminals are. The memory 23 comprises thirty-two word storage locations for storing terminal addresses. The memory is accessed sequentially, as indicated by the time slot addresses on lines 27 from Counter 20 is set. In the presence of an agreement signal from the comparator 21 and a write request from the central processing unit 200, which is supplied via the control manifold 203, the Memory 23 by the control logic circuit 22 driven so that it has the state (state) of the data multiplex 202 in a memory storage location which is determined by the time slot address. Immediately after the memory 23 is activated drive circuit 22 also sends a "dun-it" signal on a line in the control trunk 203 to indicate to the central processing unit that the memory has been loaded. Through these devices the central unit 200 can transfer data to a network circuit at predetermined times and to memory locations provided Write in according to the time slot addresses.

There are two sources in the network circuit that are direct can be read by the central unit 200, namely the memory 23 and a counter 33, which later will have to be described. A read-out selection circuit 24 is connected to the memory 23 via lines 29 and to the Output of the counter 33 connected. The logic circuit generates a memory read signal or a read query signal depending on the state or level of the one

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Bits it receives from the address trunk. The logic circuit 22 generates this signal "in the presence of a match signal from the comparator 21 and a read request from the central unit 200, which is fed via the control multiple line 203. The readout selection circuit 24 responds to that read signal generated by the logic circuit 22 with a transmission of the output signal from the memory 23 or the Output signal from counter 33 on system data trunk line 202. Control logic circuit 22 sends as in the case of writing also "dun-it" signal to the central unit immediately after the output data from memory 23 or the data from counter 33 to, .-. of the trunk line 201 appear. In this pail, the "dun-it" signal from the central unit indicates that the data are available on multiple line 201.

The peripheral interface unit (PIU) 210 generates Network circuit addresses identified by a comparator 30 can be compared with the fixed address of a network circuit 10. If there is a match between the fixed address and the network connection address on, the comparator 30 supplies a release or control signal on a line 35. During the presence this enable signal occurs the signaling function between the peripheral interface unit 210 and a user terminal with incoming and outgoing lines 12 and 13 connected. A decoder 31 decodes the time slot addresses from the counter 20 on a line 36 when one occurs every time slot address 0 a time slot .O signal to create. Should the active signaling not continue

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leads, a logic gate 32 leads the time window 0 signal the counter 33 to. The counter 33 generates terminal query addresses. As described above, is the output signal of the counter 33 of the data multiple line 202 via the reading selection circuit 24 available.

The output of counter 33 and eight of lines 29 of the output of memory 23 are connected to a terminal address selection circuit 25 connected. The selection circuit 25 is controlled to be an interrogation address from the counter 33 in the presence of a time window O-SLgnals selects that with the selection circuit 25 over a lock gate 34 is applied. In the absence or non-existence of the time window O signal at the locking gate 34, circuit 25 selects eight bits of a terminal address from memory 23. During the signaling from the peripheral interface unit 210, the gate 34 is controlled via the sequence line 216 so that it has the passage the time window 0 signal for selection unit 25 blocks. Pole is the terminal address in the word storage location is selected for the time slot O address in memory 23 instead of the output of counter 33.

The selected address is sent over a terminal address trunk 28 from the output of the address selection circuit 25 to the input of an output buffer circuit 50 for the Transfer control multiple line. The buffer circuit 50 drives a terminal control trunk 14, the one terminal address multiple line 14e for conveying the terminal addresses to the terminal control and ' Buffer circuit (TCB) 70 as described in Pig. 3 shown.

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is. The system clock times two and main group synchronization signals are connected to the buffer circuit 50 via synchronization lines 217 connected. These signals are buffered and sent to the terminal control and buffer circuit 70 via lines 14c and 14b. A test control line Hd is from the output of the buffer circuit 50 connected to the terminal control and buffer circuit 70.

The switching portion of the network circuit 10 conveys and manipulates all appearing on lines 12 and 13 Pulse code modulation signals. A buffer circuit 49 drives the outgoing line 13. Each of the terminal interface units (TIU) replies to an alternately exclusively specified eight-bit terminal address, which is on the terminal address multiple line 14e appears. The terminal interface unit addressed during a specific time window receives information from the outgoing line 13 and transmits information on the incoming line 12. When a test control signal is present on test line 14d, the terminal interface unit transmits only the data from the line 13 on the line With this device, the speech path continuity can be checked by the network circuit 10 v / earth. Main group synchronization signals and symmetrical clock signals with twice the speed are fed to all terminal interface units via lines 14b and 14c, respectively, to the Codecs enable pulse code modulation information in a known way 'to decode and encode. The one on the

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incoming line 12 transmitted signals will, however in order of significance to a group with respect to that received from the outgoing line 13 Signals advanced.

From the terminal interface units to the incoming one. Signals transmitted on line 12 are serially received by the first stage of shift register 40. The information is shifted serially through the shift register 40 by the system clock signal which is applied to the shift register 40 via one of the lines 217. The shift register 40 is arranged so that the total time delay from the last stage of the shift register 40 through the system via lines 13 and 12 and through the shift register 40 is greater than the group length of the system by one time window interval. Since a group length is equal to thirty-two time window intervals, the delay of the η-th stage of the shift register 40 is therefore equal to thirty-three time window intervals. The information bits in the η-1 ien stage and the η + 1-th stage of the shift register 40 are connected to a time delay selection circuit 41. The time delay selection circuit 41 is controlled with the speed of the system clock by the least significant bit of the time slot addresses from the counter 20 so _s that they thirty-one (n - 1) or thirty-three (n + 1) time-window interval delays selects, depending on the Whether the time slot address is even or odd A bilateral or bilateral exchange of information bits between fixed pairs of time slots is achieved as a result, for example, as shown in the following abbreviated table:

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Time slot address Information bit sequence Delayed information bit sequence

0 1 2 2 4 5 30 31

0 12 3 4 5 30 31

10 3 2 5 4 31 30

Information bits that are in even-numbered time slot addresses fall are delayed by thirty-three timeslot intervals to match the odd timeslot addresses, and information bits falling in odd timeslot addresses are thirty-one timeslots delayed to match the even-numbered time slot addresses, so the time slots become two and three continuously exchanged, - time windows four and 5 continuously exchanged and so on. For example, a terminal with time slot two also receives the time slot information from one terminal the time slot three, while the time slot three terminal the time slot information from the time slot two terminal receives. The active user terminals are determined by the terminal addresses from the memory 23 and they are accessed as described above.

The output of the time slot delay selection circuit 41 is one of sixteen paths on the network trunk 16 connected. The network paths create the connections between terminals, the other network circuits assigned. All sixteen network paths enter a room switch 43 in each of the network circuits a. The space switch 43 is controlled by four data word bits that come directly from the output of the memory 23

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are connected here. An address selection function similar to that provided by the address selection circuit 25 is not required since the network trunk line 16 does not carry any supervisory signaling information. The space switch 43 accordingly selects one of the paths in the network trunk line 16 and supplies the information contained in the time slot to a half-time slot selection circuit 51 which is required for the operation of the network connection multiplexer 100, as will be described further below . The information contained in the time window appears at the output of the selection circuit 51 and is presented to the input of a normal test selection circuit 44. The circuit 44 responds to two bits on the lines 29 in such a way that it forwards either the information contained in the time window or the test information to a selection gate 45. As previously mentioned, when a terminal interface unit is tested under the control of a test signal on line 14d, it only forwards the test information from the outgoing line 13 to the incoming line 12. The normal test selection circuit 4Λ uses the test information it has generated together with the appropriate time slot information it receives to check or ensure the continuity of the terminal interface unit pulse code modulation speech path. The selection gate 45 accepts the information contained in the time window from the selection circuit 44 or the system signaling signals from the outgoing signaling line 214. The selection gate 45 generates system signaling signals at its output only when the

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Time window O decoded by the decoder 31 and a control signal is made available by the comparator 30. In all other cases the output signal will be from the normal test selection circuit 44 from the selection gate 45 via the buffer circuit 49 to outgoing line 13 forwarded.

In the foregoing description, the signaling circuits and -functions only insofar as it is necessary for the representation of the transmission of the normal information contained in the time windows is required between different terminal interface units was. A more detailed description of the signaling function now follows.

To the function of signaling from the peripheral To accomplish interface unit 210 to a terminal interface unit, the desired Terminal address from the system data trunk line loaded into memory 23 (at memory address 0, during time window 0). The peripheral interface unit 210 receives and stores the data content of the signaling from the central unit 200 via the system data Multiple line 202. A generated in the peripheral interface unit 210 and via the Sequence line 210 to the logic gate 34 control signal applied, that the logic gate 34 prevents the time slot zero signals from reaching the address selection circuit 25. Consequently, in time slot 0, the terminal address of the data in address memory location 0 of the memory becomes derived. The time slot 0 signals cause the selection gate 45 supplies the buffer 49 with the signaling data at each time window 0. The signaling data are

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from the peripheral interface unit 210 the outgoing signaling line 214 and the outgoing line 13 of the addressed terminal interface unit serially supplied until all signaling data have been transmitted.

So that a terminal interface unit provides signaling can send to the central unit 200, the terminal interface unit must first the peripheral Interface unit 210 indicate the need for signaling, and the peripheral interface unit must respond to this 210 itself a release or activation display to the terminal interface unit via the deliver outgoing signaling routine.

A terminal interface unit, to which an access has occurred, reports that there is a "1" bit enters into the time window 0 on the line 12. The "T" bit appears at the (n-i) th stage in the shift register 40, then it is transmitted to the logic gate 32 via a line 46. The logic gate 32 responds to this by that it prevents the O time slot signal from going to the counter to be directed. As a result, the query function is interrupted and with each following time window 0 there is continuous access to the same terminal interface unit, while the rest of the terminal interface unit is not accessed. The terminal interface unit which has been accessed continues to send the "1" bit in each subsequent time slot 0 until from. of the peripheral interface unit 210 another action is taken. The peripheral interface unit 210 continuously generates a cyclic sequence of

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Network addresses. If there is a match between a Network address and the fixed address for a network circuit, then the comparator 30 delivers a release or actuation signal for the logic gate 32 and an mLt a gate / buffer 37 provided via the line 35. When the price signal is present, the gated buffer 37 forwards the information on the time window 0 from the penultimate stage of the shift register 40 to the incoming signaling line 213 becomes the "1" bit from the peripheral interface unit 210 which causes the cyclic sequence of network addresses to be stopped and the current Network address is maintained for the duration of the following signaling sequence. The release signal from comparator 30 also causes selection gate 45 to signaling data during time window 0 from the peripheral interface unit (PIU) 210 via the signaling line 214. The peripheral Interface unit 210 activates the terminal to which the access is made by setting a predetermined one Sequence of serial data bits on the outgoing line 13 via the signaling line 214> the gate 45 and the buffer 49 sends. The terminal interface unit sends in response serial signaling data via the incoming line 12, the shift register 40, the buffer 37 and the outgoing signaling line 214 to the peripheral interface unit 210. The peripheral Interface unit 210 receives the signaling data over a consecutive series of time slots 0 and stores the data so that they can be accessed by the central processing unit 200 on request. Are the da-

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When saved, the peripheral interface unit is reversed 210 and the network circuit for normal query after a signaling function, until another signaling input or output sequence is initiated will.

Pig. 3 is a detailed block diagram of the terminal control and buffer unit (TCB) 70 and one of those in Pig. Terminal interface units 301 shown in FIG. 1. Each A terminal control and buffer circuit 70 is associated with network circuit 10. The terminal control and buffer circuit performs a pulse code modulation signal buffer function, a decoding function and a timing function for approximately 150 terminal interface units 301. The terminal control and buffer circuit 70 includes a pulse code modulation signal buffer 72 which acts as a relay amplifier (repeater) for pulse code modulation signals works. Outgoing and incoming pulse code modulation signals are switched between buffer 72 and a network circuit device 10 via an outgoing pulse code modulation line 13 or an incoming pulse code modulation line 12 connected as it did in the Pig. 1 and 2 is shown. Ground outgoing and incoming pulse code modulation signals between the buffer 72 and a codec 320 in each terminal interface unit 301 and a supervisory control circuit 330 in each terminal interface unit 301 via outgoing and incoming pulse modulation lines 13a and 12a, respectively.

The terminal control and buffer circuit 70 also includes a synchronization regenerator 75 and a decoder circuit 77 for terminal addresses. The terminal addresses

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Decoder circuit 77 receives the terminal addresses from of the network circuit 10 over the terminal address trunk 14e in the terminal control multiple line 14 and provides a single line drive signal in a control trunk 71 to the appropriate terminal interface unit 301 as determined by the content of each terminal address. Step unassigned time slots, then the content of the terminal address indicates that no trigger signal is generated will. The sync regenerator 75 receives main group sync signals and multiplied by two or double system clock signals tone of the network circuit 10 via lines 14-b and 14c of the terminal control multiple line 14. The synchronization regenerator 75 is using the double system clock signals instead of being supplied with the system clock signals, to perform the regeneration of precise timing signals to enable relatively simple circuits. The synchronization regenerator supplies power from these signals 75 the terminal interface units 301 with system clock signals, time window O display signals and Main group synchronization signals for phase 1 and phase 2 via lines in the control trunk line 71. Like in Pig. 6, phase 2 is offset from phase 1 by an advance of one group period. The signals from sync regenerator 75 are sent to codecs 320 and supervisory control circuitry 330 is supplied with the exception of the main group synchronization signals of phase 2, which are only supplied to the codec 320 are. In Pig 3, the terminal interface unit 301 contains a line circuit 340, which is connected to a subscriber station 500 via a participant loop 501

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connected is. However, there are changes to the line circuit 340 required in the other terminal interface units 301 in order to use these e.g. B. with 2-wire or 4-wire analog local or long-distance line systems associate. The line circuit 340 is with the codec 220 are connected via outgoing and incoming, analog voice lines 13b and 12b, respectively. The callsign (20 Hz) the office battery voltage and ground are provided to line circuit 340 on lines 334, 335 and 336, respectively.

In operation, each time a selection signal appears on the trunk line 170, the associated one Codec causes a pulse code modulation information signal bit and a pulse code modulation information signal bit to send. The significance value of each pulse code modulation information signal bit transmitted is determined by the phase 2 main group sync signals. The order of significance of each received pulse code modulation information signal bit is determined by the main group synchronization signals of phase 1. This compensates for inherent in the transmission of information contained in time slots between two terminal interface units Delay.

In the codec 320, analog voice tape signals from the subscriber station 500 via subscriber line 501, line circuit 340 and incoming line 12b receive. These analog signals are converted into pulse code modulation words for transmission on line 12a coded. Pulse code modulation information signal bits received on line 13a and to pulse code modulation words composed. The impulse demodulation

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Words are converted into speech tape signals and sent to the Subscriber call station 500 via the line circuit 340 and the subscriber loop 501 are sent out.

The line circuit 340 can be implemented using "known circuit elements. The exchange of information between the line circuit 340 and the supervisory control circuit takes place via the control lines 332. The line circuit 340 supplies the monitoring control circuit 330 with an indication of the status of the subscriber loop 501 and can be obtained from the monitoring control circuit 330 for the application of monitoring signals (for example the 20 Hz ringing signal) the subscriber station 500 can be controlled if necessary.

The supervisory control circuit 330 responds to a drive signal during the presence of a time slot O indication by sending or receiving serial signaling bits over lines 12a and 13a, like it above in connection with the Pig. 1 and 2 has been described. During a time slot O display, the codec 320 blocked against the receipt or transmission of an information bit.

The terminal control and buffer circuit 70 also includes a continuity test circuit 73> which responds to a predetermined signal state on test line 14d to the effect that that it causes the buffer 72 to transfer a bit of information from the outgoing line 13 to the incoming line 12 to transfer. By this device, a continuity test is performed by the normal test selection circuit 44 in FIG.

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Pig. 2 performed to the operational readiness of the lines 12 and 13 and the associated network circuit in Pig. 2 to be checked or verified.

In a typical system, the ends served ⁴ -Ellen control and buffer circuitry 70 up to 150 terminals interface units 301 and / or 302 in response to traffic considerations. In Pig. 1 shows a carrier interface unit 400 associated with a seventh terminal control and buffer circuit 70 which interfaces with a known T1 carrier arrangement. This arrangement is shown only to illustrate the versatility of the present switching system. This feature will only be mentioned below to show that the carrier interface unit 400 merely effects a regrouping (reframing) of the pulse code modulation words so that the switching system and the carrier device are compatible.

The network trunk line multiplexer 100 is more accurate in Pig. 4 shown. If a system is large enough to require more than 15 network circuits 10, additional circuits are required Network trunks required. This is in Pig. 1, the network trunks Plays NBO through NB4. The Hetzwerk multiple line ■ Multiplexer provides information path connections between the network multiple lines, in addition it has as practically established to produce all of the basic network complex timing function from multiplexer 100 allow. Pole the timing source is in subordinate to each peripheral interface unit 210 of a system synchronization source 110 if a multi-

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plexer is added to a system. The system synchronization source 110 supplies the system clock, the system clock times two or twice the system clock, the Main group synchronization and a local clock lock on suitable lines in the system synchronization trunk 204.

Each path in each network trunk has a separate one Input appearance on one of a group of bit stretching circuits (bit stretching circuits) 114. Each bit stretching circuit is controlled by the double system clock signals to have one bit of information during the first half of a Receives time window and outputs this information bit during the full time window.

The output of each bit stretcher circuit is connected to a space switch circuit 116. The circuit 116 is capable of time slot information from any path on any network trunk on any of four paths on any other jffetzwerk trunk transferred to. For example, each information path in the network trunk can be IBO on any of four selected paths on one of the network trunks NB1 to KB4 can be switched. It may also be dependent on the particular inter-network trunking traffic requirements other arrangements can be used.

The outputs of space switch circuit 116 are respectively with one of a group of selection switches 118 for the the last half of the time windows are connected, which duplicate those originating from the system synchronization source 110

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System clock signals are controlled in such a way that they receive information contained in time windows from the outputs of the Room switch 116 on the network trunks during the last half of each time window. To information tone other network trunk lines To receive assigned user terminals, the space switch 34 in FIG. 2 selects the required path in the Network multiple line during the required time window and forwards the information contained in the time window formation from this path to the input of the selection circuit 51 for half the time window. The selection circuit 51 transmits the information contained in the last half of the time window under the control of a signal on one of the lines 29 to the buffer 49.

The space switch 116 is controlled by data words that from a multiplex controller 112. The multiplex controller (multiplex controller) is so far the Control part of a network circuit 10 similar, as time slot addresses can be generated to control access to a memory provided by the central processing unit (CPTJ) via the trunks 201, 202 and 203 can be described.

Monitoring signals, dial tone signals, callback signals, etc. are typically required in every telephone system. In a pulse code modulation telephone system, these signals from a group of signal generators for generating analog signals like in a typical analog Telephone system can be generated. The analog signals are fed to one or more pulse code modulation encoders as required

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supplied and then at a suitable time and at a suitable Place inserted into the system.

In the Pig. 1 can be any of the network circuits 10 can be replaced by various functional circuits. A puncture circuit can have certain time windows Information signals contained on the Hetzwerk multiple line appear, further process or can information signals on the Unetwork trunk transfer. Such a circuit is a monitoring signal source, those in Pig. 5 is shown. The monitoring signal source includes a pest value memory (ROM) 62 for supervisory signal pulse code modulation words generated by a ROM control unit 63 in response to the Main group synchronization signals and the system clock signals is controlled via the synchronization line 217 can be received. All monitoring signals like z. The dial tone, busy tone, etc. required for use in the system are grounded in the Pest value memory 62 is stored in pulse code modulation format. The register value memory (ROM) 62 is controlled to contain all pulse code modulation supervisory tone signals Bit by bit on a pulse code modulation word line 64 provides. Each pulse code modulation supervisory tone appears on a dedicated line in the trunk line 64. Each bit of information is present for the full duration of a group; H. η time window intervals at. A monitoring signal controller 65 of the memory 23 and the associated circuit elements 20 to 24 in the network circuit from Pig. 2 is similar provides 66 addresses on an address multiple line for accessing and forwarding the pulse code modulation

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words from read-only memory 62. A monitoring signal room switch 67 generates information signal bits contained in time windows by having bits of pulse code modulation word en from the pulse code modulation word trunk in response to the addresses from the control device 65 selects only during the first half of time windows, such as that by the double system clock signals of one of the lines 217 is set. Each of the selected information signal bits is set to a predetermined one Transmit path in the network trunking. This is how the monitoring signal source in Pig generates. 5 Supervision tones using the pulse code modulation word formats of the system, as in Pig. 6 are compatible.

In operation as a time division multiplex telephone switching system with pulse code modulation, a simple telephone call follows a routing sequence of events. In the "0" time window, terminal interface units are addressed or queried by the network circuits 10 assigned to them. An off-hook telephone causes the assigned terminal interface unit to ^{send out a 11} 1 "bit in the time window" 0 "and thereby to stop the interrogation by the network circuit at the moment in which the relevant terminal interface unit is interrogated Signaling unit 210 responds to the interruption of the query in the network circuit by sending a "1" bit in the next time window "0" to the terminal interface unit. In the subsequent time window "0", the terminal interface unit serially signals the lifted ( off-hook) state of the subscriber telephone set to the

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peripheral signaling unit. When the signaling is complete, the peripheral signaling unit picks up the query of the other terminals again and sends an input interrupt signal to the central unit a line in the control trunk line 203. As soon as it becomes free, the central unit responds to the interrupt signal by receiving the signaled data and the terminal address data from the peripheral interface unit and the associated network circuit accepts. The central processing unit (CPU) then performs the following Steps from:

a) It loads the IT network circuit memory 25 in one Time slot address storage space with the terminal address, the terminal interface address and the address of the monitoring tone signal holding network path contains;

b) it loads the supervisory signal controller 65 in the same time slot address location with the address of the pulse code modulation dial tone words. Then the monitoring signal space switch expands the pulse code modulation dial tone signal with each recurrence of the time window from the read-only memory (ROE) to the route in the Metzwerk multiple line. Under the control of the network circuit memory becomes the Terminal interface unit selected or activated during each occurrence of the time window. The space switch expands under the control of the network circuit memory the corresponding network path on the outgoing line of the network, so that the Terminal interface unit the pulse code modulation

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Receives dial tone signal and an analog dial tone to Telephone set transmits.

When receiving a dial tone, the telephone set is switched off by the User operated in the usual manner so that he dials the desired telephone number. The voting is done in consecutive Transfer time windows "0". In the pail of Dialing pulses, each dialing pulse requires a series of consecutive "0" time slots to be transmitted. If necessary, the central unit receives the entire dialing information, identifies the network circuit that the selected party is assigned and loads the memory during a time window "0" with the address of the called party Participant. Depending on the central unit, the peripheral interface unit transmits during a time window 0 a ringing command to the terminal interface unit of the called subscriber in order to send a ringing button to the called subscriber Create telephone set. In the meantime, the calling subscriber receives a ringback tone from the monitoring tone signal circuit fed. If the called party picks up, the terminal interface unit stops, one Läutton apply, and the off-hook status becomes the peripheral signaling unit during the time window "0" which sends an interrupt signal to the central unit. If the signal unit is free, the central unit takes counteracts this information and responds to it by having it

a) blocks the callback connection from the tone signaling circuit and

b) the network circuit memory associated with each terminal with the terminal address and the network

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Loads the path address of the other participant.

The network circuit memory is provided with this information are loaded into adjacent time slot word storage locations, thereby enabling the system to generate a To build a speech path.

The structure and method of operation of the system creates a flexibility that allows adding different operations opportunities made possible. For example, a monitoring sound source, a music playback while waiting or a conference connection option can be provided that one of the Uetzwerkschaltungen through a Circuit for the operating option in question is replaced. Alternatively, these operational options can also be provided by circuits connected to a network circuit via the incoming and outgoing Ways is turned on. Such a circuit is described in Canadian patent application Fr.225,276.

The system uses a time delay for bits of information between time slots in fixed pairs of time slots to exchange. A time delay of n / 2 time slot intervals has been described, and a time delay has also been described described by η time window intervals plus or minus a time window interval. The latter has one result in some simplification in the software for the central unit compared to an n / 2 time delay. Thus, a time delay of η ± 1 time window intervals in conjunction with that of the exemplary Embodiment described.

According to the invention thus includes a time division multiplex

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Message system with pulse code modulation a variety of user terminals, a switching network and a Central unit for controlling the creation of transmission paths between the user terminals and the switching network for the transfer of information between specified user terminals. An incoming path carries information bits from the user terminals to the switching network and an outgoing path Information bits from the switching network to the user terminals. The switching network includes devices for Transmission of individual information bits, each of which is located in a time window interval, from the incoming Path to the outgoing path. The transfer device includes an exchange device for accomplishing a bilateral or bilateral exchange of information bits in fixed pairs of time window intervals, where paths for one information bit transmission periodically between individual user terminals be manufactured according to the central unit. Pulse code modulation words are thereby bit by bit exchanged between selected user terminals in fixed pairs of time window intervals.

- patent claims -

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Claims (1)

Claims e 1. ) Method for the exchange of pulse code modulation words, each of which comprises m information bits, between zv / ei user terminals in a time division multiplex message system with pulse code modulation, which is a switching network connected to a plurality of user terminals via an incoming path and an outgoing path comprises, characterized in that a) Sequences or poles of η time window addresses are generated, where η is an even number, b) that one bit of information from the incoming path during the interval of occurrence of each Time slot address is received, c) that the information bits received during the occurrence of even-numbered time slot addresses are transmitted or sent out with a delay of η + 1 time window address intervals, and that the during the occurrence of not counted Time slot addresses received information bits with a delay of η - 1 time slot address intervals be sent out, d) that the one user terminal each time a predetermined even-numbered time slot address occurs 709820/0369 is selected, e) that the other user terminal is dialed each time a time slot address occurs, which immediately follows each occurrence of the specified, even-numbered time slot address, f) that each selected user terminal is caused to one of the transmitted information bits from to receive outgoing path and to transmit an information bit on the incoming path, which is in the pulse code modulation word format relating to the information bit received from the outgoing path has moved up one place in the order of the bit significance, whereby pulse code modulation words with m bits between the time window intervals adjacent to one another in fixed pairs selected user terminals are exchanged bit for bit. Method of exchanging pulse code modulation words each comprising m bits of information between User terminals in a time division multiplex message system with pulse code modulation, the one Central unit for controlling the operation of the system and includes a Schalxnetzwerk, which has an incoming Path and an outgoing path connected to a plurality of user terminals, characterized in that a) Sequences or sequences of η time window addresses are generated, where η is an even number, 709820/0369 2851745 b) that a bit of information from the incoming path during the interval of occurrence of each time slot address is received, c) that the information bits received during the occurrence of even-numbered time slot addresses are transmitted or sent out with a delay of η + 1 time window address intervals, and that the information bits received during the occurrence of odd time slot addresses with a delay of η - 1 time window address intervals be sent out, d) that the terminal addresses from the central unit are stored in η word memory locations, each of which corresponds to one of the η time window addresses, and that a terminal address to the user terminals of each word storage location in Response to each occurrence of the corresponding time window address is transmitted or sent will, e) that each user ends in response to each occurrence their own, exclusive indstelle address is selected or activated that an information bit is received by the outgoing path, and that on the incoming path an information bit is sent out or transmitted in the order of the bit significance in the pulse co demodulation word format regarding the information bit that was received from the outgoing path, one position ahead 709820/0369 has moved, whereby pulse code modulation words comprising m bits Bit for bit between a user terminal for which, in a word memory location, which corresponds to an even terminal address, a terminal address, and another user terminal are exchanged for which there is a terminal address in the "adjacent word memory location which is the odd-numbered time-slot address immediately following the even-numbered time slot address is equivalent to. 3. The method according to claim 2, characterized in that that step (e) consists in extracting m information bits sequentially according to their significance during of each interval of a phase 2 timing signal is transmitted, and that m bits of information received in the same sequence during each interval of a phase 1 timing signal and that will continue f) the phase 1 timing signal and the phase 2 timing signal time slot addresses are generated in synchronization with the occurrence of sound, with the timing signals each comprise an interval of mn time window intervals and the phase 1 timing signal lags the phase 2 timing signal by η time window intervals. 4-. Method for the elimination of pulse code modulation words, each of which comprises m bits of information between a first and a second user terminal in an im Time division multiplex message system with pulse code 709820/0369 2B51745 modulation, which comprises a switching network with a plurality of user terminals via an incoming Path and an outgoing path is connected, characterized in that a) Sequences or sequences of η time window addresses are generated, where η is an even number, b) that one bit of information from the incoming path during the interval of occurrence of each time slot address Will be received, c) that the received information bits with a delay of n / 2 time slot address intervals transmitted or sent out, d) that during each occurrence one of the time slot addresses η a user terminal is controlled or selected, e) that the other user terminal is selected during the occurrence of each time slot address which is delayed from the other time slot address by n / 2 time slot address intervals, f) that each selected user terminal is caused to one of the transmitted information bits from the outgoing Path to receive and to transmit an information bit on the incoming path, which is in the order of precedence the bit significance in the pulse code modulation word IOrmat has moved one position with respect to the information bit received from the outgoing route, 709820/0369 through which. Pulse code modulation words with m bits between the selected user terminals are exchanged bit for bit in fixed pairs of time windows, where "with the respective time window intervals are separated by n / 2-1 between them. Time division multiplex messaging system with pulse code modulation with a plurality of user terminals, a switching network and a control circuit device for controlling the establishment of transmission paths between the user terminals and the Switching network for the transmission of information between specified user terminals, characterized by an incoming path (12, 12a) for transmitting information bits from the user terminals to the switching network, through an outgoing path (13, 13a) for transmitting information bits from the switching network to the user terminals, through devices (4-3) in the switching network for transmitting a individual bits of information, each of which is located in a time window interval, from the incoming path the outgoing path, and through an exchange device (40, 41) in the switching network between the input path and the transmission device is connected and serves to facilitate a bilateral exchange of information to effect bits in fixed pairs of time slot intervals, creating between certain user terminals In accordance with the control switching device, paths are periodically created for the transmission of information bits will. 709820/0369 Time division multiplex communication system with pulse code modulation for the exchange of pulse code modulations ons -words, each of which is m InformationsMts comprises between at least a first and a second user terminal from a large number of user terminals, which are connected to a switching network via an incoming path and an outgoing path are characterized by a device (20) for generating sequences of an even number η of time window addresses, by control devices (23, 50, 75, 77) for selecting or controlling the relevant user terminals during each occurrence of a predetermined, even-numbered time slot address and to dial the other user terminal during each occurrence of a time slot address, which immediately follows each occurrence of the predetermined, even-numbered time slot address by in which Memory devices (40) arranged in a switching network for receiving an information bit from the incoming path during the interval of each occurrence of a tent window address and by arranged in the switching network Devices (41) for transmitting the even-numbered time slot addresses during the occurrence received information bits with a delay of η - 1 time slot address intervals, and for transmission the information bits received during the occurrence of odd-numbered time slot addresses a delay of η + 1 time slot address intervals, and by located in each user terminal Devices (320) which respond to the control devices in such a way that they receive one of the transmitted information bits from the outgoing path and on the incoming 70 9820/0369 - vr- 8 the way a InformatlonsMt transmitted, which in the Ranking of bit significance in the pulse code modulation word format information bit received with respect to the Tom outgoing path is advanced by one position, as a result of which Pulse code modulation words with m bits between the selected user terminals bit for bit in fixed pairs be exchanged by neighboring time windows. Time division multiplex communication system with pulse code modulation with a switching network connected to a plurality of user end parts via an incoming Path and an outgoing path is connected, and with a central unit to control the exchange of pulse code modulation words, each of which comprises m information bits, between the user terminals, characterized by a device (20) for generating poles of an even number η of time window addresses, by a storage device (23) comprising η word storage locations, each of which has one corresponds to the η time slot addresses, and which is used to store terminal addresses from the central unit and a terminal address of each word location in response to each occurrence of the corresponding time slot address to send out to the end user, by storage devices provided in the switching network (40) which serve to take a bit of information from the incoming path during the interval of each occurrence to receive a time slot address by devices (41) provided in the switching network, which serve to send the information bits received during the occurrence of even-numbered time window addresses with a delay of η + 1 time window addresses 709820/0369 Send out intervals, and those during the occurrence Information bits received from odd-numbered time slot addresses with a delay of η - 1 Send out time slot address intervals by devices provided in each user terminal (320), which respond to each transmission of the terminal address exclusively provided for the user terminal as to respond that they have received an information bit from the outgoing path (13a) and on the incoming path (12a) transmit a bit of information ranked in order of bit significance in the pulse code modulation word format has advanced one place with respect to the information bit received from the outgoing path, whereby Pulse code modulation words comprising m bits, bit for bit, between the one user terminal for which a terminal address is in a word memory location corresponding to an even-numbered time slot address is located, and transmitted to another user terminal for which there is a terminal address is in the adjacent word memory location that corresponds to the odd-numbered time slot address, which immediately follows the even-numbered time slot address. 8. Time division multiplex message system with pulse code demodulation according to claim 7, characterized in that the storage device a shift register (40) having an input connected to the incoming path and first and second output connections each connected to stages in the shift register for accomplishing 709820/0369 has delays of η + 1 and η - 1 time slot intervals in the system, and that the transmission device a selection circuit (41) which is used to select an information bit for the transmission of either the first or the second output port in response to selecting whether the current timeslot address is odd or even. 709820/0369