DE10260823A1 - Integrated random-access memory circuit has data terminals for different regions of each memory bank coupled to common databus via single data line with anti-parallel write-in and read-out amplifiers - Google Patents

Abstract

The memory circuit has a number of memory banks, each having a number of addressable regions, each with more than 2 data terminals (A), for simultaneous write-in or read-out of information. The data terminals for different regions of each memory bank are coupled with a common databus via data paths each having a single data line (DL) containing an anti-parallel circuit (BA) with write-in and read-out amplifiers. A cross-bar matrix with selectively closed bidirectional switch groups (SG) is used to couple the data lines with the databus.

Description

The invention relates to an integrated RAM memory circuit according to the preamble of claim 1; the acronym RAM (Random Access Memory) Memory with random access for read / write operation. preferred, however not exclusive Field of application of the invention are dynamic RAMs (DRAMs), in particular those for designed to operate at a doubled (or even higher) data rate are.

RAMs with high storage capacity included several so-called "banks", which in some Distance to each other are integrated on a single chip and their each a big one Variety "z" of memory cells includes the matrix are arranged in rows and columns. There are a number of external connections (pins) on the chip provided to input and output data, address information for selection enter the memory cells and also clock and control information for the Create read and write operations. Various are also on the chip Decoding and control devices integrated to ensure that between the data pins and the addressed memory cells the necessary data connections for writing or reading are established become.

Each bank consists of one or a plurality of memory areas, each area having a plurality "n" of data ports to address to n Memory cells of the area concerned simultaneously n data in To be able to register or read out parallel form. The outer data pins usually form together with clock-controlled receive and transmit amplifiers, one bidirectional Parallel port to simultaneously multiple data bits in parallel form to be able to enter or output. This I / O port is over a branch of the supply system with the data connections the banks connected. The supply system starts at the I / O port with a central one n-bit parallel bus that branches to the individual banks.

If each bank as a single memory area is organized, i.e. only has a total of n data connections, the central bus only needs to branch to the various banks. In this case, it is enough a bank multiplexer that is dependent is controllable from the bank address to the central bus with the to connect each addressed bank. Is each bank in m> 1 selectively selectable disjoint Memory areas with n data connections each divided, then one additional Branch stage necessary, which contain a range multiplexer to the central bus with the selected area to connect to the respective addressed bank.

A division of the banks into two (or more) disjoint areas is required when the input and output of data on the I / O port is to be done at a data rate that is double (or several times) as high as the clock rate of the writer and reading at the banks. For some time now, DRAMs have been with: doubled data rate below the Description DDR DRAM (Double Data Rate DRAMs) already commercially available; recent developments to lead to DRAMs with four times the data rate (DDR-2 DRAMs) and future generations with yet higher Data rate should to be expected.

Generally, with a DRAM, the for m times Data rate is designed and is generally referred to here as "mDR-DRAM", in write mode during each Clock period m parallel n-bit data words in succession over the I / O port on the central n-bit bus and from there via a 1: m multiplexer, on m secondary distributed n-bit parallel buses. Each of these m secondary "area" buses branches to the individual banks, and that over the bank multiplexer to exactly one individually assigned area every bank. The m data words, which, in the course of a full cycle period, the different ones Reach area buses become temporary in latch circuits held and at the end of the clock period simultaneously assigned to the m Areas of the bank written by the bank multiplexer due to the Bank address selected is. Reading is running the opposite is true: in every cycle period are on simultaneously n memory cells in all m areas of an addressed bank read out, and the m different n-bit read data are read by Intermediate storage in the latch circuits on the m area buses held, then using the range multiplexer one after the other times the clock frequency to be routed to the I / O port.

That from the I / O port to the data connections of the Supply system leading benches, including the bank multiplexer and possibly the area multiplexer, is on the chip area in areas outside the Benches housed. In its last shows, in front of each bank, the supply system includes m * n parallel data paths (the symbol * is here and below for the Multiplication sign). Since the data is on its way between I / O port and the data connections the storage areas reinforced Need to become, it is necessary to line amplifiers to be provided at a suitable location, separately for data transfer in writing direction and for the data transfer in the reading direction. According to the current status of Technique it is common each of the m * n data paths between the last bus branch and the data connections of the Benches in split a write path and a read path and into each of them separate paths an amplifier for the to provide the relevant transfer direction.

As a result of this splitting into separate write and read paths, each of the last branches of the supply system contains 2m * n data lines. Already with DRAMs with a simple data rate and a common one Chen 16-bit data width at the I / O port, i.e. in the case of m = 1 and n = 16 (1DRx16-DRAM), a bundle of 32 parallel data lines must lead to each bank. With the currently frequently used DRAMs with double data rate and a 16-bit data width at the I / O port, ie in the case of m = 2 and n = 16 ("2DRx16-DRAM"), each bundle comprises 64 Data lines, and in the advanced 4DRx16 DRAMs each bundle 128 Data lines. Since the said data line bundles occupy their own space on the chip area, the larger the product m * n, the larger the overall dimension of the chip. However, a high value of m * n is desirable, since this value determines the effective data throughput (bits per unit time) of the memory circuit.

The object of the invention is to reduce the necessary dimensions of a chip which contains an integrated RAM memory circuit without having to reduce the maximum possible data throughput. This object is achieved by the features specified in claim 1 d he solved the memory circuit.

Accordingly, the invention is implemented on an integrated RAM memory circuit with several on one Chip banks arranged adjacent to each other, each of which m≥1 addressable Contains areas whose each has a plurality z of memory cells and n≥2 data connections in order to be connected to the respective addressed a simultaneous writing or reading of To enable data at n addressed memory cells in this area. Is exactly one area of at least two different banks assigned a common bus with n parallel bus lines. The n data connections of each area. about n Data paths, each of which has a first data line amplifier that can be switched on and off for data transfer in Write direction and a second on and off data line amplifier for data transfer in Reading direction contains connected to the assigned bus or via a switching device connectable. An operating control device is also provided, which in write mode only a write control signal for switching on the first data line amplifier for the addressed area and delivers a read control signal in read mode for switching on only the second data line amplifier for the addressed Area supplies. According to the invention, everyone contains Data path only a single-core data line, in the path of which the first and the second data line amplifier as an anti-parallel connection added is.

Thanks to the training according to the invention the memory circuit contain the data line bundles that branch off from the bus lines to the individual banks, only half as much many data lines as in the prior art. This is those of these bundles occupied areas on the chip only half as wide as before, so that the chip size for a given maximum bit width n and given factor m, which is the data rate co-determined, can be reduced. Conversely, it is possible to maximum bit width n or to double the data rate factor m without the Chip must be enlarged compared to the prior art.

Advantageous configurations and Further developments of the memory circuit according to the invention in the subclaims characterized.

A particular configuration concerns creating an easier one. Possibility, to the for a maximum bit width n designed memory circuit optionally also adapt to a data stream of smaller bit width, which only is a fraction of n. The number of memory cells in RAM banks mostly in disjoint elementary groups of k elements each divided. Usually is k = 4 (cell quadruple). Each address identified in the addressed Memory area of such a cell group, each of which only as a whole can be accessed. Access is by connecting the addressed cell group with a selected k-tuple of the n data connections of the relevant memory area.

Accordingly, the smallest possible bit width is for the Operation of such banks (and thus also for the Operation of the entire memory circuit) equal to k. The maximum bit width n must therefore be an integer multiple of k.

The reduction of each data path according to the invention between the data connections at the banks and the assigned bus lines on a single line It makes it easy to switch the memory circuit to one of several possible ones Adapt data bit widths that are in the range from k to n and are any multiples of k. To enable this adjustment are according to one advantageous embodiment the invention the anti-parallel circuits of the data line amplifier arranged the bank-side ends of the data lines, and the n Data lines of all those areas assigned to the same bus are on a common bundle merged from n data lines. Between the n data lines of the common bundle and the n lines of the A switching device is provided for the associated area bus which is a total of more than n / k disjoint groups each contains k bidirectional switches, which are controllable for Establishing different connection patterns between the one hand disjoint groups of k bus lines each and, on the other hand, individual groups of k data lines each.

To explain the invention in more detail the problems of the state of the following with reference to drawings Technology and two embodiments described the invention.

1 shows the schematic of a 2DRx16-DRAM of known design without the possibility of adapting the ef effective bit width.

2 shows the schematic of a 2DRx16-DRAM known type with switching device for adjusting the effective bit width.

3 shows the schematic of a 2DRx16 DRAM according to the invention without the possibility of adapting the effective bit width.

4 shows the schematic of a 4DRx16 DRAM according to the invention with switching device for adapting the effective bit width.

5 shows a control logic circuit for the in 4 Switching device shown to adjust the effective bit width.

6 shows the possible structure of one of the bidirectional switches, as in the switch groups of the embodiment 4 be used.

The drawings are similar Elements and signals of the same function with the same function Letters denoted, with a suffix to distinguish them is recreated from one or more numbering numbers. On Colon ":" between two numbers stands for the word "to". In the description the lowercase letter "i" is used as a proxy for one any bank number used.

The memory circuit after 1 contains four banks, of which only the bank due to the limited space on the drawing sheet 1 top left and the bank 2 are shown in fragments at the bottom left. Only part of the side edge of each of these banks on which the data connections A are located is shown. The bench 3 and the bank 4 you have to think at the top right and bottom right. The same applies to representation in the 2 . 3 and 4 , This arrangement of the banks corresponds to the actual arrangement in the four quadrants of a 4-bank memory chip.

All four banks of the memory circuit are of the same size and have the same structure. In the example after 1 is a dynamic RAM memory circuit that is designed for a bit width n = 16 and for double data rate, i.e. a 2DFx16 DRAM. Accordingly, each bank is divided into m = 2 disjoint areas (area 1 and area 2), each with n = 16 data connections AO to A15. Data connections are only shown at area 1; area 2 is only drawn in dash-dotted outline and compressed, without showing its data connections.

A switchable bank amplifier arrangement BAi is provided for each bank i, which contains bank write amplifiers and bank sense amplifiers. These amplifiers are located along the edges of the banks near the data connections because there is enough space there. Each data connection A is connected to the input of a sense amplifier and to the output of a write amplifier. All write amplifiers on the same bank i can be switched on together by a bank write signal WBi (write bank i), and the read amplifiers of bank i can be switched on together by a bank read signal RBi (read bank i). The signals WBi and RBi are generated at a clock rate f _c and depending on the bank address and on a write or read command. The switchable bank amplifier arrangements BA1: 4 can thus fulfill the function of a bank multiplexer.

The output of each sense amplifier on the bank is connected to an outgoing read data line RDL, and the input of each write amplifier at the bank is with one incoming write data line WDL connected. So every area a local bundle for each bank of n write data lines WDL0: 15 and a local bundle of n Read data lines RDL0: 15 assigned.

The four WDL local bundles of area 1 of the four banks 1: 4 are merged into a common WDL main bundle in the central space between the banks. In the same way, the RDL local bundles of area 1 of the four banks are merged into a common central RDL main bundle. The n lines of the WDL main bundle can be connected to the n lines of a first area bus BUS1 via a write switch arrangement WSN, which contains n switches each in the form of a transmission gate. The n lines of the RDL main bundle can be connected to the n lines of the area bus BUS1 mentioned via a read switch arrangement RSN, which also contains n switches. The n write switches WSN are closed only in the write mode of the memory circuit, and the n read switches RSN only in the read mode. The described connection paths between the data connections A of the bank areas 1 and the BUS1 together form a first data channel with a multiplexer function for the parallel transmission of n data bits.

In the same way as described above, the WDL and RDL local bundles of the areas are also 2 the benches 1 : 4 via specially assigned WDL and RDL main bundles and write or Read switch WSN or RSN can be connected to an assigned area bus BUS2. This second data channel is only represented by dash-dotted outline lines. The two area buses BUS1 and BUS2 are each connected via an n-bit latch to two n-bit branch connections of a 2-to-1 area multiplexer 2-MUX, whose n-bit collective connection is connected to the I / O port of the memory circuit connected is.

The memory circuit after 1 works as follows: In the write mode, the write switches WSN are closed in both data channels, and the write data are applied as successive n-bit parallel words with a repetition frequency 2f _c to the collective connection of the area multiplexer 2-MUX. The This multiplexer is switched with the frequency 2f _c , so that the successive write data words alternately reach the latch circuits on the two area buses BUS1 and BUS2. After receipt of a pair of write data, the write amplifiers at the addressed bank are briefly switched on, so that the two data words of the pair in question, which are temporarily stored in the latch circuits, are simultaneously written to the addressed bank, one in area 1 and the other in Area 2. The location within each area is determined by row and column address bits, both of which. Areas are assigned at the same time.

In the read mode, the read switches RSN are closed in both data channels, and in each period of the frequency f _c the sense amplifiers on the respectively addressed bank are temporarily closed in order to simultaneously read an n-bit data word from n addressed memory cells from the two bank areas. These two data words reach the two latch circuits on the area multiplexer 2-MUX via the respectively assigned area bus BUS1 or BUS2. Switching this multiplexer with the frequency 2 * f _c causes the data words to be output successively at the rate 2 * f _c on the I / O port.

In the 1 it can be seen that the two data channels between the buses BUS1 and BUS2 and the assigned areas of the banks occupy a wide space between the banks. At its widest point, each of the m = 2 data channels contains two parallel main bundles of n = 16 parallel lines, in each of which a switch must be inserted. In the room between the banks, 2m * n = 64 parallel lines must be accommodated, which creates space problems. Things become even more problematic if you want to create a way to change the effective bit width, as in the 2 is illustrated.

Even the memory circuit after 2 is a 2DRx16-DRAM and in this respect corresponds to the memory circuit 1 , when it contains four banks, each with two areas, each of which has n = 16 data connections, which are connected to the banks via separate write and read amplifiers and from there via separate write and read data lines to an assigned 16-bit area bus BUS1 or BUS2 are guided. Only the components of the data channel that is assigned to areas 1 of the four banks and BUS1 are shown in detail. The other data channel, which is assigned to areas 2 of the four banks and BUS2, is only drawn with dash-dotted outline lines.

The 2 illustrates the general organizational structure of the memory cells within the bank areas. Each bank area is divided into two disjoint "sections", each of which in turn is divided into two disjoint sub-sections, which are referred to here as "zones". Each zone comprises a large number of z / k disjoint groups, each of k = 4 memory cells, where z is the total number of barks within the area. The address part for the selection of a cell group within an area is thus composed of a section address bit, a zone address bit and a group address consisting of several bits.

A (in 2 mode controller (not shown) is adjustable such that it ignores either the section address bit and the zone address bit or only the zone address bit or none of these bits. In the first case, referred to here as "n / 1 mode", four cell groups are selected simultaneously by the group address, one in each of the four zones of the area. In the second case, referred to here as "n / 2 mode", the group address simultaneously selects two cell groups, one in each of the two zones of only that section which is determined by the section address bit. In the third case, referred to here as "n / 4 mode", the group address selects only a single cell group which lies in the zone of the section determined by the zone address bit of that section which is determined by the section address bit.

In the 2 each group of k = 4 data lines, which transmit the data of the same selected memory cell group, is summarized as a single thick line. Similarly, the n = 16 connections A0: 15 at each memory area are summarized as n / k = 4 groups A0: 3, A4: 7, A8: 11 and A12: 15, each of which contains k = 4 individual connections. Each of the amplifier symbols in 2 symbolizes a group of k = 4 parallel amplifiers connected to the k = 4. parallel lines of the assigned data line group are connected. The same symbolizes each in 2 drawn switch symbol a group of k = 4 parallel individual switches, which lie in the paths of the k = 4 parallel lines of the assigned data line group.

The main data line bundle of the data channel between the areas 1 of the banks and the associated area bus BUS1 contains, as in the case of 1 a bundle of n = 16 write data lines and n = 16 read data lines, each consisting of n / k = 4 groups of k = 4 lines each. A first write switch group WSG11 is used to connect the first WDL group WLG1, which is assigned to the four data connections A0: 3, to a first group BLG1 of four lines of the bus BUS1. A second write switch group WSG22 is used to connect the second WDL group WLG2, which is assigned to the four data connections A4: 7, to a second group BLG2 of four lines of the bus BUS1. A third write switch group WSG33 is used to connect the third WDL group WLG3, the four data connections A8: 11 is assigned, with a third group BLG3 of four lines of the bus BUS1. A fourth write switch group WSG44 is used to connect the fourth WDL group WLG4, which is assigned to the four data connections A12: 15, to a fourth group BLG4 of four lines of the bus BUS1.

In addition there are four further write switch groups provided: a fifth Write switch group WSG14 can be the first WDL group WLG1 with the connect fourth bus line group BLG4; a sixth write switch group WSG24 can be the second WDL group WLG2 with the fourth bus line group Connect BLG4; a seventh write switch group WSG13 can connect the first WDL group WLG1 to the third bus line group BLG3, and an eighth write switch group WSG34 can the third WDL group WLG3 connect to the fourth bus line group BLG4.

In a similar pattern as the eight write switch groups WSG between the four WDL groups WLG1: 4 and the four bus line groups are eight read switch groups RSG11, RSG22, RSG33, RSG44, RSG14, RSG24, RSG13 and RSG34 between the four RDL groups RLG1: 4 and the four bus line groups BLG1: 4 intended.

In addition there are four sense amplifier groups provided: between the read switch group RSG11 and the first Busleitungsg: cuppe BLG1 is a first sense amplifier group RAG1 by a mode-dependent Read control signal MR / 1 can be switched on; between the reading switch group RSG22 and the second bus line group BLG2 is a second sense amplifier group RAG2, which can also be switched on by the control signal MR / 1; between the read switch group RSG33 and the third bus line group BLG3 is a third sense amplifier group RAG3, which can be switched on by a control signal MS / 2, and between the read switch group RS44 and the fourth bus line group BLG4 is a fourth sense amplifier group RAG4, which can be switched on by a control signal MR / 4.

Table 1 below shows the switch-on pattern for the write and read switch groups WSG and RSG and for the sense amplifier groups RAG dependent from a chosen one Mode and dependent from addressing:

Table 1 read / write operation Fig. 2

In n / 1 mode, the effective one Bit width of the maximum bitbrit n = 16. Here are four memory cell groups addressed simultaneously, one in all four zones of the Storage area. All four bus line groups BLG1: 4 are seized. This corresponds to the normal mode of the 2DRx16-DRAM.

In n / 2 mode, the effective one Bit width n / 2 = B. Here two memory cell groups are used simultaneously addressed, one in each zone of only the addressed section. Only two of the four bus line groups are occupied, namely BLG3 and BLG4. The 2DRx16-DRAM is thus operated as a 2DRx8-DRAM.

In n / 4 mode, the effective one Bit width n / 4 = 4. Here, only one memory cell group is addressed at the same time, namely in the addressed zone of the addressed section, only one of the four bus line groups is used, namely BLG4. The 2DRx16-DRAM is thus operated as a 2DRx4-DRAM.

In 2 it can be clearly seen that the arrangement of the write and read switch groups WSG and RSG and the associated connecting lines takes up a lot of space. There are 2 * 8 = 16 switch groups with 4 parallel switches each, i.e. 64 parallel single switches, which must be inserted in 64 cable routes at the location of the switch system. In addition, the shown spatial parallel arrangement of the branches containing the switch groups requires a complicated layout on the chip. Since the other there too tenkanal, which is assigned to the area bus BUS2 and areas 2 of the banks, such an arrangement must be kept in the area between the banks at the location of the switch space for 128 line branches and the associated 128 individual switches. Did you want the in 2 To design the memory circuit shown for operation with four times the data rate, for which each bank would have to be divided into four areas and consequently four area buses and four data channels would have to be created, 256 line branches with 256 associated switches would have to be accommodated in the space between the banks.

With the present invention, the space requirement of the data feed system is significantly reduced, in general, both in RAMs with a single data rate (m = 1) and in RAMs with an arbitrarily multiplied data rate (m> 1), and also regardless of whether one Setting option for the effective bit width is created or not. This is based on the following 3 and 4 illustrated.

The 3 shows as an example a four-bank DRAM designed according to the invention for double data rate with the bit width n = 16 (ie a 2DRx16 DRAM), without setting the effective bit width. In this respect, the basic structure of the DRAM corresponds 2 the well-known DRAM 1 , The difference according to the invention is that only a single data line DL is laid between each of the n = 16 data connections A0: 15 of each of the m = 2 bank areas and the respectively assigned area bus BUS1 or BUS2 (instead of a line pair WDL and RDL as in FIG 1 ). In order to allow bidirectional operation for the read and write direction, an anti-parallel connection of two line amplifiers which can be switched on and off separately is inserted in the way of each of these n “single-wire” data lines DL, one of which is used as a write amplifier for data transfer in the write direction and the other as a sense amplifier serves for data transfer in the reading direction.

The respective anti-parallel connected amplifier pairs are preferably arranged near the bank-side ends of the n data lines DL, they form a bank amplifier block BAi with a total of m * n amplifier pairs at the bank i in question, whereby write amplifiers can be switched on jointly by a bank write command WBi and the sense amplifiers jointly by one Bank read command RBi can be switched on. Thus, the amplifier blocks BA on the four banks can also perform the function of the bank multiplexer, similar to the memory circuit shown in FIG 1 ,

The four local data line bundles (each n = 16 data lines DLL: 16), which are assigned to the first areas (areas 1) of the four banks, are brought together on a common main bundle of 16 data lines, which is fixed to the n = 16 lines 0 : 15 of the first area bus BUS1. In the same way, the four local data line bundles, which are assigned to the second areas of the four banks, are merged into a second main bundle, which is permanently connected to the n = 16 lines of the second area bus BUS1 (this second data channel is only drawn by its dash-dotted outline ). The two area buses BUS1 and BUS2 are, as in the case of 1 , each provided with an n-bit latch and selectively connectable to the I / O port of the memory circuit via a 2/1 area multiplexer 2-MUX. The control of this multiplexer and the generation of the control signals WBi and RBi for the amplifiers in the bank amplifier blocks BAi takes place in a known manner, as described above in connection with the 1 was described in order to carry out the write and read operation on the banks with double data rate.

Since each data line bundle in the two data channels after the memory circuit 3 contains only n (instead of 2n previously) parallel lines and the write switches and read switches in the main bundles are no longer required, the space requirement and the layout effort for the data supply system are significantly reduced.

The reduction of each data path in the data channels to a single-wire line can bring a particular advantage if an adjustment option for the effective bit width is to be created. The 4 shows as a further example a four-bank DRAM designed according to the invention for four times the data rate with the maximum bit width n = 16 (thus a 4DRx16 DRAM) and setting option for the effective bit width. In the 4 is, similar to in 2 , Each group of four data lines, which are assigned to a common group of k = 4 memory cells, are drawn as a single bold line, and each amplifier or switch symbol symbolizes a group of k = 4 parallel elements.

In 4 Each bank is divided into four disjoint areas, each consisting of 2 disjoint sections, each of which is in turn divided into 2 disjoint zones. Each area has n = 16 data connections A0: 15, divided into n / k = 4 groups A0: 3, A4: 7, A8: 11 and A12: 15. The four connections of each group are connected to the four lines of an assigned data line group via a pair of anti-parallel amplifiers in a bank amplifier block BAi. The assignment of the connection groups to the zones of the relevant bank area and the addressing and selection of the memory cell groups to be addressed via the connection groups is carried out in exactly the same way as described above using the 2 has been described.

The 4DRx16 DRAM after 4 has four n-bit area buses BUS1: 4 that can be selectively connected to the I / O port using a 4/1 area multiplexer. Each area bus is connected via an assigned, branching data channel to the n data connections of exactly one assigned area in the banks. The amplifier blocks BAi on the banks are by bank write and bank read commands WBi or RBi controllable and also serve as a bank multiplexer, similar to that described above. The write and read operation is similar to that in connection with the 2DRx16-DRAM 1 only that the area multiplexer is switched at four times the clock frequency f _{c in} order to connect the four area buses to the I / O port one after the other in each clock period and thus to enable a data rate of 4f _c at the I / O port. In the 4DRx16 DRAM 4 the necessary latch circuits are not arranged on the branch connections of the area multiplexer 4/1-MUX but are located elsewhere, as will be described later.

Each of the four data channels between the four area buses and the four areas of each bank has the same structure. Only the first one is shown in detail, assigned to the area bus BUS1 and areas 1 of the banks is. The other three data channels are only indicated with dash-dotted outline.

• (a) Es existiert eine Menge {P} von natürlichen Zahlen p_j, durch welche die Zahl n/k, also die Anzahl der Datenleitungsgruppen, ganzzahlig teilbar ist. Im dargestellten Fall n/k=4 besteht diese Menge aus den drei Zahlen p₁=1, p₂=2 und p₄=4. Jede Zahl p_j hat die Bedeutung eines möglichen Divisors, der angibt, welchem Bruchteil der maximalen Bitbreite die reduzierte effektive Bitbreite entsprechen soll.
• (b) Die Gesamtmenge der Schaltergruppen in der Matrix ist in mindestens zwei gleich mächtige Untermengen organisiert, die nicht disjunkt sind (also eine endliche Schnittmenge haben) und deren jede n/k Schaltergruppen umfasst.
• (c) Jede Untermenge ist für einen anderen Divisor p_j der Divisormenge {P} vorgesehen, wobei eine der Untermengen für den Divisor p₁=1 vorgesehen ist.
• (d) Jede der Untermengen ist organisiert in p_j gleich mächtige disjunkte Teilmengen dieser Untermenge, wobei die n/(k*p_j) Schaltergruppen jeder dieser Teilmengen angeordnet sind zum Verbinden von n/(k*p_j) vorbestimmten Auswahl-Busleitungsgruppen mit n/(k*p_j) Datenleitungsgruppen, die der betreffenden Schaltergruppen-Teilmenge individuell zugeordnet sind.

In the data channel under consideration, the local data line groups of areas 1 of all four banks are combined to form a main bundle, which therefore consists of n / k = 4 data line groups DLG1: 4. Each of these data line groups consists of k = 4 parallel, bidirectionally operated single-wire lines. The first data line group DLG1 is the zone 1 assigned to the responsible bank areas in section 1, DLG2 is the zone 2 assigned to section 1, DLG3 is the zone 1 assigned to section 2, and DLG4 is the zone 2 assigned to section 2. This data line bundle is crossed by a bus line bundle which consists of n / k = 4 bus line groups BLG1: 4. This crossover forms a matrix of (n / k) ² = 16 crossing points. At selected intersections there is a group of k = 4 bidirectional switches. Each of these switch groups is in 4 denoted by the letter combination SG and a trailing number of two digits, the first of which indicates the column position and the second of which indicates the row position in the matrix. The pattern of the locations of the switch groups can generally be described for any values of n and k as follows

• (a) There is a set {P} of natural numbers p _j , by which the number n / k, i.e. the number of data line groups, is divisible by an integer. In the illustrated case n / k = 4, this set consists of the three numbers p ₁ = 1, p ₂ = 2 and p ₄ = 4. Each number p _j has the meaning of a possible divisor, which indicates which fraction of the maximum bit width the reduced effective bit width should correspond to.
• (b) The total set of switch groups in the matrix is organized into at least two equally powerful subsets, which are not disjoint (i.e. have a finite intersection) and each of which includes n / k switch groups.
• (c) Each subset is provided for a different divisor p _{j of} the divisor set {P}, one of the subset being provided for the divisor p ₁ = 1.
• (d) Each of the subsets is organized into p _j equally disjoint subsets of that subset, the n / (k * p _j ) switch groups of each of these subsets being arranged to connect n / (k * p _j ) predetermined selection bus line groups to n / (k * p _j ) data line groups that are individually assigned to the relevant switch group subset.

In the example according to 4 a subset is provided for each of the three divisors p ₁ = 1, p ₂ = 2 and p ₄ = 4.

• The first subset, which is assigned to the divisor p ₁ = 1, comprises four switch groups SG11, SG22, SG33 and SG44, which are arranged to enable a connection of each data line group to exactly one individually assigned bus line group. In the case shown, these are the connections DLGI - BLG1, DLG2 - BLG2, DLG3 - BLG3 and DLG4 - BLG4. Because p ₁ = 1, this subset consists of only a "subset" that is identical to the subset.
• - The second subset is assigned to the divisor p ₂ = 2 and therefore comprises 2 disjoint subsets with 2 elements each. The first subset consists of the elements SG33 and SG44, which are arranged to establish the connections DLG3 - BLG3 and DLG4 - BLG4. The second subset of the second subset consists of the elements SG13 and SG24, which are arranged to produce the connections DLG1 - I3LG3 and DLG2 - DLG4.
• - The third subset is assigned to the divisor p ₄ = 4 and therefore consists of 4 disjoint subsets, each of which contains only 1 element. The first subset consists of the switch group SG14, which is arranged to establish the connection DLGI - BLG4. The second subset consists of the switch group SG24, which is arranged to establish the connection DLG2 - BLG4. The third subset consists of the switch group SG34, which is arranged to establish the connection DLG3 - BLG4. The fourth subset consists of the switch group SG44, which is arranged to establish the connection DLG4 - BLG4.

The switch groups in the matrix can be controlled according to an adjustable pattern in such a way that only a selected subset from exactly one selected subset of the switch groups is closed at the same time. The subset is selected depending on mode information indicating which one cher of the divisors p _j should apply to the storage mode. The selection of the subset within the selected subset takes place depending on a zone selection information which indicates which zone (or zones) in the addressed bank area is selected (or is selected together) by the address information. The zone selection information consists of 2 bits, namely the section address bit and the zone address bit.

According to the 4 an anti-parallel connection of a pair of bus amplifiers is inserted in the path of each bus line between the switch matrix and the continuing part of the area bus BUS1. In each pair of bus amplifiers, one acts as a write amplifier and the other as a sense amplifier. Each of the bus line groups BLG1: 4 is assigned one of the write amplifier groups WAG1: 4 and one of the sense amplifier groups RAG1: 4. The write amplifier groups are selectively switchable on and off depending on the mode information and on whether write or read mode is used. A control signal MR / 1 is used for the sense amplifier groups RAG1: 2, a control signal MR / 2 is used for the sense amplifier group RAG3, and a signal MR / 4 is used for sense amplifier groups RAG4. A control signal MW / 1 is used for the write amplifier groups WAG1: 2, a control signal MW / 2 is used for the write amplifier group WAG4, and a signal MW / 4 is used for write amplifier groups WAG4.

Table 2 below shows the tax pattern for the bidirectional switch groups SG in the switch matrix and for the write and sense amplifier groups WAG and RAG on the bus line groups BLG depending on a selected mode and dependent from addressing:

Table 2 Read / write operation Fig. 4

This control pattern is in principle similar to the control pattern as it is in Table 1 for the write and read switch groups WSG and RSG and for the sense amplifier groups RAG 2 is specified. However, because of the bidirectionally operated single-wire data lines and the use of bidirectional switches, the switching device can be kept spatially smaller. In particular, this offers in 4 The layout of the switching device shown as a matrix has the advantage that the arrangement is not only compact but can also be implemented in a very clear layout on the chip. Within this "crossbar" layout, it is relatively easy to arrange the positions of the switch groups in different patterns in order to select which of the n / p bus lines should be occupied in the different n / p modes.

Another special feature of the circuit example according to 4 consists in the fact that the latch circuits for the temporary storage of the write or read data are not connected centrally to the area bus, but decentrally to the local data line bundles. Since these bundles contain fewer lines than in the prior art, there is sufficient space for accommodating individual latch circuits, which for each local data line consists of a feedback loop made up of two inverters, as is known per se.

The 5 shows the schematic of a logic circuit for generating the switch-on commands for the bidirectional switch groups SG and the switch-on signals MW / 1, MW / 2, MW / 4 or MR / 1, MR / 2, MR / 4 for the selective activation of the write or. Sense amplifier groups WAG1: 4 and RAG1: 4 on the area bus. The logic circuit after 5 processes mode information consisting of 2 bits M1 and M2, furthermore the section address bit AB, the zone address bit ZB and a read / write command bit SB.

The mode information can be programmed on the chip by optionally closing or opening two connection paths C1 and C2, which are connected in series to a source of logic potential "1". This programming can be carried out by bonding (mechanical contact) or by fuse elements (fusible links), preferably in the "back end" of the chip production, ie after the chips have been separated from the wafer. In the n / 1 mode, ie when the chip is configured for the maximum bit width (here n = 16 data bits), both connection paths C1 and C2 are closed, so that the mode bit M1 is only "1" then. In n / 2 mode, i.e. when configuring the chip for bit width n / 2 (here 8 data bits), only C2 is closed, so that M2 is "1" and M1 is "0. 'In n / 4 mode, ie when the chip is configured for bit width n / 4 (here 4 data bits), C1 is open, so that only then Mode bits M2 is "0." This scheme is in a box in 5 shown.

Section address bit AB is "0" when section 1 is addressed and "1" when section 2 is addressed. The zone address bit ZB is equal to "0" if the zone 1 is addressed within any gate, and equal to "1" if the zone 2 is addressed. This corresponds to the entries in table 2 above. The write / read command bit SB is "1" in write mode and "0" in read mode.

The logic diagram after 5 , in which the usual symbols for AND gate (empty semicircle), OR gate (filled semicircle) and inversion (small circle) are used, is understandable in itself, so that no separate description is required. The output signals ESGxy lead to the control connections of the correspondingly designated switch groups SGxy in 4 (x is the number of the data group DLG and y is the number of the bus line group). With logic value "1", the switches of the relevant group are closed (conductive state), with logic value "0" they remain open (non-conductive state).

The control outputs MW / 1, MW / 2, MW / 4 and MR / 1, MR / 2, MR / 4 lead to the correspondingly designated control connections on the bus amplifier groups WAG or RAG 4 , The logic value "1" makes the relevant amplifier group effective (switched on), the logic value "0" makes it ineffective (switched off). In the n / 1 mode (maximum bit width), all control signals MW / 1, MW / 2, MW / 4 (write mode) or all control signals MR / 1, MR / 2, MR / 4 (read mode) are set to "1", so that all four amplifier groups WAG1: 4 or RAG1: 4 are switched on. In n / 2 mode (half the bit width), the two MW / 2, MW / 4 (write mode) or the two control signals MR / 2, MR / 4 (read mode) are set to "1" so that the two amplifier groups WAG2, WAG4 or RAG2, RAG4 can be switched on. In the n / 4 mode (quarter bit width), only the control signal MW / 4 (write mode) or MR / 4 (read mode) is set to "1", so that only the amplifier group WAG4 or RAG4 is switched on.

In the 6 a circuit example for a bidirectional switch "Sxy" is shown as it follows k times (in the present case four times) to implement the switch groups SGxy in the switch matrix 4 is used. The switch Sxy1 for connecting a data line DLx1 from any data line group DGLx is shown 4 with a bus line BLy1 from any bus line group BLGy 4 , The switch Sxy1 is a bidirectional "transfer gate", consisting of an N-channel field effect transistor N-FET and a P-channel field effect transistor P-FET, the source connections of both transistors being connected together, as are the drain connections. This parallel transistor connection lies between the lines DLx1 and BLy1. A control line that carries the control signal ESGxy for the switch group SGxy (from the logic circuit to 5 ) leads, is connected directly to the gate connection of the N-FET and, via an inverter INV, to the gate connection of the P-FET. This results in the following switching behavior: If ESGxy is brought to 0 volts (corresponds to the logic value "0"), both transistors are in the non-conductive state, and there is only an extremely high-resistance connection between DLx1 and BLy1, which in the technical sense is "no connection" applies. This is the "open" state of the switch. If ESGxy is brought to the value of the supply voltage (eg 2 volts) (corresponds to the logic value "1"), the two transistors are in the conductive state and a low-resistance connection is created between DLx1 and BLy1, which in the technical sense is the "closed state" of the Switch applies and it enables voltage levels and thus logic values "0" or "1" to be transferred from DLx1 to BLy1 and from BLy1 to DLx1.

All k switches Sxy1: k the same Switch group SGxy becomes the same control signal ESGxy at N-FET and its inverted version applied to P-FET. An INV inverter does not have to must be present in all k switches in the same group; for every A single inverter can suffice for the group receives the control signal ESGxy at the input and with its output the gate connections all P-FETs of the group in question are connected.

The above based on the 3 to 6 Circuit arrangements described are merely exemplary embodiments, to which the invention is of course not restricted. Various modifications and alternatives are possible within the scope of the inventive concept, of which only a few are mentioned below:
The memory circuit can also contain more or less than four banks. Even if there are only two banks, the reduction in space required for the branching data feed system achieved by the invention is advantageous. There is an advantage even if each bank consists of only one area (RAM for simple data rate); this case is also within the scope of the invention.

The numerical values for the number k of memory cells per addressable group is 4 for all common DRAMs However, the invention also includes conceivable other numerical sets for k. The maximum bit width n can also be smaller or larger than 16. In any case however, n must be an integer multiple of k.

The divisors p _j for the different effective bit widths n / p _j can be chosen as desired. In front preferably n = s ^x , and each of the numbers p _j is an integer power y <x of s, where s is a natural number ≥2. Preferably, s = 2. In a preferred embodiment, the set of numbers p _j comprises the set of all natural numbers 2 ⁰ ≥ 2 ^y ≥ 2 ^{x - 1} . The number of banks, the number m of areas per bank and the number k are preferably integer powers of 2.

In the 4 latch elements are only connected to a data line branch near a bank. Corresponding latch elements can also be located in the other data line branches at the same time. However, the invention is not limited to specific locations of the latch circuits. In each embodiment, whether with or without the possibility of adjusting the effective bit width, the latch circuits can be arranged on the data lines or close to the area multiplexer.

Furthermore, it should be mentioned that the in 4 additional anti-parallel circuits shown by write and read amplifiers in the paths of the bus lines can, if desired, also be blown away. On the other hand, such additional amplifiers can of course also be inserted if, as in the case of 3 , no switching device is provided for reduced effective bit width. In such a case, these amplifiers are only controlled by the write or read command.

A

Data connections to bank

FROM

Abschnittadressbit

BA

Bank amplifier block

BL

bus lines

BLG

Busleitungsgruppen

BUS

Bereichbus

C

programmable links

DL

(Read / write) data lines

DLG

groups of (read / write) data lines

I / O

Input / output port of the chip

IT G

control signal for switch groups

INV

inverter

M

mode bits

MR

control signal for sense amplifier groups

MW

control signal for write amplifier groups

N-FET

N-channel field effect transistor

P-FET

P-channel field effect transistor

RAG

Sense amplifier groups

RB

Bank read signal

RDL

Read data lines

RLG

groups of read data lines

RSG

Read switch groups

RSN

write switch

WAG

Write amplifier groups

WB

Bank write signal

WDL

Write data lines

WLG

groups of write data lines

WSG

Write switch groups

WSN

write switch

S

bidirectional switch

SB

command bit for writing or reading

SG

groups of bidirectional switches

For example,

Zonenadressbit

Claims (13)

Integrated RAM memory circuit with a plurality of banks arranged adjacent to one another on a chip, each of which contains m≥1 addressable areas, each of which has a multiplicity of z memory cells and n≥2 data connections (A) in order to simultaneously write or To enable reading of data at n addressed memory cells in this area, with - in each case exactly one area of at least two different banks being assigned a common bus with n parallel bus lines - the n data connections (A) of each area via n data paths, each of which is a first - and off baren data line amplifier for data transfer in the write direction and a second data line amplifier for data transfer in the read direction that can be switched on and off, connected to the assigned bus or can be connected via a switching device, - an operation control device is provided which, in write operation, provides a write control signal for switching on only the first one Provides data line amplifier for the addressed area and delivers a read control signal for switching on only the second data line amplifier for the addressed area in read mode. characterized in that each data path contains only a single-core data line (DL), in the path of which the first and the second data line amplifier are inserted as an anti-parallel connection (BA). The integrated memory circuit of claim 1, wherein any range from q≥1 Zones of the same size exist and the z / q memory cells of each zone each have a separate k-tuple of the n data connections (A) is assigned, with k = n / q, characterized in that that the anti-parallel connections of the data line amplifiers (BA) are arranged at the bank-side ends of the data lines (DL) and that the n data lines (DL) of all those areas that the are assigned to the same bus on a common bundle (DLG1: 4) merged from n data lines are and that between the n data lines of the common bundle (DLG1: 4) and the n bus lines (BLG1: 4) a switching device (SG11: 44) is provided which is a total of more a1s n / k disjoint groups (SG) each consisting of k bidirectional switches contains which are controllable for producing different connection patterns between individual disjoint groups (BLG) of each k bus lines and, on the other hand, individual groups (DLG) of each k Data lines that are assigned to individual zones. Integrated memory circuit according to Claim 2, characterized in that the number n / k of data line groups (DGL1: 4) is an integer multiple of at least one natural number p _j ≥1 and that the total number of switch groups (SG11: 44) forms at least two subsets , each of which comprises n / k switch groups, and that each subset is provided for a different number p _j , one of the subset being provided for the number p _j = 1, and that each of the subset is organized in p _j equally disjoint subsets of this subset, the n / (k * p _j ) switch groups of each of these subsets being arranged to connect n / (k * p _j ) predetermined selection bus line groups to n / (k * p _j ) data line groups corresponding to the switch group concerned. Subset are individually assigned. Integrated memory circuit according to Claim 2 or 3, characterized in that n = s ^x and that each of the numbers p _{j is} an integer power y <x of s, where s is a natural number ≥2 Integrated memory circuit according to Claim 4, characterized in that the set of numbers p _{j is} the set of all natural numbers 2 ⁰ ≥ 2 ^y ≥ 2 ^{x- 1} . Integrated memory circuit according to claim 4 or 5, characterized in that s = 2. Integrated memory circuit according to one of Claims 3 to 6, characterized that the common bundle of Groups of data lines (DLG1: 4) and the bundle of groups of bus lines (BLG1: 4) in the area of the switching device each as a bundle of parallel faulty lines is laid, so that the two bunch cross each other in isolation and the total number of crossings an n-by-n matrix between each data line and a bus line forms, and that each of the bidirectional switches (Sxy) is spatially close the intersection of the two lines to be connected by him is. Integrated memory circuit according to one of Claims 3 to 7, characterized in that the operation control device contains a switch control logic which is connected to receive the following input information: - Mode information (M1, M2) which specifies which of the numbers p _j for the operation of the memory circuit should be effective; a zone information (AB, ZB) derived from the address information of the memory circuit, which indicates which zones of the addressed area are addressed by the address information in order to close the switch groups (SG11: 44) on precisely those data line groups (DLG) that the are addressed to the respective zones. Integrated memory circuit according to claim 8, characterized characterized in that by way of each bus line group (BL) a write amplifier group (WAG) for the data transfer in the write direction and, in parallel, a sense amplifier group (RAG) for the data transfer is inserted in the reading direction. Integrated memory circuit according to claim 9, characterized characterized in that the operational control device has an amplifier control logic contains to the write control signal, the read control signal and the mode information (M1, M2) responds to for the write or read operation amplifier switch-on signals (MW or MR) which the bus line amplifiers only select the bus line group (s) turn. Integrated memory circuit according to one of the preceding Expectations for one Operation with a data rate equal to an integer multiple Z2 the write and read clock rate, the number m of areas is equal to this multiple in each bank and in each case overall m Areas belonging to the same bank or to different banks at the same time are addressable, but are assigned to different buses, characterized in that on each data line (DL0: 15) one Latch circuit is connected to that transmitted on the data line (DL0: 15) Caching the date on demand. Integrated memory circuit according to Claim 11, characterized in that m ≥ 2 is. Integrated memory circuit according to Claim 12, characterized in that m <2 and is equal to an integer power of 2.