DE102012110382A1 - Substrate i.e. printed circuit board, for electrical circuits and/or modules, has stop structure extending up to level of adjacent exposed outer surface of metallization regions or surface of end layer projects above level - Google Patents
Substrate i.e. printed circuit board, for electrical circuits and/or modules, has stop structure extending up to level of adjacent exposed outer surface of metallization regions or surface of end layer projects above level Download PDFInfo
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- DE102012110382A1 DE102012110382A1 DE102012110382A DE102012110382A DE102012110382A1 DE 102012110382 A1 DE102012110382 A1 DE 102012110382A1 DE 102012110382 A DE102012110382 A DE 102012110382A DE 102012110382 A DE102012110382 A DE 102012110382A DE 102012110382 A1 DE102012110382 A1 DE 102012110382A1
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- layer
- oxide
- metallization
- substrate
- stop structure
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- 239000000758 substrate Substances 0.000 title claims abstract description 90
- 238000001465 metallisation Methods 0.000 title claims abstract description 76
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000002184 metal Substances 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 37
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- 229910052802 copper Inorganic materials 0.000 claims abstract description 25
- 239000010949 copper Substances 0.000 claims abstract description 25
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 19
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 239000011888 foil Substances 0.000 claims abstract description 10
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- 229910000679 solder Inorganic materials 0.000 claims description 95
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 48
- 229910052759 nickel Inorganic materials 0.000 claims description 24
- 238000005476 soldering Methods 0.000 claims description 23
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 21
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- 239000010931 gold Substances 0.000 claims description 21
- 239000000919 ceramic Substances 0.000 claims description 19
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 18
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 16
- 238000013532 laser treatment Methods 0.000 claims description 16
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- 239000000853 adhesive Substances 0.000 claims description 10
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- 229910000431 copper oxide Inorganic materials 0.000 claims description 7
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 7
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 7
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 7
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- 239000000126 substance Substances 0.000 claims description 7
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 7
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- 229910000480 nickel oxide Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229920000049 Carbon (fiber) Polymers 0.000 claims description 5
- 239000004917 carbon fiber Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 5
- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims description 5
- 229920002430 Fibre-reinforced plastic Polymers 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
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- 229910001316 Ag alloy Inorganic materials 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
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- 239000011203 carbon fibre reinforced carbon Substances 0.000 claims description 2
- 229910000990 Ni alloy Inorganic materials 0.000 claims 1
- 150000001879 copper Chemical class 0.000 claims 1
- 229960004643 cupric oxide Drugs 0.000 description 6
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- 229910000881 Cu alloy Inorganic materials 0.000 description 2
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- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 description 2
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical compound [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 description 2
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- BUHVIAUBTBOHAG-FOYDDCNASA-N (2r,3r,4s,5r)-2-[6-[[2-(3,5-dimethoxyphenyl)-2-(2-methylphenyl)ethyl]amino]purin-9-yl]-5-(hydroxymethyl)oxolane-3,4-diol Chemical compound COC1=CC(OC)=CC(C(CNC=2C=3N=CN(C=3N=CN=2)[C@H]2[C@@H]([C@H](O)[C@@H](CO)O2)O)C=2C(=CC=CC=2)C)=C1 BUHVIAUBTBOHAG-FOYDDCNASA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 238000000637 aluminium metallisation Methods 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
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- 229910052758 niobium Inorganic materials 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
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- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09909—Special local insulating pattern, e.g. as dam around component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0315—Oxidising metal
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
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Abstract
Description
Die Erfindung bezieht sich auf ein Substrat, insbesondere in Form einer Leiterplatte, gemäß Oberbegriff Patentanspruch 1 sowie auf ein Verfahren zum Herstellen eines Substrates, insbesondere in Form einer Leiterplatte, gemäß Oberbegriff Patentanspruch 10.The invention relates to a substrate, in particular in the form of a printed circuit board, according to the preamble of
Substrate in Form von Leiterplatten bestehend aus einer Isolierschicht aus einem polymeren Material und/oder aus Keramik, aus wenigstens einer mit einer Oberflächenseite der Isolierschicht verbundenen und zur Ausbildung von Leiterbahnen, Kontakten, Kontakt- oder Befestigungsbereichen strukturierten Metallisierung sind in verschiedensten Ausführungen bekannt. Bekannt ist hierbei auch, solche Bereiche der Metallisierung (nachstehend als Löt- oder Bondbereiche bezeichnet), die für eine Verbindung von Anschlussleitungen, Schaltungs- oder Modulkomponenten usw., insbesondere auch für eine Verbindung von elektrischen Bauteilen und/oder deren Anschlüsse durch eine Löten vorgesehen sind, seitlich mit einer, eine Barriere für das flüssige Lot bildenden Lötstoppstruktur zu versehen. Üblicherweise bestehen diese Lötstoppstrukturen aus einem Auftrag oder aus einer Schicht aus einem polymeren und/oder anorganischen Material und müssen in einem relativ aufwendigen Verfahren aufgebracht werden. Nachteilig ist hierbei insbesondere, dass für das Aufbringen der bekannten Lötstoppstrukturen mehrere zusätzliche Verfahrensschritte erforderlich sind, dass die bekannten Lötstoppstrukturen bei Verwendung eines polymeren Materials eine nur geringe Temperaturbeständigkeit aufweisen und bei Verwendung eines anorganischen Materials ein zusätzlicher, die Herstellungskosten des Substrates verteuernder Einbrennschritt erforderlich ist, der in der Regel auch einen speziellen Ofen erfordert. Weiterhin enthalten die für Lötstoppstrukturen verwendeten bekannten Lacke oder Paste grundsätzlich Lösungsmittel, die insbesondere auch beim Einbrennen verdampfen und eine Belastung der Umwelt darstellen. Weiterhin ist die Einhaltung eines gewünschten Layouts für die jeweilige Lötstoppstruktur vielfach schwierig und die angestrebte Qualität der Haftung der Lötstoppstruktur auf dem Substrat wird vielfach nicht erreicht.Substrates in the form of printed circuit boards consisting of an insulating layer of a polymeric material and / or of ceramic, at least one connected to a surface side of the insulating layer and to form interconnects, contacts, contact or mounting areas structured metallization are known in various designs. It is also known, such areas of metallization (hereinafter referred to as soldering or bonding areas), which provided for a connection of leads, circuit or module components, etc., in particular for a connection of electrical components and / or their connections by soldering are to be provided laterally with a, a barrier for the liquid solder forming solder stop structure. Usually, these solder stop structures consist of an order or of a layer of a polymeric and / or inorganic material and must be applied in a relatively expensive process. The disadvantage here is in particular that for the application of the known Lötstoppstrukturen several additional process steps are required that the known Lötstoppstrukturen using a polymeric material have only low temperature resistance and when using an inorganic material, an additional, the production cost of the substrate more expensive burn-in is required which usually also requires a special oven. Furthermore, the known paints or pastes used for solder resist structures generally contain solvents which, in particular, also evaporate during stoving and represent a burden on the environment. Furthermore, compliance with a desired layout for the respective solder stop structure is often difficult and the desired quality of the adhesion of the solder stop structure on the substrate is often not achieved.
Bekannt sind auch Verfahren zum Herstellen von Substraten in Form einer Leiterplatten für elektrische Schaltungen und/oder Module (
Bekannt ist weiterhin das sogenannten „DCB-Verfahrens” (Direct-Copper-Bond-Technology) beispielsweise zum Verbinden von Metallschichten oder -blechen (z. B. Kupferblechen oder -folien) mit einander und/oder mit Keramik oder Keramikschichten, und zwar unter Verwendung von Metall- bzw. Kupferblechen oder Metall- bzw. Kupferfolien, die an ihren Oberflächenseiten eine Schicht oder einen Überzug (Aufschmelzschicht) aus einer chemischen Verbindung aus dem Metall und einem reaktiven Gas, bevorzugt Sauerstoff aufweisen. Bei diesem beispielsweise in der
Dieses DCB-Verfahren weist dann z. B. folgende Verfahrensschritte auf:
- • Oxidieren einer Kupferfolie derart, dass sich eine gleichmäßige Kupferoxidschicht ergibt;
- • Auflegen des Kupferfolie auf die Keramikschicht;
- • Erhitzen des Verbundes auf eine Prozesstemperatur zwischen etwa 1025 bis 1083°C, z. B. auf ca. 1071°C;
- • Abkühlen auf Raumtemperatur.
- • Oxidizing a copper foil so that a uniform copper oxide layer results;
- • placing the copper foil on the ceramic layer;
- • Heating the composite to a process temperature between about 1025 to 1083 ° C, z. B. to about 1071 ° C;
- • Cool to room temperature.
Bekannt ist weiterhin das sogenannte Aktivlot-Verfahren (
Der Erfindung liegt die Aufgabe zugrunde, ein Substrat aufzuzeigen, welches die vorgenannten Nachteile vermeidet und bei dem die jeweilige Lötstoppstruktur zeitsparend und kostengünstig hergestellt ist. Zur Lösung dieser Aufgabe ist ein Substrat entsprechend dem Patentanspruch 1 ausgebildet. Ein Verfahren zum Herstellen des Substrates ist Gegenstand des Patentanspruchs 10. The invention has for its object to provide a substrate which avoids the aforementioned disadvantages and in which the respective Lötstoppstruktur is made time-saving and inexpensive. To solve this problem, a substrate according to
Der besondere Vorteil der Erfindung besteht u. a. darin, dass die jeweilige Lötstoppstruktur bzw. das jeweilige Lötstoppmuster ohne aufwendige Verfahrensschritte, ohne zusätzliche Arbeitsmittel und ohne Umweltbelastung hergestellt werden kann, und zwar mit einer optimalen Haftung der Lötstoppstruktur an dem jeweiligen Substrat bzw. der Metallisierung. Weiterhin kann die Lötstoppstruktur durch Steuerung der Relativbewegung zwischen dem Substrat und dem Laserstrahl problemlos und beispielsweise programm- und/oder computergesteuert in dem gewünschten Layout erzeugt werden, insbesondere auch in einer feinen und differenzierten Form. Lösungsmittel und die damit verbundene Umweltbelastung werden mit der Erfindung vermieden.The particular advantage of the invention is u. a. The fact that the respective Lötstoppstruktur or the respective Lötstoppmuster can be prepared without complex process steps, without additional equipment and without environmental pollution, with an optimal adhesion of the Lötstoppstruktur to the respective substrate or the metallization. Furthermore, by controlling the relative movement between the substrate and the laser beam, the solder stop structure can be produced without problems and, for example, program-controlled and / or computer-controlled in the desired layout, in particular also in a fine and differentiated form. Solvent and the associated environmental impact are avoided with the invention.
Die Erzeugung des die Lötstoppstruktur bildenden Metalloxids erfolgt bevorzugt derart, dass das Metalloxid zumindest bis an das Niveau einer angrenzenden freiliegenden Metallfläche reicht, bevorzugt über dieses Niveau vorsteht. Die Hitzeeinwirkung (z. B. Lasern) erfolgt auf jeden Fall so, dass kein Materialabtrag oder im Wesentlichen kein Materialabtrag (z. B. durch Verdampfen), weder am Substrat bzw. an der Isolierschicht, noch an der jeweiligen Metallisierung erfolgt. Dies gilt auch dann, wenn die Metallisierung zusätzlich mit wenigstens einer äußeren metallischen Abschlussschicht versehen ist, d. h. die Metallisierung beispielsweise aus Kupfer oder Aluminium besteht und als Abschlussschicht mit eine Nickelschicht oder mit einer Nickelschicht und einer äußerer Goldschicht versehen ist. In Um dies zu erreichen und einen Materialabtrag bzw. Metallabtrag (z. B. durch Verdampfen) zu vermeiden, ist es erforderlich, dass die Hitzebehandlung (z. B. Lasern) in einer Atmosphäre erfolgt, deren Sauerstoffgehalt nicht unter 10% liegt. Im Falle einer Abschlussschicht aus Nickel ist das die Lötstoppstruktur bildende Metalloxids u. a. Nickeloxid. Dies gilt auch im Falle einer Abschlussschicht aus innen liegender, bzw. an die Metallisierung angrenzender Nickelschicht und äußerer Goldschicht, wobei das Nickel hierbei durch die Goldschicht diffundiert. Bevorzugt ist die Hitzeeinwirkung (z. B. Lasern) für die Erzeugung der Lötstoppstruktur so eingestellt, dass bei einer Abschlussschicht nur oder im Wesentlichen deren Oxid die Lötstoppstruktur bildet.The production of the metal oxide forming the solder stop structure preferably takes place in such a way that the metal oxide extends at least as far as the level of an adjacent exposed metal surface, preferably protruding above this level. In any case, the effect of heat (eg lasers) is such that there is no removal of material or essentially no material removal (eg by evaporation), neither at the substrate or at the insulating layer, nor at the respective metallization. This is true even if the metallization is additionally provided with at least one outer metallic end layer, d. H. the metallization consists for example of copper or aluminum and is provided as a final layer with a nickel layer or with a nickel layer and an outer gold layer. In order to achieve this and to avoid material removal or metal removal (eg by evaporation), it is necessary that the heat treatment (eg lasers) takes place in an atmosphere whose oxygen content is not less than 10%. In the case of a final layer of nickel, the metal oxide forming the solder stop structure u. a. Nickel oxide. This also applies in the case of a top layer of internal nickel layer or metal layer adjacent to the metallization and outer gold layer, wherein the nickel diffuses through the gold layer. The heat action (eg lasers) for the production of the solder stop structure is preferably adjusted such that only or essentially its oxide forms the solder stop structure in the case of a terminating layer.
Bei einer besonderen Ausführungsform ist das jeweilige Substrat Bestandteil eines als Mehrfachnutzen hergestellten Mehrfachsubstrates, bei dem auf einer großformatigen Isolierschicht mehrere Einzelsubstrate bzw. deren Metallisierungen durch Strukturieren von auf die Isolierschicht aufgebrachten Metallschichten oder Metallfolien erzeugt sind, wie dies beispielsweise in der
In Weiterbildung der Erfindung ist das Substrat beispielsweise auch so ausgebildet,
dass die wenigstens eine Metallisierung zumindest teilweise von einer Kupferschicht, vorzugsweise von einer Kupferschicht mit einer Dicke im Bereich zwischen 0,015 mm bis 0,8 mm und die Oxidschicht von einem Kupferoxid, vorzugsweise mit einer Dicke im Bereich zwischen 0,00015 mm bis 0,1 mm gebildet sind,
und/oder
dass die wenigstens eine Metallisierung zumindest teilweise von einer Schicht aus Aluminium, vorzugsweise mit einer Dicke im Bereich zwischen 0,015 mm bis 0,8 mm und die Oxidschicht von Aluminiumoxid, vorzugsweise mit einer Dicke im Bereich zwischen 0,005 mm bis 0,1 mm gebildet sind,
und/oder
dass die wenigstens eine Metallisierung wenigstens zweilagig mit einer an die Isolierschicht anschließenden Kupfer- oder Aluminiumschicht sowie mit einer zumindest einlagigen, vorzugsweise dünnen Oberflächen- oder Abschlussschicht an der der Isolierschicht abgewandten Oberflächenseite der Kupfer- oder Aluminiumschicht ausgeführt ist,
und/oder
dass die Oberflächen- oder Abschlussschicht eine Nickelschicht ist, vorzugsweise mit einer Dicke im Bereich zwischen 0,002 mm und 0,015 mm,
und/oder
dass die Oberflächen- oder Abschlussschicht eine Schicht aus Silber ist, vorzugsweise mit einer Schichtdicke im Bereich zwischen 0,00015 mm und 0,05 mm,
und/oder
dass die Oberflächen- oder Abschlussschicht eine Schicht aus Gold ist, beispielsweise mit einer Schichtdicke im Bereich zwischen 0,0001 mm und 0,015 mm,
und/oder
dass die Oberflächen- oder Abschlussschicht eine Schicht aus Silber oder Gold ist mit einer Schichtdicke im Bereich zwischen 0,01 μm und 3 μm,
und/oder
dass die Oberflächen- oder Abschlussschicht mehrlagig ausgeführt ist und wenigstens aus der an die Kupfer- oder Aluminiumschicht anschließenden Nickelschicht und aus der Silber- und/oder Goldschicht besteht, die an die der Isolierschicht abgewandten Seite der Nickelschicht anschließt,
und/oder
dass die die Lötstoppstruktur bildende Oxidschicht im Wesentlichen aus Nickeloxid besteht,
und/oder
dass die die Lötstoppstruktur bildende Oxidschicht zumindest bis an das Niveau der Außenfläche der Metallisierung oder der Oberflächen- oder Abschlussschicht reicht, vorzugsweise über dieses Niveau vorsteht,
und/oder
dass die die Lötstoppstruktur bildende Oxidschicht eine Schichtdicke im Bereich zwischen 0,0001 mm und 0,015 mm aufweist,
und/oder
dass die Lötstoppstruktur den wenigstens einen Löt- oder Bondbereich umschließt,
und/oder
dass die Lötstoppstruktur eine Breite im Bereich zwischen 0,1 mm und 1,2 mm aufweist,
und/oder
dass die Isolierschicht aus Kunststoff, beispielsweise aus faserverstärktem Kunststoff besteht,
und/oder
dass die Isolierschicht aus Kunststoff, beispielsweise aus faserverstärktem Kunststoff besteht und eine Dicke im Bereich zwischen 0,015 mm und 3,0 mm aufweist,
und/oder
dass die Isolierschicht eine Keramikschicht, vorzugsweise aus Aluminiumoxid, Aluminiumnitrid, Siliziumnitrid oder Aluminiumoxid mit Zirkonoxid ist,
und/oder
dass die Isolierschicht eine Keramikschicht, vorzugsweise aus Aluminiumoxid, Aluminiumnitrid, Siliziumnitrid oder Mischkeramik aus Aluminiumoxid mit Zirkonoxid, beispielsweise aus Aluminiumoxid mit 1 Gew.-% bis 23 Gew.-% Zirkonoxid ist und eine Dicke im Bereich zwischen 0,15 mm und 1,5 mm aufweist,
und/oder
dass die wenigstens eine Metallisierung durch Kleben oder Aktivlöten oder DCB-Bonden mit der Isolierschicht verbunden ist,
und/oder
dass auf den wenigstens einen Bond- oder Lötbereich eine Lotschicht aufgebracht ist,
und/oder
dass auf den wenigstens einen Bond- oder Lötbereich eine Lotschicht aufgebracht ist und über die Lötschicht ein Bauteil (
wobei die vorgenannten Merkmale jeweils einzeln oder in beliebiger Kombination verwendet sein können.In a development of the invention, for example, the substrate is also designed
the at least one metallization is at least partially composed of a copper layer, preferably of a copper layer having a thickness in the range of 0.015 mm to 0.8 mm and the oxide layer of a copper oxide, preferably of a thickness in the range of 0.00015 mm to 0.1 mm are formed,
and or
the at least one metallization is formed at least partially by a layer of aluminum, preferably with a thickness in the range between 0.015 mm and 0.8 mm, and the oxide layer of aluminum oxide, preferably with a thickness in the range between 0.005 mm and 0.1 mm,
and or
that the at least one metallization is embodied in at least two layers with a copper or aluminum layer adjoining the insulating layer and with an at least single-layer, preferably thin surface or final layer on the surface side of the copper or aluminum layer facing away from the insulating layer,
and or
the surface or final layer is a nickel layer, preferably with a thickness in the range between 0.002 mm and 0.015 mm,
and or
that the surface or final layer is a layer of silver, preferably with a layer thickness in the range between 0.00015 mm and 0.05 mm,
and or
that the surface or final layer is a layer of gold, for example with a layer thickness in the range between 0.0001 mm and 0.015 mm,
and or
the surface or final layer is a layer of silver or gold with a layer thickness in the range between 0.01 μm and 3 μm,
and or
the surface or cover layer is multi-layered and consists at least of the nickel layer adjoining the copper or aluminum layer and of the silver and / or gold layer which adjoins the side of the nickel layer facing away from the insulating layer,
and or
that the oxide layer forming the solder stop structure consists essentially of nickel oxide,
and or
that the oxide layer forming the solder stop structure extends at least to the level of the outer surface of the metallization or of the surface or outer layer, preferably protruding above this level,
and or
the oxide layer forming the solder stop structure has a layer thickness in the range between 0.0001 mm and 0.015 mm,
and or
that the solder stop structure surrounds the at least one soldering or bonding region,
and or
that the solder stop structure has a width in the range between 0.1 mm and 1.2 mm,
and or
that the insulating layer is made of plastic, for example of fiber-reinforced plastic,
and or
that the insulating layer consists of plastic, for example of fiber-reinforced plastic and has a thickness in the range between 0.015 mm and 3.0 mm,
and or
in that the insulating layer is a ceramic layer, preferably of aluminum oxide, aluminum nitride, silicon nitride or aluminum oxide with zirconium oxide,
and or
in that the insulating layer is a ceramic layer, preferably of aluminum oxide, aluminum nitride, silicon nitride or mixed ceramic of aluminum oxide with zirconium oxide, for example of aluminum oxide with 1% by weight to 23% by weight zirconium oxide and a thickness in the range between 0.15 mm and 1, 5 mm,
and or
the at least one metallization is connected to the insulating layer by gluing or active soldering or DCB bonding,
and or
in that a solder layer is applied to the at least one bonding or soldering region,
and or
in that a solder layer is applied to the at least one bonding or soldering area and a component is applied via the soldering layer (
wherein the aforementioned features can be used individually or in any combination.
In Weiterbildung der Erfindung ist das Verfahren u. a. beispielsweise so ausgebildet,
dass die partielle Umwandlung des Metalls der wenigstens einen Metallisierung in das die Lötstoppstruktur bildende Oxid durch Wärmeeintrag und/oder durch chemische Oxidation erfolgt,
und/oder
dass die partielle Umwandlung des Metalls der wenigstens einen Metallisierung in das die Lötstoppstruktur (
und/oder
dass die partielle Umwandlung des Metalls der wenigstens einen Metallisierung in das die Lötstoppstruktur (
und/oder
dass die partielle Umwandlung des Metalls in das die Lötstoppstruktur bildende Oxid in einer sauerstoffhaltigen Atmosphäre mit einem Sauerstoffanteil von wenigstens 10%, beispielsweise in einer sauerstoffhaltigen Atmosphäre mit einem Sauerstoffanteil zwischen 21% und 99% erfolgt,
und/oder
dass die Laserbehandlung über eine Maske erfolgt,
und/oder
dass die Laserbehandlung durch Relativbewegung zwischen einem Laserstrahl und dem Substrat in Richtung des Verlaufs der Lötstoppstruktur sowie auch durch eine kreisende und/oder oszillierende Relativbewegung, insbesondere durch eine oszillierende Relativbewegung quer zum Verlauf der Lötstoppstruktur erfolgt,
und/oder
dass die partielle Umwandlung des Metalls in das die Lötstoppstruktur bildende Oxid derart erfolgt, dass die die Lötstoppstruktur bildende Oxidschicht zumindest bis an das Niveau der Außenfläche der Metallisierung oder der Oberflächen- oder Abschlussschicht reicht, vorzugsweise über dieses Niveau vorsteht,
und/oder
dass die partielle Umwandlung des Metalls der wenigstens einen Metallisierung in das die Lötstoppstruktur bildende Oxid nach dem Aufbringen einer wenigstens einlagigen metallischen Oberflächen- oder Abschlussschicht auf eine mit der Isolierschicht verbundene Metallschicht, beispielsweise aus Kupfer oder Aluminium erfolgt,
und/oder
dass die partielle Umwandlung des Metalls der wenigstens einen Metallisierung in das die Lötstoppstruktur bildende Oxid derart erfolgt, dass die die Lötstoppstruktur bildende Oxidschicht nur oder im Wesentlichen nur von wenigsten einem Metall der Oberflächen- oder Abschlussschicht gebildet ist,
und/oder
dass die Oberflächen- oder Abschlussschicht oder zumindest eine Teilschicht dieser Oberflächen- oder Abschlussschicht aus Nickel, Gold, Silber oder Nickel-, Gold-, Silber-Legierungen besteht,
und/oder
dass bei einer wenigstens zweilagigen Ausbildung der Oberflächen- oder Abschlussschicht (
und/oder
dass bei einer Isolierschicht aus Keramik, beispielsweise aus Aluminiumoxid, Aluminiumnitrid, Siliziumnitrid oder Aluminiumoxid mit Zirkonoxid, die wenigstens eine aus Kupfer oder Aluminium bestehende Metallisierung durch DCB-Bonden oder Aktivlöten oder durch Kleben, vorzugsweise durch Kleben mit einem Carbon-Fasern oder Carbon-Nanofasern enthaltenden Kleber mit der Isolierschicht verbunden wird,
und/oder
dass bei einer Isolierschicht aus einem polymeren Material die wenigstens eine Metallisierung mit der Isolierschicht durch Kleben, vorzugsweise mit einem polymeren Kleber, z. B. mit einem polymeren Carbon-Fasern- und/oder Carbon-Nofasern enthaltenden Kleber verbunden wird,
und/oder
dass die partielle Umwandlung des Metalls in das die Lötstoppstruktur bildende Metalloxid unter Verwendung einer Maske erfolgt,
und/oder
dass die partielle Umwandlung des Metalls in das die Lötstoppstruktur bildende Metalloxid unter Verwendung einer Maske durch chemische oder nasschemische Oxidation über die Maske erfolgt,
und/oder
dass auf den wenigstens einen Bond- oder Lötbereich nach dem Erzeugen der Lötstoppstruktur eine Lötschicht aufgebracht wird,
und/oder
dass wenigstens ein elektrisches Bauelement (
und/oder
dass bei einer Herstellung der Substrate in einem Mehrfachnutzen oder in einem Mehrfachsubstrat und beim Trennen des Mehrfachsubstrates in die Substrate oder beim Einbringen von Trenn- oder Sollbruchlinien in der Isolierschicht zwischen den Substraten durch Laserbehandlung in diesem Verfahrensschritt oder zumindest mit demselben Laser auch die Lötstoppstrukturen oder Lötstoppmuster erzeugt werden,
wobei die vorgenannten Merkmale jeweils einzeln oder in beliebiger Kombination verwendet sein können.In a development of the invention, the method is, for example, designed in such a way, for example.
the partial transformation of the metal of the at least one metallization into the oxide forming the solder stop structure takes place by heat input and / or by chemical oxidation,
and or
in that the partial conversion of the metal of the at least one metallization into the solder stop structure (
and or
in that the partial conversion of the metal of the at least one metallization into the solder stop structure (
and or
in that the partial conversion of the metal into the oxide forming the solder stop structure takes place in an oxygen-containing atmosphere having an oxygen content of at least 10%, for example in an oxygen-containing atmosphere having an oxygen content between 21% and 99%,
and or
that the laser treatment takes place via a mask,
and or
the laser treatment takes place by relative movement between a laser beam and the substrate in the direction of the course of the solder stop structure as well as by a circular and / or oscillating relative movement, in particular by an oscillating relative movement transverse to the course of the solder stop structure,
and or
in that the partial conversion of the metal into the oxide forming the solder stop structure takes place in such a way that the oxide layer forming the solder stop structure extends at least as far as the level of the outer surface of the metallization or the surface or outer layer, preferably above this level,
and or
in that the partial conversion of the metal of the at least one metallization into the oxide forming the solder stop structure takes place after the application of an at least single-layer metallic surface or final layer to a metal layer, for example made of copper or aluminum, connected to the insulating layer,
and or
in that the partial transformation of the metal of the at least one metallization into the oxide forming the solder stop structure takes place in such a way that the oxide layer forming the solder stop structure is formed only or substantially only by at least one metal of the surface or final layer,
and or
that the surface or finishing layer or at least a sub-layer of this surface or Final layer consists of nickel, gold, silver or nickel, gold, silver alloys,
and or
in the case of at least two-ply formation of the surface or outer layer (
and or
in the case of an insulating layer of ceramic, for example of aluminum oxide, aluminum nitride, silicon nitride or aluminum oxide with zirconium oxide, the at least one copper or aluminum metallization by DCB bonding or active soldering or by gluing, preferably by gluing with a carbon fiber or carbon nanofibers containing adhesive is connected to the insulating layer,
and or
that in an insulating layer of a polymeric material, the at least one metallization with the insulating layer by gluing, preferably with a polymeric adhesive, for. B. is bonded to a polymeric carbon fiber and / or carbon nofasern containing adhesive,
and or
the partial conversion of the metal into the metal oxide forming the solder stop structure takes place using a mask,
and or
in that the partial conversion of the metal into the metal oxide forming the solder stop structure takes place by means of a mask by chemical or wet chemical oxidation over the mask,
and or
in that a soldering layer is applied to the at least one bonding or soldering area after the soldering-stop structure has been produced,
and or
that at least one electrical component (
and or
that in a production of the substrates in a multiple use or in a multi-substrate and in separating the multi-substrate into the substrates or when introducing separation or predetermined breaking lines in the insulating layer between the substrates by laser treatment in this process step or at least with the same laser and the Lötstoppstrukturen or Lötstoppmuster be generated,
wherein the aforementioned features can be used individually or in any combination.
Der Ausdruck „ohne Materialabtrag” bedeutet im Sinne der Erfindung, dass bei Erzeugen des die Lötstoppstruktur bildenden Metall-Oxids kein Material oder im Wesentlichen kein Material beispielsweise durch Verdampfen entfernt wird.The term "without material removal" in the sense of the invention means that no material or substantially no material is removed, for example by evaporation, when the metal oxide forming the solder stop structure is produced.
Der Ausdruck „im Wesentlichen” bzw. „etwa” bedeutet im Sinne der Erfindung Abweichungen vom jeweils exakten Wert um +/–10%, bevorzugt um +/–5% und/oder Abweichungen in Form von für die Funktion unbedeutenden Änderungen.The expression "essentially" or "approximately" in the sense of the invention means deviations from the exact value by +/- 10%, preferably by +/- 5% and / or deviations in the form of changes that are insignificant for the function.
Weiterbildungen, Vorteile und Anwendungsmöglichkeiten der Erfindung ergeben sich auch aus der nachfolgenden Beschreibung von Ausführungsbeispielen und aus den Figuren. Dabei sind alle beschriebenen und/oder bildlich dargestellten Merkmale für sich oder in beliebiger Kombination grundsätzlich Gegenstand der Erfindung, unabhängig von ihrer Zusammenfassung in den Ansprüchen oder deren Rückbeziehung. Auch wird der Inhalt der Ansprüche zu einem Bestandteil der Beschreibung gemacht.Further developments, advantages and applications of the invention will become apparent from the following description of exemplary embodiments and from the figures. In this case, all described and / or illustrated features alone or in any combination are fundamentally the subject of the invention, regardless of their summary in the claims or their dependency. Also, the content of the claims is made an integral part of the description.
Die Erfindung wird im Folgenden anhand der Figuren an Ausführungsbeispielen näher erläutert. Es zeigen:The invention will be explained in more detail below with reference to the figures of exemplary embodiments. Show it:
Das in den
Entsprechend den
Wird der Hitzeeintrag zur Bildung des Lötstoppmusters
Für das Aufbringen des Lötstoppmusters eignet sich insbesondere eine Laserbehandlung mit einem YAG-Laser oder CO2-Laser oder Eximer-Laser, beispielsweise mit einem YAG-Laser mit einer Leistung zwischen 30 W und 100 W, mit einem CO2-Laser mit einer Leistung zwischen 50 W und 300 W oder mit einem Eximer-Laser mit einer Leistung zwischen 30 W und 150 W. Die Laserbehandlung erfolgt durch direkte Bestrahlung des Metallbereichs
Die Metallisierungen
Die Isolierschicht
Für die Isolierschicht
U. a. unter Berücksichtigung der für die Isolierschicht
Besteht die Isolierschicht
Zur Fertigstellung des Substrates
Für die Oberflächen- oder Abschlussschicht
Durch die Oberflächenbeschichtung
Die
Das Verbinden und dabei insbesondere das elektrische Verbinden der wiederum als Leiterplatten verwendeten Substrat
Ist die Oberflächenbeschichtung
Wie vorstehend erwähnt, erfolgt die Erzeugung des Lötstoppmusters
Die Erfindung wurde voranstehend an Ausführungsbeispielen beschrieben. Es versteht sich, dass zahlreiche Änderungen sowie Abwandlungen möglich sind, ohne dass dadurch der der Erfindung zugrunde liegend Erfindungsgedanke verlassen wird.The invention has been described above by means of exemplary embodiments. It is understood that numerous changes and modifications are possible, without thereby departing from the invention underlying the idea of the invention.
So wurde vorstehend davon ausgegangen, dass die Lötstoppmuster
Vorstehend wurde davon ausgegangen, dass die Metallisierungen
Durch ein mehrmaliges, beispielsweise zweimaliges Abfahren des Lötstoppmusters
Wird das Substrat
BezugszeichenlisteLIST OF REFERENCE NUMBERS
- 1, 1a–1c1, 1a-1c
- Substratsubstratum
- 22
- Isolierschichtinsulating
- 3, 43, 4
- Metallisierungmetallization
- 3.1, 3.23.1, 3.2
- Metallbereichmetal sector
- 55
- Lötstoppmuster oder -strukturSolder stop pattern or structure
- 66
- BondbereichBond area
- 77
- Lotsolder
- 88th
- elektrisches Bauelementelectrical component
- 99
- Oberflächen- oder AbschlussschichtSurface or finishing layer
- 9.1, 9.29.1, 9.2
- Teilschichtsublayer
- 1111
- Maskemask
- AA
- Wärme- oder Hitzeeintrag bzw. LaserstrahlungHeat or heat input or laser radiation
ZITATE ENTHALTEN IN DER BESCHREIBUNG QUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- DE 102008042777 A1 [0003] DE 102008042777 A1 [0003]
- US 3744120 [0004] US 3744120 [0004]
- DE 2319854 [0004] DE 2319854 [0004]
- DE 2213115 [0006] DE 2213115 [0006]
- EP 153618 A [0006] EP 153618 A [0006]
- DE 4319944 A1 [0010] DE 4319944 A1 [0010]
Claims (19)
Priority Applications (1)
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DE102012110382.8A DE102012110382B4 (en) | 2011-12-21 | 2012-10-30 | Substrate and method for manufacturing a substrate |
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DE102011056768.2 | 2011-12-21 | ||
DE102011056768 | 2011-12-21 | ||
DE102012110382.8A DE102012110382B4 (en) | 2011-12-21 | 2012-10-30 | Substrate and method for manufacturing a substrate |
Publications (2)
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DE102012110382A1 true DE102012110382A1 (en) | 2013-06-27 |
DE102012110382B4 DE102012110382B4 (en) | 2021-02-18 |
Family
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DE102012110382.8A Active DE102012110382B4 (en) | 2011-12-21 | 2012-10-30 | Substrate and method for manufacturing a substrate |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2966677A1 (en) * | 2014-07-07 | 2016-01-13 | Nxp B.V. | Method of attaching electronic components by soldering with removal of substrate oxide coating using a flux, corresponding substrate and corresponding flip-chip component |
CN108374170A (en) * | 2016-12-20 | 2018-08-07 | 中国航空制造技术研究院 | A kind of painting method of only solder flux |
EP4053886A1 (en) * | 2021-03-01 | 2022-09-07 | Infineon Technologies AG | Method for fabricating a substrate with a solder stop structure, substrate with a solder stop structure and electronic device |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3744120A (en) | 1972-04-20 | 1973-07-10 | Gen Electric | Direct bonding of metals with a metal-gas eutectic |
DE2213115A1 (en) | 1972-03-17 | 1973-09-27 | Siemens Ag | PROCESS FOR HIGH STRENGTH JOINING CARBIDES, INCLUDING DIAMONDS, BORIDES, NITRIDES, SILICIDES, TO METAL BY THE DRY SOLDERING PROCESS |
DE2319854A1 (en) | 1972-04-20 | 1973-10-25 | Gen Electric | PROCESS FOR DIRECTLY JOINING METALS WITH NON-METALLIC SUBSTRATES |
EP0153618A2 (en) | 1984-02-24 | 1985-09-04 | Kabushiki Kaisha Toshiba | Method for preparing highly heat-conductive substrate and copper wiring sheet usable in the same |
DE4319944A1 (en) | 1993-06-03 | 1994-12-08 | Schulz Harder Juergen | Multiple substrate and process for its manufacture |
DE102008042777A1 (en) | 2008-10-13 | 2010-04-15 | Robert Bosch Gmbh | Selective solder stop |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10027732A1 (en) * | 2000-06-03 | 2001-12-06 | Kem Tec Service Gmbh | Multiple use circuit board provided on both sides with rupture lines using displacement of circuit board relative to opposing laser beam elements |
JP4065215B2 (en) * | 2003-05-13 | 2008-03-19 | 福田金属箔粉工業株式会社 | Copper foil for printed wiring boards |
DE10351120A1 (en) * | 2003-11-03 | 2005-06-09 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Lötstopbarriere |
DE102005042554B4 (en) * | 2005-08-10 | 2008-04-30 | Curamik Electronics Gmbh | Metal-ceramic substrate and method for producing a metal-ceramic substrate |
-
2012
- 2012-10-30 DE DE102012110382.8A patent/DE102012110382B4/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2213115A1 (en) | 1972-03-17 | 1973-09-27 | Siemens Ag | PROCESS FOR HIGH STRENGTH JOINING CARBIDES, INCLUDING DIAMONDS, BORIDES, NITRIDES, SILICIDES, TO METAL BY THE DRY SOLDERING PROCESS |
US3744120A (en) | 1972-04-20 | 1973-07-10 | Gen Electric | Direct bonding of metals with a metal-gas eutectic |
DE2319854A1 (en) | 1972-04-20 | 1973-10-25 | Gen Electric | PROCESS FOR DIRECTLY JOINING METALS WITH NON-METALLIC SUBSTRATES |
EP0153618A2 (en) | 1984-02-24 | 1985-09-04 | Kabushiki Kaisha Toshiba | Method for preparing highly heat-conductive substrate and copper wiring sheet usable in the same |
DE4319944A1 (en) | 1993-06-03 | 1994-12-08 | Schulz Harder Juergen | Multiple substrate and process for its manufacture |
DE102008042777A1 (en) | 2008-10-13 | 2010-04-15 | Robert Bosch Gmbh | Selective solder stop |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2966677A1 (en) * | 2014-07-07 | 2016-01-13 | Nxp B.V. | Method of attaching electronic components by soldering with removal of substrate oxide coating using a flux, corresponding substrate and corresponding flip-chip component |
CN105244295A (en) * | 2014-07-07 | 2016-01-13 | 恩智浦有限公司 | Methods of attaching electronic components |
CN108374170A (en) * | 2016-12-20 | 2018-08-07 | 中国航空制造技术研究院 | A kind of painting method of only solder flux |
EP4053886A1 (en) * | 2021-03-01 | 2022-09-07 | Infineon Technologies AG | Method for fabricating a substrate with a solder stop structure, substrate with a solder stop structure and electronic device |
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