CN213878074U - Substrate for lead bonding process - Google Patents
Substrate for lead bonding process Download PDFInfo
- Publication number
- CN213878074U CN213878074U CN202022480537.6U CN202022480537U CN213878074U CN 213878074 U CN213878074 U CN 213878074U CN 202022480537 U CN202022480537 U CN 202022480537U CN 213878074 U CN213878074 U CN 213878074U
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- bonding
- bonding pad
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Abstract
The utility model aims at providing a substrate for a lead bonding process, which is used for the lead bonding of a substrate and a chip; a substrate for a lead bonding process comprises a substrate 1, a substrate bonding pad 2, a chip 3, a chip bonding pad 4 and a bonding wire 5; the substrate 1 is also provided with an upper substrate 11 and a lower substrate 12; the upper layer substrate 11 and the lower layer substrate 12 are arranged in a step shape from top to bottom; the substrate pad 2 is arranged inside the substrate 1; the chip 3 is arranged at the lower part of the substrate 1; the chip bonding pad 4 is embedded in the upper surface of the chip 3; the bonding wire 5 is connected with the chip bonding pad 4 and the substrate bonding pad; the utility model has the advantages that: by changing the design of the substrate, the arc length of the gold wire is shortened, and the use cost of the gold wire is reduced; and the line arc impact resistance is improved.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a base plate for lead bonding technology.
Background
At present, the traditional packaging form of the DRAM memory realizes circuit conduction between a chip and a substrate in the forms of chip pasting and wire bonding. The substrate consists of two circuit layers, and the current product design arranges the substrate pads at the layer far from the chip (as shown in fig. 2). In the lead bonding engineering, pure gold wires are welded on the substrate bonding pad and the chip bonding pad to realize circuit conduction of the substrate bonding pad and the chip bonding pad.
Because the performance and reliability requirements of DRAM products are high, the bonding operation is still carried out by gold wires with the purity of 99.99 percent in the industry at present. The price trend of the gold price market is continuously rising up to date in 2018, the manufacturing cost is continuously rising, the length of a bonding wire arc in product design is long, and the impact resistance of the wire arc is poor.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a base plate for wire bonding technology for the wire bonding of base plate and chip.
The utility model provides a substrate for a lead bonding process, which comprises a substrate 1, a substrate bonding pad 2, a chip 3, a chip bonding pad 4 and a bonding wire 5;
the substrate 1 is also provided with an upper substrate 11 and a lower substrate 12; the upper layer substrate 11 and the lower layer substrate 12 are arranged in a step shape from top to bottom;
the substrate pad 2 is arranged inside the substrate 1;
the chip 3 is arranged at the lower part of the substrate 1;
the chip bonding pad 4 is embedded in the upper surface of the chip 3;
the bonding wire 5 connects the chip bonding pad 4 and the substrate bonding pad.
The utility model has the advantages that: by changing the design of the substrate, the arc length of the gold wire is shortened, and the use cost of the gold wire is reduced; and the line arc impact resistance is improved.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of a prior art structure;
in the figure, the position of the upper end of the main shaft,
1. a substrate 11, an upper substrate 12, a lower substrate; 2. a substrate pad; 3. a chip; 4. a chip bonding pad; 5. and (7) welding wires.
Detailed Description
The present invention will now be described in detail with reference to the drawings, which are provided for illustrative and explanatory purposes only and should not be construed as limiting the scope of the present invention in any way.
As shown in fig. 1, the utility model provides a substrate for wire bonding process, which comprises a substrate 1, a substrate bonding pad 2, a chip 3, a chip bonding pad 4 and a bonding wire 5;
the substrate 1 is also provided with an upper substrate 11 and a lower substrate 12; the upper layer substrate 11 and the lower layer substrate 12 are arranged in a step shape from top to bottom;
the substrate pad 2 is arranged inside the substrate 1;
the chip 3 is arranged at the lower part of the substrate 1;
the chip bonding pad 4 is embedded in the upper surface of the chip 3;
the bonding wire 5 connects the chip bonding pad 4 and the substrate bonding pad.
As shown in fig. 2, which is a schematic diagram of a prior art structure, a bonding wire needs to be long because the bonding wire is connected from a chip bonding pad to a substrate bonding pad on the upper surface of a substrate. As shown in fig. 1, in the bonding wire connection method of the present embodiment, the bonding wire 5 is connected from the die pad 4 to the substrate pad 2 on the lower substrate 12, which reduces the required length of the bonding wire compared to the prior art. Meanwhile, the height difference from the chip bonding pad 4 to the substrate bonding pad 2 on the lower substrate 12 is small, so that the radian of the bonding wire 5 is large, and the line arc impact resistance is strong.
It should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The above-mentioned embodiments of the present invention do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (1)
1. A substrate for a lead bonding process comprises a substrate (1), a substrate bonding pad (2), a chip (3), a chip bonding pad (4) and a bonding wire (5);
it is characterized in that the preparation method is characterized in that,
the substrate (1) is also provided with an upper substrate (11) and a lower substrate (12); the upper layer substrate (11) and the lower layer substrate (12) are arranged in a step shape from top to bottom;
the substrate pad (2) is arranged inside the substrate (1);
the chip (3) is arranged at the lower part of the substrate (1);
the chip bonding pad (4) is embedded in the upper surface of the chip (3);
the bonding wire (5) is connected with the chip bonding pad (4) and the substrate bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022480537.6U CN213878074U (en) | 2020-10-30 | 2020-10-30 | Substrate for lead bonding process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022480537.6U CN213878074U (en) | 2020-10-30 | 2020-10-30 | Substrate for lead bonding process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213878074U true CN213878074U (en) | 2021-08-03 |
Family
ID=77051536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022480537.6U Active CN213878074U (en) | 2020-10-30 | 2020-10-30 | Substrate for lead bonding process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN213878074U (en) |
-
2020
- 2020-10-30 CN CN202022480537.6U patent/CN213878074U/en active Active
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