CN216056325U

CN216056325U - DALI & PUSH control circuit for inhibiting surge voltage

Info

Publication number: CN216056325U
Application number: CN202122313070.0U
Authority: CN
Inventors: 郑德华; 陈耿圳
Original assignee: Zhuhai Shengchang Electronics Co ltd
Current assignee: Zhuhai Shengchang Electronics Co ltd
Priority date: 2021-09-24
Filing date: 2021-09-24
Publication date: 2022-03-15
Anticipated expiration: 2031-09-24

Abstract

The utility model discloses and provides a DALI & PUSH control circuit for inhibiting surge voltage. The utility model comprises a signal terminal, a protective tube, a bidirectional transient voltage stabilizing diode, a rectifier bridge, a first resistor, a second resistor, a third resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a first PNP triode, a second PNP triode, an NMOS tube, an NPN triode, a first optocoupler, a second optocoupler, a voltage stabilizing tube, a singlechip, a second capacitor and a third capacitor. The utility model is applied to the technical field of power supply circuits and controller circuits.

Description

DALI & PUSH control circuit for inhibiting surge voltage

Technical Field

The present invention relates to a power circuit and a controller circuit, and more particularly, to a DALI & PUSH control circuit for suppressing surge voltage.

Background

With the rapid development of the LED lighting industry, LEDs are installed in all households and outdoor lighting at present, so that the LED power supply market is developed vigorously, and the requirements on the LED power supply are higher and higher. At present, DALI power supplies are also widely applied in the market. The DALI power supply is controlled in two ways, one is controlled by a DALI dimmer, and the other is controlled by a PUSH switch. The same as the alternating current input of the DALI power supply, the PUSH switch dimming is connected with the high-voltage alternating current voltage, so that very high surge voltage can be generated at the moment of pressing down the PUSH switch during dimming, and even the phenomenon of sparking can occur due to overhigh surge voltage. Because DALI dimming and PUSH switch dimming share the same DALI control circuit, surge voltage generated by the PUSH switch easily breaks down components of the DALI control circuit, so that the DALI control circuit is invalid. Therefore, it is necessary to develop a DALI & PUSH control circuit for suppressing the surge voltage.

SUMMERY OF THE UTILITY MODEL

The utility model aims to overcome the defects of the prior art and provides a DALI & PUSH control circuit for inhibiting surge voltage.

The technical scheme adopted by the utility model is as follows: the bidirectional transient voltage regulator comprises a signal terminal P1, a fuse tube FU1, a bidirectional transient voltage regulator diode TV1, a rectifier bridge DB1, a first resistor R1, a second resistor R2, a third resistor R3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first PNP triode Q1, a second PNP triode Q2, an NMOS tube Q3, an NPN triode Q4, a first optical coupler U1, a second optical coupler U2, a voltage regulator tube Z1, a single chip microcomputer U3, a second capacitor C2 and a third capacitor C3; two input ends of the signal terminal P1 are connected to a DALI bus signal of a DALI controller, one output end of the signal terminal P1 is connected to one end of the fuse FU1, the other end of the fuse FU1 and one end of the bidirectional transient zener diode TV1 are both connected to one input end of the AC of the rectifier bridge DB1, the other end of the bidirectional transient zener diode TV1 and the other input end of the AC of the rectifier bridge DB1 are both connected to the other output end of the signal terminal P1, and the DALI bus signal is connected to two input ends of the AC of the rectifier bridge DB1 through the fuse FU1 and the bidirectional transient zener diode TV 1; the DALI bus signal rectified by the rectifier bridge DB1 is connected to the emitter of the second PNP triode Q2 through the first resistor R1, the base of the second PNP triode Q2 is connected to the GND terminal through the seventh resistor R7, the collector of the second PNP triode Q2 outputs a DALI bus signal, and the DALI bus signal is connected to pin 1 of the second optocoupler U2, and the DALI bus signal is output to the cathode of the regulator tube Z1 and one end of the third capacitor C3 through pin 2 of the second optocoupler U2, the anode of the regulator tube Z1 and the other end of the third capacitor C3 are connected to the GND terminal, the regulator tube Z1 is regulated to a certain value, the third capacitor C3 filters and stores voltage, and the second optocoupler U2 is turned on; an emitter of the first PNP triode Q1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to an emitter of the second PNP triode Q2 and a base of the first PNP triode Q1, and a collector of the first PNP triode Q1 is connected to a base of the second PNP triode Q2; when the current flowing through the first resistor R1 is too large, the voltage drop across the first resistor R1 reaches the conduction threshold of the first PNP transistor Q1, the first PNP transistor Q1 is turned on, and at this time, the second PNP transistor Q2 is turned off, so as to protect the second optocoupler U2 from being damaged by the large current; the voltage pulled up to a power supply VDD by the pin 4 of the second optical coupler U2 through the fifth resistor R5 is pulled low, and the pin 2 of the singlechip U3 detects the voltage pulled low by the pin 4 of the second optical coupler U2; because the DALI signal is a pulse square wave signal, the 2-pin of the single chip microcomputer U3 continuously detects the pulse square wave signal transmitted by the DALI bus signal; a pin 2 of the first optocoupler U1, a pin 3 of the second optocoupler U2 and a pin 4 of the singlechip U3 are all connected to a GNS terminal, after a pin 2 of the singlechip U3 detects a DALI bus signal, a pin 1 of the singlechip U3 outputs a corresponding pulse square wave DALI signal, and the pulse square wave DALI signal is connected to a pin 1 of the first optocoupler U1 through the second resistor R2 and then turns on the first optocoupler U1; a pin 4 of the first optocoupler U1 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to a GND terminal, after the first optocoupler U1 is turned on, the voltage stored in the pin 4 of the first optocoupler U1 by the third capacitor C3 is output through a pin 3 of the first optocoupler U1, the voltage output by the pin 3 of the first optocoupler U1 is connected to the gate of the NMOS transistor Q1 through the third resistor R3, so that the NMOS transistor Q1 is turned on, one end of the sixth resistor R6, one end of the second capacitor C2, and the collector of the NPN transistor Q4 are all connected to the gate of the NMOS transistor Q1, the other end of the sixth resistor R6, the other end of the second capacitor C2, and the emitter of the NPN transistor Q4 are all connected to the GND terminal, the base of the NPN transistor Q4 and one end of the eighth resistor R8 are connected to the source of the NMOS transistor Q1, the other end of the eighth resistor R8 is connected to a GND terminal, the drain of the NMOS transistor Q1 is connected to one end of the emitter of the first PNP triode Q1, and the NMOS transistor Q1 transmits a DALI signal output from pin 1 of the single chip microcomputer U3 to a DALI controller by pulling down a DALI bus signal on the rectifier bridge DB1, so that communication between the DALI controller and the single chip microcomputer U3 is completed; when the current flowing through the MOS transistor Q1 is too large, the voltage drop across the eighth resistor R8 reaches the turn-on threshold of the NPN transistor Q4, the NPN transistor Q4 is turned on, and the driving voltage of the gate of the MOS transistor Q1 is pulled down, so as to protect the MOS transistor Q1.

Further, 8 pins of the single chip microcomputer U3 are pulled up to a power supply VDD.

Further, the DALI & PUSH control circuit for suppressing surge voltage further comprises a first capacitor C1, one end of the first capacitor C1 is connected with the pin 8 of the single chip microcomputer U3, and the other end of the first capacitor C1 is connected to a GNS terminal.

The utility model has the beneficial effects that: when the PUSH switch is used for PUSH control, because the PUSH switch is connected with high-voltage alternating-current voltage, very high surge voltage can be generated at the moment of pressing the PUSH switch, the bidirectional transient voltage stabilizing diode TV1 can quickly absorb the surge voltage, the voltage is clamped in a safe voltage range, and components of a control circuit at the back are protected.

Drawings

Fig. 1 is a circuit diagram of the present invention.

Detailed Description

As shown in fig. 1, in this embodiment, the present invention includes a signal terminal P1, a fuse FU1, a bidirectional transient zener diode TV1, a rectifier bridge DB1, a first resistor R1, a second resistor R2, a third resistor R3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a first PNP triode Q1, a second PNP triode Q2, an NMOS tube Q3, an NPN Q4, a first optocoupler U1, a second optocoupler U2, a stabilivolt Z1, a singlechip U3, a second capacitor C2, and a third capacitor C3; two input ends of the signal terminal P1 are connected to a DALI bus signal of a DALI controller, one output end of the signal terminal P1 is connected to one end of the fuse FU1, the other end of the fuse FU1 and one end of the bidirectional transient zener diode TV1 are both connected to one input end of the AC of the rectifier bridge DB1, the other end of the bidirectional transient zener diode TV1 and the other input end of the AC of the rectifier bridge DB1 are both connected to the other output end of the signal terminal P1, and the DALI bus signal is connected to two input ends of the AC of the rectifier bridge DB1 through the fuse FU1 and the bidirectional transient zener diode TV 1; the DALI bus signal rectified by the rectifier bridge DB1 is connected to the emitter of the second PNP triode Q2 through the first resistor R1, the base of the second PNP triode Q2 is connected to the GND terminal through the seventh resistor R7, the collector of the second PNP triode Q2 outputs a DALI bus signal, and the DALI bus signal is connected to pin 1 of the second optocoupler U2, and the DALI bus signal is output to the cathode of the regulator tube Z1 and one end of the third capacitor C3 through pin 2 of the second optocoupler U2, the anode of the regulator tube Z1 and the other end of the third capacitor C3 are connected to the GND terminal, the regulator tube Z1 is regulated to a certain value, the third capacitor C3 filters and stores voltage, and the second optocoupler U2 is turned on; an emitter of the first PNP triode Q1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to an emitter of the second PNP triode Q2 and a base of the first PNP triode Q1, and a collector of the first PNP triode Q1 is connected to a base of the second PNP triode Q2; when the current flowing through the first resistor R1 is too large, the voltage drop across the first resistor R1 reaches the conduction threshold of the first PNP transistor Q1, the first PNP transistor Q1 is turned on, and at this time, the second PNP transistor Q2 is turned off, so as to protect the second optocoupler U2 from being damaged by the large current; the voltage pulled up to a power supply VDD by the pin 4 of the second optical coupler U2 through the fifth resistor R5 is pulled low, and the pin 2 of the singlechip U3 detects the voltage pulled low by the pin 4 of the second optical coupler U2; because the DALI signal is a pulse square wave signal, the 2-pin of the single chip microcomputer U3 continuously detects the pulse square wave signal transmitted by the DALI bus signal; a pin 2 of the first optocoupler U1, a pin 3 of the second optocoupler U2 and a pin 4 of the singlechip U3 are all connected to a GNS terminal, after a pin 2 of the singlechip U3 detects a DALI bus signal, a pin 1 of the singlechip U3 outputs a corresponding pulse square wave DALI signal, and the pulse square wave DALI signal is connected to a pin 1 of the first optocoupler U1 through the second resistor R2 and then turns on the first optocoupler U1; a pin 4 of the first optocoupler U1 is connected to one end of the third capacitor C3, the other end of the third capacitor C3 is connected to a GND terminal, after the first optocoupler U1 is turned on, the voltage stored in the pin 4 of the first optocoupler U1 by the third capacitor C3 is output through a pin 3 of the first optocoupler U1, the voltage output by the pin 3 of the first optocoupler U1 is connected to the gate of the NMOS transistor Q1 through the third resistor R3, so that the NMOS transistor Q1 is turned on, one end of the sixth resistor R6, one end of the second capacitor C2, and the collector of the NPN transistor Q4 are all connected to the gate of the NMOS transistor Q1, the other end of the sixth resistor R6, the other end of the second capacitor C2, and the emitter of the NPN transistor Q4 are all connected to the GND terminal, the base of the NPN transistor Q4 and one end of the eighth resistor R8 are connected to the source of the NMOS transistor Q1, the other end of the eighth resistor R8 is connected to a GND terminal, the drain of the NMOS transistor Q1 is connected to one end of the emitter of the first PNP triode Q1, and the NMOS transistor Q1 transmits a DALI signal output from pin 1 of the single chip microcomputer U3 to a DALI controller by pulling down a DALI bus signal on the rectifier bridge DB1, so that communication between the DALI controller and the single chip microcomputer U3 is completed; when the current flowing through the MOS transistor Q1 is too large, the voltage drop across the eighth resistor R8 reaches the turn-on threshold of the NPN transistor Q4, the NPN transistor Q4 is turned on, and the driving voltage of the gate of the MOS transistor Q1 is pulled down, so as to protect the MOS transistor Q1.

In this embodiment, the pin 8 of the single chip microcomputer U3 is pulled up to the power supply VDD.

In this embodiment, the DALI & PUSH control circuit for suppressing a surge voltage further includes a first capacitor C1, one end of the first capacitor C1 is connected to the pin 8 of the single chip U3, and the other end of the first capacitor C1 is connected to a GNS terminal.

In the present embodiment, the GND terminal and the GNS terminal are two ground terminals with reference to ground.

In this embodiment, the model of the single chip microcomputer U3 is STM32G030K8T6 or STM32G030F6P 6.

When the PUSH signal is applied to both ends of the signal terminal P1, a high surge voltage is generated at a moment when the PUSH switch is pressed because the PUSH switch is applied with a high ac voltage. The surge voltage is absorbed by the bidirectional transient voltage stabilizing diode TV1 through the protective tube FU1, the voltage is clamped in a safe voltage range, and components of a rear control circuit are protected. Without the bi-directional transient zener diode TV1 to absorb the surge voltage, the surge voltage can break down the components of the following control circuit.

While the embodiments of the present invention have been described in terms of practical embodiments, they are not to be construed as limiting the meaning of the present invention, and modifications of the embodiments and combinations with other embodiments will be apparent to those skilled in the art in light of the present description.

Claims

1. A DALI & PUSH control circuit for suppressing surge voltages, characterized by: the DALI & PUSH control circuit for suppressing surge voltage comprises a signal terminal (P1), a protective tube (FU 1), a bidirectional transient voltage stabilizing diode (TV 1), a rectifier bridge (DB 1), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fifth resistor (R5), a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), a first PNP triode (Q1), a second PNP triode (Q2), an NMOS tube (Q3), an NPN triode (Q4), a first optical coupler (U1), a second optical coupler (U2), a voltage stabilizing tube (Z1), a single chip microcomputer (U3), a second capacitor (C2) and a third capacitor (C3); two input ends of the signal terminal (P1) are connected with a DALI bus signal of a DALI controller, one output end of the signal terminal (P1) is connected with one end of the fuse (FU 1), the other end of the fuse (FU 1) and one end of the bidirectional transient zener diode (TV 1) are both connected with one input end of the AC of the rectifier bridge (DB 1), the other end of the bidirectional transient zener diode (TV 1) and the other input end of the AC of the rectifier bridge (DB 1) are both connected with the other output end of the signal terminal (P1), and the DALI bus signal is connected with two ends of the AC input of the rectifier bridge (DB 1) through the fuse (FU 1) and the bidirectional transient zener diode (TV 1); the DALI bus signal rectified by the rectifier bridge (DB 1) is connected to the emitter of the second PNP triode (Q2) through the first resistor (R1), the base of the second PNP triode (Q2) is connected to a GND terminal through the seventh resistor (R7), the collector of the second PNP triode (Q2) outputs a DALI bus signal which is connected to pin 1 of the second optocoupler (U2), the DALI bus signal is output to the cathode of the stabilivolt (Z1) and one end of the third capacitor (C3) through pin 2 of the second optocoupler (U2), the anode of the stabilivolt (Z1) and the other end of the third capacitor (C3) are connected to a GND terminal, the stabilivolt (Z1) is stabilized to a certain value, the third capacitor (C3) filters and stores voltage, and the second optocoupler (U2) is conducted; the emitter of the first PNP triode (Q1) is connected with one end of the first resistor (R1), the other end of the first resistor (R1) is connected with the emitter of the second PNP triode (Q2) and the base of the first PNP triode (Q1), and the collector of the first PNP triode (Q1) is connected with the base of the second PNP triode (Q2); when the current flowing through the first resistor (R1) is too large, the voltage drop across the first resistor (R1) reaches the conduction threshold of the first PNP transistor (Q1), the first PNP transistor (Q1) is turned on, and at this time, the second PNP transistor (Q2) is turned off, so as to protect the second optocoupler (U2) from being damaged by the large current; the voltage pulled up to a power supply (VDD) by the fifth resistor (R5) on the 4 pins of the second optical coupler (U2) is pulled down, and the 2 pins of the single chip microcomputer (U3) detect the voltage pulled down on the 4 pins of the second optical coupler (U2); because the DALI signal is a pulse square wave signal, the 2-pin of the single chip microcomputer (U3) continuously detects the pulse square wave signal transmitted by the DALI bus signal; a pin 2 of the first optical coupler (U1), a pin 3 of the second optical coupler (U2) and a pin 4 of the single chip microcomputer (U3) are all connected to a GNS terminal, after a DALI bus signal is detected by the pin 2 of the single chip microcomputer (U3), a pin 1 of the single chip microcomputer (U3) outputs a corresponding pulse square wave DALI signal, and the pulse square wave DALI signal is connected to a pin 1 of the first optical coupler (U1) through the second resistor (R2) and then turns on the first optical coupler (U1); a pin 4 of the first optical coupler (U1) is connected with one end of the third capacitor (C3), the other end of the third capacitor (C3) is connected to a GND terminal, after the first optical coupler (U1) is turned on, the voltage stored in the third capacitor (C3) on the pin 4 of the first optical coupler (U1) is output through a pin 3 of the first optical coupler (U1), the voltage output through the pin 3 of the first optical coupler (U1) is connected to a gate of the NMOS transistor (Q3) through the third resistor (R3), and further the NMOS transistor (Q3) is turned on, one end of the sixth resistor (R6), one end of the second capacitor (C2) and a collector of the NPN transistor (Q4) are all connected to the gate of the NMOS transistor (Q3), the other end of the sixth resistor (R6), the other end of the second capacitor (C2) and an emitter of the NPN transistor (Q4) are all connected to GND terminal of the NPN 3983), a base electrode of the NPN triode (Q4) and one end of the eighth resistor (R8) are connected with a source electrode of the NMOS transistor (Q3), the other end of the eighth resistor (R8) is connected with a GND terminal, a drain electrode of the NMOS transistor (Q3) is connected with one end of an emitter electrode of the first PNP triode (Q1), and the NMOS transistor (Q3) transmits a DALI signal output by a pin 1 of the singlechip (U3) to a DALI controller by pulling down a DALI bus signal on a rectifier bridge (DB 1), so that the communication between the DALI controller and the singlechip (U3) is completed; when the current flowing through the NMOS transistor (Q3) is too large, the voltage drop of the eighth resistor (R8) reaches the conduction threshold of the NPN transistor (Q4), the NPN transistor (Q4) is conducted, the driving voltage of the grid electrode of the NMOS transistor (Q3) is pulled down, and therefore the NMOS transistor (Q3) is protected.

2. The DALI & PUSH control circuit for suppressing a surge voltage according to claim 1, wherein: 8 pins of the single chip microcomputer (U3) are pulled up to a power supply (VDD).

3. The DALI & PUSH control circuit for suppressing a surge voltage according to claim 2, wherein: the DALI & PUSH control circuit for suppressing the surge voltage further comprises a first capacitor (C1), one end of the first capacitor (C1) is connected with the 8 pin of the single chip microcomputer (U3), and the other end of the first capacitor (C1) is connected to a GNS terminal.