CN215070001U

CN215070001U - Solar cell and back contact structure thereof, cell module and photovoltaic system

Info

Publication number: CN215070001U
Application number: CN202121675055.4U
Authority: CN
Inventors: 陈刚; 许文理; 邱开富; 王永谦; 杨新强
Original assignee: Zhejiang Aiko Solar Energy Technology Co Ltd; Guangdong Aiko Technology Co Ltd; Tianjin Aiko Solar Energy Technology Co Ltd; Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Current assignee: Zhejiang Aiko Solar Energy Technology Co Ltd; Guangdong Aiko Technology Co Ltd; Tianjin Aiko Solar Energy Technology Co Ltd; Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
Priority date: 2021-07-22
Filing date: 2021-07-22
Publication date: 2021-12-07
Anticipated expiration: 2031-07-22

Abstract

The utility model is suitable for a solar cell technical field provides a solar cell and back contact structure, battery pack and photovoltaic system thereof, and the back contact structure includes that the interval sets up the first doping area opposite with silicon substrate polarity at the back of silicon substrate and the second doping area the same with silicon substrate polarity, is equipped with the guard area on the first doping area; the first doping region and the second doping region respectively comprise a first doping layer, a passivation layer and a second doping layer; the protection region comprises an insulating layer and a third doping layer with the same polarity as the second doping region; an isolation region is arranged between the first doping region and the second doping region; the protection region is provided with an opening so as to connect the first conductive layer with the first doped region; the heights of the first doped region and the second doped region are higher than the height of the isolation region. The utility model discloses in the back contact structure that provides, there is the problem of the produced fish tail of belt transmission in having solved current battery preparation process.

Description

Solar cell and back contact structure thereof, cell module and photovoltaic system

Technical Field

The utility model belongs to the technical field of solar cell, especially, relate to a solar cell and back contact structure, battery pack and photovoltaic system thereof.

Background

Solar cell power generation is a sustainable clean energy source, which can convert sunlight into electric energy by using the photovoltaic effect of semiconductor p-n junction, and the conversion efficiency is an important index of solar cell performance. The positive electrode and the negative electrode of the IBC (interdigitated back contact) battery are both designed on the back surface of the battery, so that the front surface thoroughly avoids the shielding of metal grid lines, the optical loss caused by the shielding of the metal grid lines is avoided, meanwhile, the electrode width is wider than that of the existing battery, the series resistance loss is reduced, and the conversion efficiency is greatly improved. In addition, the product appearance is more beautiful under the front electrodeless design, and the product is suitable for various application scenes.

In the existing doped polysilicon passivated IBC cell, the doped polysilicon is isolated from the silicon substrate by the tunneling layer, so that a passivated contact structure of the doped polysilicon-tunneling layer (insulating layer) -silicon substrate laminated type is formed. The IBC battery manufacturing method comprises the steps of manufacturing an IBC battery, wherein in the existing IBC battery manufacturing process, various process flows such as polishing, doping, etching, film coating, screen printing and the like need to be performed, and meanwhile, in the process of circulating among the processes, the IBC battery needs to be transmitted through various transportation modes such as a belt, a graphite boat, a sucker and the like.

However, in the process of conveying the battery piece by using the belt, the battery piece is in complete contact with the belt, at the moment, the rough surface on the belt in the conveying process may have the risk of scratching the battery piece, the scratch layer can be removed through subsequent procedures of texturing, etching and the like in the early preparation procedure of the battery piece, but after the passivation contact structure is prepared, the scratch influence of the belt on doped polycrystalline silicon in the passivation contact structure is difficult to remove or the process flow needs to be added for removing, at the moment, if the scratch of the battery piece is not treated, the defect of the battery piece caused by the scratch still exists in the subsequent procedures of plating a back passivation film and screen printing an electrode, so that the conversion efficiency of the battery piece is influenced.

SUMMERY OF THE UTILITY MODEL

An object of the embodiment of the utility model is to provide a solar cell's back contact structure aims at solving the problem that has the produced fish tail of belt transmission in the current battery preparation process.

The embodiment of the utility model provides a realize like this, a solar cell's back contact structure, include:

the silicon substrate comprises a first doping region and a second doping region, wherein the first doping region is arranged on the back surface of the silicon substrate at intervals and has the opposite polarity to the silicon substrate, the second doping region has the same polarity as the silicon substrate, and a protection region is arranged on the first doping region;

the first doped region and the second doped region both comprise a first doped layer, a passivation layer and a second doped layer;

the protection region comprises an insulating layer and a third doping layer with the same polarity as the second doping region;

an isolation region is arranged between the first doping region and the second doping region;

the protection region is provided with an opening so as to connect the first conductive layer with the first doped region;

the heights of the first doped region and the second doped region are higher than the height of the isolation region.

Furthermore, the height of the first doped region is higher than that of the second doped region.

Furthermore, the passivation layer is a porous structure with the first doping layer and/or the second doping layer in the hole region.

Furthermore, one of the first doped region and the second doped region is a P-type doped region, the other is an N-type doped region, and the thickness of the passivation layer in the P-type doped region is greater than that in the N-type doped region.

Furthermore, one of the first doped region and the second doped region is a P-type doped region, the other is an N-type doped region, and the hole density of the passivation layer in the P-type doped region is greater than the hole density of the passivation layer in the N-type doped region.

Further, the doping polarity of the first doping layer and the second doping layer is the same.

Furthermore, the height difference between the first doping region and the second doping region is 1-8 um.

Furthermore, the height difference between the second doping region and the isolation region is 0.5-8 um.

Further, the pore size in the porous structure is less than 20 um.

Further, the ratio of the area of the pore region of the porous structure to the overall area of the porous structure is less than 20%.

Further, the thickness of the passivation layer is 0.5-10 nm.

Further, the passivation layer and/or the insulating layer is one or more of an oxide layer, a silicon carbide layer and an amorphous silicon layer.

Furthermore, the doping concentration of the first doping layer is between the doping concentration of the silicon substrate and the doping concentration of the second doping layer.

Further, the junction depth of the first doped layer is less than 1.5 um.

Further, the first doped layer is a doped monocrystalline silicon layer doped with a group iii or group v element.

Further, the second doped layer and/or the third doped layer comprise a doped polysilicon layer or a doped silicon carbide layer or a doped amorphous silicon layer.

Furthermore, the doped silicon carbide layers in the second doped layer and/or the third doped layer are composed of at least one doped silicon carbide film with different refractive indexes, and the refractive index of each doped silicon carbide film is sequentially reduced from the silicon substrate to the outside.

Still further, the doped silicon carbide layer in the second doped layer and/or the third doped layer comprises a doped hydrogenated silicon carbide layer having a conductivity greater than 0.01S-cm and a thickness greater than 10 nm.

Further, the thickness of the insulating layer is 5-150 nm.

Further, the thickness of the insulating layer is greater than the thickness of the passivation layer.

An object of another embodiment of the present invention is to provide a solar cell, including:

a silicon substrate;

the back contact structure is arranged on the back of the silicon substrate;

a first dielectric layer disposed on the front side of the silicon substrate;

a first conductive layer disposed on the first doped region in the back contact structure and a second conductive layer disposed on the second doped region in the back contact structure; and

a second dielectric layer disposed on the back contact structure and between the first conductive layer and the second conductive layer.

Furthermore, the first dielectric layer and the second dielectric layer are one or more of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer and a silicon oxide layer.

Furthermore, the first dielectric layer and/or the second dielectric layer are an aluminum oxide layer and a silicon carbide layer, or a silicon oxide layer and a silicon carbide layer;

the thickness of the first dielectric layer is larger than 50nm, and the thickness of the second dielectric layer is larger than 25 nm.

Furthermore, the thickness of the aluminum oxide layer or the silicon oxide layer in the first dielectric layer is less than 40nm, the thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer is less than 25nm, and the thickness of the silicon carbide layer in the first dielectric layer and/or the second dielectric layer is greater than 10 nm.

Furthermore, the silicon carbide layer in the first dielectric layer and/or the second dielectric layer is composed of at least one silicon carbide film with different refractive indexes, and the refractive index of each silicon carbide film is reduced from the silicon substrate to the outside in sequence.

Furthermore, the outer layer of the first dielectric layer and/or the second dielectric layer is also provided with a magnesium fluoride layer.

Furthermore, the first conductive layer and the second conductive layer are TCO transparent conductive films and/or metal electrodes.

Further, the metal electrode includes a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode, or a silver-clad copper electrode.

Furthermore, an electric field layer or a floating junction is arranged between the front surface of the silicon substrate and the first dielectric layer.

Another embodiment of the present invention is directed to a battery module including the solar cell as described above.

It is still another object of an embodiment of the present invention to provide a photovoltaic system, which includes the battery module as described above.

The embodiment of the utility model provides a solar cell's back contact structure, through set up the protection zone on first doping district, and do not do any processing on the second doping district, thereby make the setting of the third doping layer in the protection zone outmost play anti fish tail effect, avoid leading to the fact the fish tail to its first doping district inboard in protection zone, simultaneously because the height that highly is less than the protection zone in second doping district, make only the protection zone laminate with the belt in transmission process, and there is certain clearance and realize unsettledly between second doping district and the belt, consequently, avoid leading to the fact the fish tail to the second doping district in the belt transmission process, make it avoid leading to the fact the problem of fish tail to first doping district and second doping district in the belt transmission process, the problem of having the fish tail that the belt transmits produced in the current battery preparation process has been solved.

Meanwhile, the passivation layer and the second doping layer in the second doping region are similar to the insulation layer and the third doping layer in the protection region in structure and can be made of the same materials, and the second doping layer in the second doping region is the same as the third doping layer in the protection region in doping polarity, so that the second doping region and the protection region can be synchronously manufactured by the same process, the protection region can be used as an intermediate produced in the process production process of the second doping region and is obtained by local reservation through a graphical design, additional process generation is not needed, and the process flow, the process time and the process cost are reduced. Meanwhile, the protection region is provided with an opening, and the first conducting layer penetrates through the opening to be connected with the first doping region, so that the first conducting layer is arranged on the first doping region, the first doping region positioned on the periphery of the first conducting layer can form isolation protection on the first conducting layer, and an emitter electrode is isolated from the first conducting layer arranged on the back surface field in the battery prepared by the back surface contact structure, so that the isolation effect is improved, and the recombination of a space charge region is reduced. Meanwhile, the protective area also plays a role of pollutant blocking, so that the sensitivity of surface contamination is reduced; meanwhile, the opening formed in the protection area can be used as an alignment reference in the subsequent preparation of the first conducting layer, so that the first conducting layer can be prepared more accurately; meanwhile, the first doping layer changes the Fermi level, the solid concentration of transition group metal is increased to enhance gettering, the third doping layer changes the Fermi level, interface defects are increased, non-uniform nucleation points can be formed on the interface defects to enhance the gettering effect, and an additional gettering effect is achieved; meanwhile, an isolation region is arranged between the first doping region and the second doping region, so that the first doping region and the second doping region can be separated, and the bad phenomena of electric leakage and the like caused by the fact that the first doping region and the second doping region are connected together without obstruction are avoided; meanwhile, the passivation layer is set to be a porous structure, and the first doping layer and/or the second doping layer are/is embedded in the hole region, so that a conductive channel is formed in the hole region of the passivation layer, and therefore, good resistivity is formed for the passivation layer, the sensitivity of the thickness of the passivation layer on the influence of the resistance is reduced, and the control requirement on the thickness of the passivation layer is reduced, so that the preparation method of the passivation layer can be more diversified than the existing preparation method; meanwhile, a first doping layer is arranged between the silicon substrate and the passivation layer, so that a separation electric field for enhancing surface electron holes is formed, and the field passivation effect is improved; meanwhile, the second doping layer and the third doping layer contain hydrogen elements, and the hydrogen elements can be diffused inwards in the high-temperature process, so that the hydrogen passivation is enhanced.

Drawings

Fig. 1 is a schematic structural diagram of a back contact structure of a solar cell according to an embodiment of the present invention;

fig. 2 and fig. 3 are schematic structural diagrams of various implementations of a solar cell according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "fixed" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The utility model discloses a set up the guard band in first doping district, and do not do any processing in the second doping district, thereby make the setting of the third doping layer in the guard band outmost play anti fish tail effect, avoid leading to the fact the fish tail to the inboard first doping district in its guard band, simultaneously because the height that highly is less than the guard band in second doping district, make only guard band and belt laminate mutually in transmission process, and there is certain clearance and realize unsettledly between second doping district and the belt, consequently, avoid leading to the fact the fish tail to the second doping district in the belt transmission process, make it avoid leading to the fact the problem of fish tail to first doping district and second doping district in the belt transmission process, the problem of the fish tail that has the belt transmission to produce in the current battery preparation process has been solved.

Example one

The embodiment of the utility model provides a back contact structure of solar cell, for the convenience of explanation, only show with the utility model discloses relevant part, it is shown with reference to fig. 1, the embodiment of the utility model provides a back contact structure 20 of solar cell includes:

the first doping area 21 with the polarity opposite to that of the silicon substrate 10 and the second doping area 22 with the polarity same as that of the silicon substrate 10 are arranged on the back surface of the silicon substrate 10 at intervals, and a protection area 23 is arranged on the first doping area 21;

the first doped region 21 and the second doped region 22 each include a first doped layer 211, a passivation layer 212, and a second doped layer 213;

the protection region 23 includes an insulating layer 231 and a third doping layer 232 having the same polarity as the second doping region 22;

an isolation region 24 is arranged between the first doping region 21 and the second doping region 22;

the protection region 23 is provided with an opening to connect the first conductive layer with the first doped region 21;

the first doped region 21 and the second doped region 22 are both higher than the isolation region 24.

Wherein, in one embodiment of the present invention, the silicon substrate 10 has a front surface facing the sun during normal operation and a back surface opposite to the front surface, the front surface is a light receiving surface, and the back surface is disposed on the other side of the silicon substrate 10 opposite to the front surface; that is, the front surface and the back surface are located on different sides and opposite sides of the silicon substrate 10, wherein in this embodiment, the silicon substrate 10 is an N-type monocrystalline silicon wafer, it can be understood that in other embodiments, the silicon substrate 10 may also be other types of silicon wafers such as a polycrystalline silicon wafer or a quasi-monocrystalline silicon wafer, the type of the silicon substrate 10 may also be set to be a P-type, and the silicon substrate 10 is set according to actual use requirements, which is not specifically limited herein.

Wherein, in an embodiment of the present invention, referring to fig. 1, the back contact structure 20 includes a first region and a second region alternately disposed on the back of the silicon substrate 10 and having opposite polarities, wherein the first region includes a first doped region 21 disposed on the back of the silicon substrate 10 and a protection region 23 disposed on the first doped region 21, and the second region includes a second doped region 22 disposed on the back of the silicon substrate 10, wherein the polarity of the first region is opposite to that of the silicon substrate 10, and the polarity of the second region is the same as that of the silicon substrate 10, so in this embodiment, the first doped region 21 in the first region is a P-type doped region, and the second doped region 22 in the second region is an N-type doped region, it can be understood that, in other embodiments of the present invention, when the silicon substrate 10 is a P-type silicon wafer, the first doped region 21 is correspondingly an N-type doped region, the second doped region 22 is correspondingly a P-type doped region.

Further, in an embodiment of the present invention, the first doped region 21 and the second doped region 22 each include a first doped layer 211, a passivation layer 212, and a second doped layer 213, the protection region 23 includes an insulating layer 231 and a third doped layer 232 having the same polarity as that of the second doped region 22, that is, the first region specifically includes the first doped layer 211, the passivation layer 212, the second doped layer 213, the insulating layer 231, and the third doped layer 232, and the polarity of the third doped layer 232 is opposite to that of the second doped layer 213, and the second region specifically includes the first doped layer 211, the passivation layer 212, and the second doped layer 213. That is, the first region is more than the second region by the insulation layer 231 and the third doped layer 232 in the protection region 23. Further, the protection region 23 has an opening to connect the first conductive layer with the first doped region 21 after passing through the opening, i.e., the insulation layer 231 and the third doped layer 232 have a through opening to connect the first conductive layer with the second doped layer 213 after passing through the opening. It should be noted that, as shown in fig. 1, the opening is disposed at the middle position of the insulating layer 231 and the third doped layer 232, so that when the first conductive layer passes through the opening to be connected to the second doped layer 213, the insulating layer 231 and the third doped layer 232 at the periphery of the first conductive layer can form an isolation protection for the first conductive layer. Therefore, in the battery fabricated according to the back contact structure 20 in the present embodiment, as shown in fig. 2 and 3, since the protection region 23 surrounds the periphery of the first conductive layer, the isolation of the emitter from the first conductive layer provided on the back surface field in the battery is formed, thereby reducing the load of the space charge region; meanwhile, the protective area 23 also plays a role of pollutant blocking, so that the sensitivity of surface contamination is reduced; meanwhile, the opening formed in the protection region 23 can be used as an alignment reference in the subsequent preparation of the first conductive layer, so that the first conductive layer can be prepared more accurately. In the embodiment, the third doping layer 232 in the protection region 23 is disposed on the outermost layer, so that a scratch resistant effect is achieved, and the scratch on the first doping region 21 inside the protection region 23 is avoided; meanwhile, as the protection region 23 is arranged on the first doping region 21 and no treatment is carried out on the second doping region 22, the height of the second doping region 22 is lower than that of the protection region 23, so that only the protection region 23 is attached to the belt in the transmission process, and a certain gap exists between the second doping region 22 and the belt to realize suspension, thereby avoiding scratching the second doping region 22 in the belt transmission process.

Further, in an embodiment of the present invention, an isolation region 24 is disposed between the first doping region 21 and the second doping region 22; and the first doped region 21 and the second doped region 22 are both higher than the isolation region 24. It should be noted that the height indicated is a distance from the front side of the silicon substrate 10 to the corresponding structure, such as the height of the first doped region 21 specifically refers to a distance from the front side of the silicon substrate 10 to the outermost third doped layer 232 in the first doped region 21, and the height of the isolation region 24 specifically refers to a distance from the front side of the silicon substrate 10 to the isolation region 24. Specifically, in one embodiment of the present invention, the isolation region 24 is a trench, wherein the first doped region 21 and the second doped region 22 are disposed on the back surface of the silicon substrate 10, and the trench is opened toward the inside of the back surface of the silicon substrate 10, so that the height of the isolation region 24 is necessarily smaller than the height of the first doped region 21 and the second doped region 22, as shown in fig. 2. Wherein the height difference between the second doped region 22 and the isolation region 24 is 0.5-8 um. The first doped region 21 and the second doped region 22 are separated by the trench disposed between the first doped region 21 and the second doped region 22, so as to avoid the bad phenomena of leakage and the like caused by the mutual non-isolated connection of the first doped region 21 and the second doped region 22. It should be noted that the surface topography of the trench contacting the silicon substrate 10 may be provided with a rough texture structure, wherein the rough texture structure is usually formed by texturing, and includes but is not limited to an alkali polished surface, a mechanical polished surface, a random pyramid shape, an inverted pyramid shape, a spherical crown shape, a V-groove shape, and a topography between the above, and it is usually formed by acid texturing to form an irregular hemispherical texture, alkali texturing to form a pyramid shape texture, or alkali texturing to form a pyramid shape texture and then acid texturing to round the pyramid tip of the pyramid, and the surface topography formed at the trench on the back of the silicon substrate 10 is beneficial to increase the absorption and reuse of the silicon substrate 10 for light, so as to increase the short-circuit current density, thereby increasing the conversion efficiency of the solar cell.

Further, in other embodiments of the present invention, the isolation region 24 may also be a protrusion formed by the substrate of the silicon substrate 10, at this time, the back surface of the silicon substrate 10 is spaced apart from each other to form a groove, the first region and the second region are alternately disposed in each groove, the groove can be formed by laser ablation or by a combination of a mask (such as a hard mask, a silicon oxide mask, a silicon nitride mask, a photoresist mask, etc.) and wet/dry etching, at this time, because the groove is spaced apart from the back surface of the silicon substrate 10, the region between two adjacent grooves of the silicon substrate 10 is substantially in the shape of a protrusion, so the back pattern of the silicon substrate 10 is substantially formed by the staggered arrangement of the groove and the protrusion, and at this time, the protrusion is used as the isolation region 24 between the first doping region 21 and the second doping region 22, and the heights of the first doping region 21 and the second doping region 22 are both higher than the height of the isolation region 24, therefore, the outermost third doping layers 232 in the first doping region 21 and the second doping region 22 extend out of the surface of the boss at the top end of the groove, and the first doping region 21 and the second doping region 22 respectively arranged in each groove can be isolated by the boss structure between the grooves of the silicon substrate 10. It should be noted that the surface topography of the raised platform structure may also be provided with a rough texture, as described above. Of course, alternatively, a trench may be disposed between the first doped region 21 and the second doped region 22 in the mesa structure or the groove, so that the first doped region 21 and the second doped region 22 are isolated doubly by the mesa structure and the trench structure between the grooves of the silicon substrate 10 itself.

Further, in an embodiment of the present invention, the groove is arc-shaped, trapezoid-shaped, or square-shaped. The groove is preferably configured as an arc or trapezoid, wherein the groove has a better effect of reflecting light by the inner wall of the groove when configured as an arc or trapezoid, and the groove can increase the surface area of the passivation layer 212 contacting the first doping layer 211. Certainly, when the groove is square, the actual production process is simpler, and it should be noted that the shape of each groove may be the same or different, for example, the groove for setting the first doping region 21 and the groove for setting the second doping region 22 are both square, or the groove for setting the first doping region 21 is square, and the groove for setting the second doping region 22 is arc-shaped, and the like, so that the shape of each groove is set according to the actual use requirement, and is not specifically limited herein. Further, the width and depth of each groove may be set to be the same or different, and the width and depth may be set according to actual use requirements, which is not specifically limited herein.

Further, in an embodiment of the present invention, the height of the first doping region 21 is higher than the height of the second doping region 22. Specifically, it may be that the height of the first doping region 21 is higher than that of the second doping region 22 by controlling the thickness of each film structure of the first doping layer 211, the passivation layer 212, and the second doping layer 213 in the first doping region 21 and the second doping region 22 to be different, respectively. Of course, it is also possible to provide grooves at intervals on the back surface of the silicon substrate 10, and to dispose the first doping regions 21 outside the grooves and the second doping regions 22 inside the grooves, so that the height of the first doping regions 21 is higher than that of the second doping regions 22, as shown in fig. 3. Preferably, the height difference between the first doped region 21 and the second doped region 22 is 1-8um, that is, the depth of the groove is preferably 1-8um under the condition that the film thickness of the first doped region 21 and the film thickness of the second doped region 22 are the same. Wherein for the purpose of blocking between the first doped region 21 and the second doped region 22, a trench may be provided between the first doped region 21 and the second doped region 22, wherein the first doped region 21 and the second doped region 22 are separated by the trench. It is also possible to dispose the first doped region 21 in a partial region outside the groove and the second doped region 22 in a partial region inside the groove, so that the silicon substrate 10 inside and outside the groove without covering the first doped region 21 and the second doped region 22 separates the first doped region 21 and the second doped region 22. Further, the height difference between the second doped region 22 and the isolation region 24 is 0.5-8 um.

In one embodiment of the present invention, the passivation layer 212 in the first doped region 21 and the second doped region 22 is preferably one or more of an oxide layer, a silicon carbide layer, and an amorphous silicon layer; as some examples of the present invention, the passivation layer 212 may be an oxide layer of a single material, a combination of oxide layers of multiple materials and an amorphous silicon layer, a combination of multiple layers of amorphous silicon with different refractive indexes of a single material, or a silicon oxynitride layer, a silicon nitride layer, or the like. It is understood that the specific structural arrangement of the passivation layer 212 includes, but is not limited to, the above listed modes, and the passivation layer 212 is correspondingly configured according to the actual use requirement, which is not specifically limited herein. Further, the thickness of the passivation layer 212 is 0.5-10 nm. As a preferred embodiment of the present invention, the thickness of the passivation layer 212 is preferably 0.8-2 nm. In this case, the thickness of the passivation layer 212 in the first doped region 21 and the second doped region 22 may be set to be as the tunneling layer thickness in the prior art, or may be set to be thicker than the existing tunneling layer thickness, and the like, and the thickness is set according to the actual use requirement, which is not limited specifically herein.

In a preferred embodiment of the present invention, the passivation layer 212 is preferably an oxide layer and a silicon carbide layer, and the oxide layer and the silicon carbide layer are sequentially arranged from the silicon substrate 10 to the outside, and the oxide layer is in contact with the inner first doping layer 211 and the silicon carbide layer is in contact with the outer second doping layer 213. Further, the oxide layer preferably consists of one or more layers of a silicon oxide layer and an aluminum oxide layer; therefore, the passivation layer 212 can also be a combination of the silicon oxide layer and the aluminum oxide layer in the oxide layer. Wherein the silicon carbide layer in the passivation layer 212 comprises a hydrogenated silicon carbide layer. At this time, hydrogen in the hydrogenated silicon carbide layer enters the silicon substrate 10 under the action of a diffusion mechanism and a thermal effect, so that dangling bonds on the back surface of the silicon substrate 10 are neutralized, defects of the silicon substrate 10 are well passivated, energy bands in forbidden bands are transferred to valence bands or conduction bands, and the probability that carriers enter the second doped layer 213 through the passivation layer 212 is improved.

Further, in an embodiment of the present invention, as shown in fig. 1, the passivation layer 212 in the first doped region 21 and the second doped region 22 is a porous structure having the first doped layer 211 and/or the second doped layer 213 in the hole region, and at this time, the passivation layer 212 is a porous structure, and the porous structure thereof can be prepared by additional chemical etching, dry etching, or thermal diffusion impact, and the like, and is prepared according to actual use requirements, which is not limited herein. Note that the porous structure is a porous structure when the passivation layer 212 is viewed from a top view, and the porous structure is a multi-channel structure when the passivation layer 212 is viewed from a cross-sectional view. The holes in the porous structure now exist completely through the passivation layer 212; there is also a groove/gap formed in the surface of the passivation layer 212 that does not extend completely through the passivation layer 212. The pore diameter of the porous structure is smaller than 20um, and specifically, the average pore diameter of each pore is smaller than 20um, or the pore diameters of 90% of all pores are smaller than 20 um. Meanwhile, the ratio of the area of the hole region of the porous structure to the whole area of the porous structure is less than 20%, that is, the passivation layer 212 is sparsely distributed with holes.

In one embodiment of the present invention, the porous structure has the first doping layer 211 and/or the second doping layer 213 in the hole region, that is, the hole region may contain the first doping layer 211, the second doping layer 213, or both of the first doping layer 211 and the second doping layer 213. It should be noted that, during the actual manufacturing process, the hole region of the porous structure may also partially contain the first doped layer 211 and/or the second doped layer 213, and at this time, other portions not filled with the first doped layer 211 and/or the second doped layer 213 are void regions. It should be noted that, in addition to the first doping layer 211 and/or the second doping layer 213, the hole region may also contain impurities (such as hydrogen, oxygen, and various metal elements) generated by precipitation or segregation due to thermal processes (multiple high-temperature treatment processes may exist according to different process flows in the solar cell production). At this time, the passivation layer 212 is set to be a porous structure, and the hole region is provided with the first doping layer 211 and/or the second doping layer 213, so that a conductive channel is formed in the hole region of the passivation layer 212, thereby forming a good resistivity for the passivation layer 212, reducing the sensitivity of the thickness of the passivation layer 212 on the influence of resistance, and reducing the control requirement on the thickness of the passivation layer 212, and therefore, the preparation method of the passivation layer 212 can be more various than the existing methods; meanwhile, the second doping layer 213 is connected with the silicon substrate 10 through the doped hole region and the first doping layer 211 under the porous structure, so that the overall resistance of the prepared battery is further reduced, and the conversion efficiency of the battery is finally improved.

Further, in an embodiment of the present invention, the non-porous region of the porous structure contains a dopant with the same doping type as the first doping layer 211 and/or the second doping layer 213, specifically, when the first doping layer 211 and the second doping layer 213 in the first doping region 21 are doped with P-type dopant (e.g., boron doped) in this embodiment, the non-porous region of the passivation layer 212 in the first doping region 21 contains diffused P-type dopant. When the first doping layer 211 and the second doping layer 213 in the second doping region 22 are doped N-type (e.g., phosphorus doped), the non-hole region of the passivation layer 212 in the second doping region 22 contains diffused N-type dopant.

In an embodiment of the present invention, the first doping layer 211 is located between the silicon substrate 10 and the passivation layer 212, and the first doping layer 211 may be a doping layer directly deposited on the silicon substrate 10 by ion implantation, etc., and the first doping layer 211 is located on the silicon substrate 10, and the passivation layer 212 is prepared on the first doping layer 211; the first doping layer 211 may also be a doping layer formed in the silicon substrate 10 by directly passing the doping source through the passivation layer 212 or through the holes in the porous structure when the second doping layer 213 is formed, at this time, the first doping layer 211 is located in the silicon substrate 10, the corresponding passivation layer 212 is directly formed on the silicon substrate 10, and then, when the second doping layer 213 is formed, the second doping layer is thermally diffused into the silicon substrate 10, so that a portion of the silicon substrate 10 is diffused to become the first doping layer 211. At this time, the doping concentration of the first doping layer 211 is between the doping concentration of the silicon substrate 10 and the doping concentration of the second doping layer 213, and meanwhile, in a preferred embodiment of the present invention, the doping polarities of the first doping layer 211 and the second doping layer 213 are the same, and if the second doping layer 213 in the first doping region 21 is a P-type doping layer, then the first doping layer 211 in the first doping region 21 is also preferably a P-type doping layer; while the second doped layer 213 in the second doped region 22 is an N-type doped layer, the first doped layer 211 in the second doped region 22 is also preferably an N-type doped layer accordingly. At this time, the doping polarities of the first doping layer 211 and the second doping layer 213 in the first doping region 21 are opposite to the doping polarity of the silicon substrate 10.

Preferably, the material of the first doping layer 211 is preferably the same as that of the silicon substrate 10, that is, when the silicon substrate 10 is a monocrystalline silicon wafer, the first doping layer 211 is also preferably a monocrystalline silicon wafer, and the first doping layer 211 is a doped monocrystalline silicon layer doped with group iii or group v elements, in this case, when the second doping layer 213 is an N-type doping layer, the first doping layer 211 is a doped monocrystalline silicon layer doped with group v elements such as nitrogen, phosphorus, arsenic, etc.; when the second doped layer 213 is a P-type doped layer, the first doped layer 211 is a doped monocrystalline silicon layer doped with group iii elements such as boron, aluminum, gallium, etc. It is understood that when the silicon substrate 10 is configured as other types of silicon wafers, the first doped layer 211 thereof may be configured as other types of doped silicon wafers doped with group iii or group v elements, respectively.

Further, in an embodiment of the present invention, the distribution of the first doping layer 211 may be a discrete type or a continuous type, and it may be completely continuous and disposed between the silicon substrate 10 and the passivation layer 212, and may also be a discrete type local distribution near each hole region of the passivation layer 212, at this time, the distribution of the first doping layer 211 may be controlled by the doping process, and the longer the doping time is, the more the doping amount is, the higher the continuous ratio of the first doping layer 211 will be until a completely covered layer of the first doping layer 211 is formed on the silicon substrate 10. Further, the junction depth of the first doped layer 211 is less than 1.5 um. Wherein, the first doping layer 211 is arranged between the silicon substrate 10 and the passivation layer 212 to form a separation electric field for enhancing surface electron holes, so as to improve the field passivation effect; meanwhile, the first doping layer 211 changes the Fermi level, so that the solid concentration of transition metal is increased to enhance the gettering, thereby achieving an additional gettering effect.

Wherein, in an embodiment of the present invention, the second doped layer 213 thereof includes a doped polysilicon layer or a doped silicon carbide layer or a doped amorphous silicon layer. Wherein the doped silicon carbide layer in the second doped layer 213 is composed of at least one doped silicon carbide film with different refractive indexes, and the refractive indexes of the doped silicon carbide films are sequentially decreased from the silicon substrate 10 to the outside. It should be noted that the thickness and refractive index of the doped silicon carbide film can be set according to the actual use requirement, and it is only necessary to decrease the thickness and refractive index from the silicon substrate 10 to the outside in sequence, and is not limited specifically herein. Because the silicon carbide material has wide optical band gap and low absorption coefficient, the parasitic absorption can be reduced, and the short-circuit current density can be effectively improved. Further, the doped silicon carbide layer in the second doped layer 213 includes a doped hydrogenated silicon carbide layer having a conductivity of greater than 0.01S-cm and a thickness of greater than 10 nm. Accordingly, the conductivity and thickness thereof may be set to other values by controlling the conductivity and thickness of the doped hydrogenated silicon carbide layer so as to satisfy the conductivity requirement of the second doped layer 213 thereof, which is not particularly limited herein. It should be noted that the materials of the first doped layer 211 and the second doped layer 213 may be selected to be the same or different, for example, both the first doped layer 211 and the second doped layer 213 are doped polysilicon; the first doped layer 211 may be doped monocrystalline silicon, and the second doped layer 213 may be doped silicon carbide, etc., which are set according to actual use requirements, and are not particularly limited herein.

It should be noted that, the first doped region 21 and the second doped region 22 each include a first doped layer 211, a passivation layer 212, and a second doped layer 213. In this case, the material and thickness of each layer structure in the first doped region 21 may be the same as or different from those of each layer structure in the second doped region 22, for example, when the passivation layer 212 in the first doped region 21 is specifically selected to be a silicon oxide layer and a silicon carbide layer, the passivation layer 212 in the second doped region 22 may be selected to be the same as the passivation layer 212 in the first doped region 21, or selected to be a different material from the passivation layer 212 in the first doped region 21, such as an aluminum oxide layer and a silicon carbide layer.

While the thickness of the passivation layer 212 in the first doped region 21 and the passivation layer 212 in the second doped region 22 may be set to be the same or different, it is preferable that the thickness of the passivation layer 212 corresponding to the group iii element doped in the first doped layer 211 is set to be thicker and the thickness of the other passivation layer 212 corresponding to the group v element doped in the first doped layer 211 is set to be thinner regardless of whether the materials of the passivation layer 212 in the first doped region 21 and the passivation layer 212 in the second doped region 22 are the same. When one of the first doped region 21 and the second doped region 22 is a P-type doped region and the other is an N-type doped region, the thickness of the passivation layer 212 in the P-type doped region is greater than the thickness of the passivation layer 212 in the N-type doped region, specifically, in the present embodiment, the thickness of the passivation layer 212 in the first doped region 21 is greater than the thickness of the passivation layer 212 in the second doped region 22. Accordingly, when the silicon substrate 10 is a P-type silicon wafer, the thickness of the passivation layer 212 in the second doping region 22 is greater than that of the passivation layer 212 in the first doping region 21. The main reason is that the P-type doped region requires boron doping and other processes, requires higher temperature, and requires a thicker passivation layer 212 due to multiple heat treatment processes. In this embodiment, the material and thickness of each layer in the first doped region 21 and the second doped region 22 are set according to actual use requirements, and are not limited herein.

Meanwhile, in the preferred embodiment of the present invention, the hole density of the passivation layer 212 in the P-type doped region is greater than the hole density of the passivation layer 212 in the N-type doped region. The hole density refers to the number of holes per unit area, that is, the number of holes in the passivation layer 212 in the P-type doped region is greater than the number of holes in the passivation layer 212 in the N-type doped region in the same unit area. The main reason is that the P-type doped region has poor conductivity, so more holes are needed to improve the conductivity, and the passivation layer 212 in the P-type doped region has a thicker thickness, so more holes are needed to improve the conductivity. Specifically, in the present embodiment, the hole density of the passivation layer 212 in the first doping region 21 is greater than the hole density of the passivation layer 212 in the second doping region 22.

In an embodiment of the present invention, the insulating layer 231 in the protection region 23 is specifically described with reference to the passivation layer 212, that is, the insulating layer 231 is one or a combination of an oxide layer, a silicon carbide layer, and an amorphous silicon layer; specifically, the insulating layer 231 is preferably an oxide layer and a silicon carbide layer, which are sequentially arranged from the silicon substrate 10, the oxide layer is in contact with the inner second doped layer 213, and the silicon carbide layer is in contact with the outer third doped layer 232. Wherein the silicon carbide layer in the insulating layer 231 comprises a hydrogenated silicon carbide layer. However, it should be noted that the insulating layer 231 is not of the porous structure, and it should be noted that the structures of the passivation layer 212 and the film layer in the insulating layer 231 may be the same or different, so that the passivation layer 212 and/or the insulating layer 231 is one or more of an oxide layer, a silicon carbide layer, and an amorphous silicon layer, for example, when the passivation layer 212 and the insulating layer 231 are both a silicon oxide layer and a silicon carbide layer; if the passivation layer 212 is a silicon oxide layer and a silicon carbide layer, and the insulating layer 231 is an aluminum oxide layer and a silicon carbide layer, the passivation layer 212 and the insulating layer 231 may be respectively disposed according to actual use requirements, and are not particularly limited herein. Further, in the present embodiment, the thickness of the insulating layer 231 is 5 to 150nm, and preferably, the thickness of the insulating layer 231 is greater than the thickness of the passivation layer 212. The insulating layer 231 may also contain a dopant of the same doping type as the second doping layer 213 and/or the third doping layer 232.

In an embodiment of the present invention, the third doped layer 232 in the protection region 23 is specifically described with reference to the second doped layer 213, that is, the third doped layer 232 includes a doped polysilicon layer, a doped silicon carbide layer, or a doped amorphous silicon layer. The doped silicon carbide layer in the third doped layer 232 is composed of at least one doped silicon carbide film with different refractive indexes, and the refractive indexes of the doped silicon carbide films are sequentially reduced from the silicon substrate 10 to the outside. The doped silicon carbide layer in third doped layer 232 comprises a doped hydrogenated silicon carbide layer having a conductivity greater than 0.01S-cm and a thickness greater than 10 nm. Since the second doping layer 213 and the third doping layer 232 contain hydrogen elements, the hydrogen elements can be diffused inwards in a high-temperature process, so that hydrogen passivation is enhanced. It should be noted that the materials of the second doped layer 213 and the third doped layer 232 can also be selected to be the same or different, and therefore the second doped layer 213 and/or the third doped layer 232 comprise a doped polysilicon layer or a doped silicon carbide layer or a doped amorphous silicon layer. It should be noted that the doping polarity of the second doped layer 213 in the first doped region 21 is opposite to that of the third doped layer 232 in the protection region 23. In this embodiment, the second doped layer 213 in the first doped region 21 is a P-type doped layer, and the third doped layer 232 in the protection region 23 is an N-type doped layer. The third doped layer 232 changes the fermi level, increases the interface defects, and can form non-uniform nucleation points on the interface defects to enhance the gettering effect, thereby achieving an additional gettering effect.

In an embodiment of the present invention, when the back contact structure 20 is fabricated, the first doping region 21 is first prepared on the back of the silicon substrate 10, and as described above, the passivation layer 212 in the first doping region 21 is first prepared, then the porous structure is formed on the passivation layer 212 by additional chemical etching, dry etching or thermal diffusion impact, and then the second doping layer 213 in the first doping region 21 is prepared, specifically, intrinsic amorphous silicon is deposited on the passivation layer 212, then a P-type doping source containing boron, aluminum, gallium, etc. is deposited on the intrinsic amorphous silicon or P-type ions containing boron, aluminum, gallium, etc. are injected, then the intrinsic amorphous silicon is changed into P-type doped polysilicon by high temperature crystallization, and then the first doping layer 211 is formed in the silicon substrate 10 after the doping source passes through the passivation layer 212 or the holes in the porous structure during the high temperature crystallization process, thereby preparing the first doped region 21 on the entire back surface of the silicon substrate 10. Then, a patterned etching process (e.g. a masking process) is performed at a position where the second doped region 22 is to be prepared, so as to remove the first doped region 21 at the position where the second doped region 22 is to be prepared and expose the silicon substrate 10, and further, the second doped region 22 is prepared on the entire back surface of the silicon substrate 10, the preparation process is as described above, wherein since the passivation layer 212 and the second doped layer 213 in the second doped region 22 and the insulating layer 231 and the third doped layer 232 in the protection region 23 have similar structures and can use the same materials, and the second doped layer 213 in the second doped region 22 and the third doped layer 232 in the protection region 23 have the same doping polarities, the second doped region 22 and the protection region 23 can be synchronously manufactured by the same process, but it should be noted that the insulating layer 231 does not need to be prepared into a porous structure by additional chemical etching, dry etching, thermal diffusion impact, or the like during the deposition preparation, and the deposition time of the insulating layer 231 is longer than that of the passivation layer 212 in the second doping region 22, so that the thickness of the insulating layer 231 is greater than that of the passivation layer 212 in the second doping region 22. At this time, the protection region 23 is an intermediate generated in the process of producing the second doped region 22, and is obtained by performing local reservation through a graphical design, so that additional process generation is not required, and the process flow, the process time and the process cost are reduced.

In the embodiment, the protection region is arranged on the first doping region, and no treatment is performed on the second doping region, so that the third doping layer in the protection region is arranged on the outermost layer to achieve the scratch resistant effect, scratch to the first doping region on the inner side of the protection region is avoided, meanwhile, the height of the second doping region is lower than that of the protection region, so that only the protection region is attached to the belt in the transmission process, and a certain gap exists between the second doping region and the belt to achieve suspension, scratch to the second doping region in the belt transmission process is avoided, the problem that scratch to the first doping region and the second doping region in the belt transmission process is avoided, and the problem that scratch is generated in the belt transmission process in the existing battery preparation process is solved.

Example two

The second embodiment of the present invention provides a solar cell, for convenience of illustration, only shows the part relevant to the embodiment of the present invention, refer to fig. 2 and fig. 3, the embodiment of the present invention provides a solar cell including:

a silicon substrate 10;

the back contact structure 20 of the previous embodiment disposed on the back side of the silicon substrate 10;

a first dielectric layer 30 disposed on the front surface of the silicon substrate 10;

a first conductive layer 40 disposed on the first doped region 21 in the back contact structure 20 and a second conductive layer 50 disposed on the second doped region 22 in the back contact structure 20; and

a second dielectric layer 60 disposed on the back contact structure 20 and between the first conductive layer 40 and the second conductive layer 50.

In one embodiment of the present invention, the first dielectric layer 30 and the second dielectric layer 60 are one or more of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, and a silicon oxide layer. The first dielectric layer 30 and the second dielectric layer 60 play a role in passivation, the first dielectric layer 30 and the second dielectric layer 60 are at least arranged into a layer structure, the refractive indexes of the layers are sequentially arranged from the silicon substrate 10 outwards in a decreasing mode, the film layer close to the silicon substrate 10 plays a role in passivation, the film layer far away from the silicon substrate 10 plays a role in antireflection, the antireflection effect can be enhanced, the absorption and the utilization of the silicon substrate 10 to light are increased, and the density of short-circuit current is increased. The film layers with different structures in the first dielectric layer 30 and the second dielectric layer may also be composed of multiple films with different refractive indexes, and the refractive indexes of the film layers are arranged in a manner of decreasing from the silicon substrate 10 to the outside in sequence according to the above, for example, the silicon oxide layer in the first dielectric layer 30 may be composed of multiple silicon oxide films with decreasing refractive indexes from the silicon substrate 10 to the outside.

It should be noted that the structures of the first dielectric layer 30 and the second dielectric layer 60 may be arranged the same or differently, and the film structures of the first dielectric layer 30 and the second dielectric layer 60 are correspondingly configured according to actual use requirements, which is not specifically limited herein. Preferably, the first dielectric layer 30 and the second dielectric layer 60 are configured to be the same, so that the first dielectric layer 30 and the second dielectric layer 60 can be prepared by performing front and back preparation on the silicon substrate 10 through the same process.

In a preferred embodiment of the present invention, the first dielectric layer 30 and/or the second dielectric layer 60 are preferably a two-layer structure of an aluminum oxide layer and a silicon carbide layer, or a two-layer structure of a silicon oxide layer and a silicon carbide layer; in this case, the overall thickness of the first dielectric layer 30 is greater than 50nm, and the overall thickness of the second dielectric layer 60 is greater than 25 nm. It is understood that the specific structural arrangement of the first and second dielectric layers 30 and 60 thereof includes, but is not limited to, the specific examples listed above.

Further, in an embodiment of the present invention, the thickness of the aluminum oxide layer or the silicon oxide layer in the first dielectric layer 30 is less than 40nm, the thickness of the aluminum oxide layer or the silicon oxide layer in the second dielectric layer 60 is less than 25nm, and the thickness of the silicon carbide layer in the first dielectric layer 30 and/or the second dielectric layer 60 is greater than 10 nm. The silicon carbide layer in the first dielectric layer 30 and/or the second dielectric layer 60 at this time not only provides a hydrogen passivation effect, but also reduces parasitic light absorption due to a large optical band gap and a small absorption coefficient.

It should be noted that, in the multilayer structure according to the embodiment of the present invention, the sequence is arranged outward from the silicon substrate 10, for example, when the first dielectric layer 30 is an alumina layer and a silicon carbide layer as described above, the alumina layer is close to the silicon substrate 10, and the silicon carbide layer is close to the outside. It should be noted that, in the drawings of the specification, as shown in fig. 2 and fig. 3, only the first dielectric layer 30 and the second dielectric layer 60 are shown as two-layer structures, it can be understood that the first dielectric layer 30 and the second dielectric layer 60 may be other layers, and the specific structure thereof is set according to actual needs, and is not completely shown in the drawings of the specification. It should be noted that, in the drawings of the present invention, it is only used to describe the distribution of each specific structure in the solar cell, but it does not correspond to the actual size of each structure, and it does not completely correspond to the actual size in the embodiment in the drawings, which should be subject to the specific parameters provided in the embodiment.

Further, the silicon carbide layer in the first dielectric layer 30 and/or the second dielectric layer 60 is composed of at least one silicon carbide film having a different refractive index. Wherein the refractive index of each silicon carbide film decreases in order from the silicon substrate 10 to the outside. Alternatively, the refractive indices of the various materials described above may be generally selected as: the refractive index of the single crystal silicon is 3.88; the refractive index of the amorphous silicon is 3.5-4.2; the refractive index of polysilicon is 3.93, the refractive index of silicon carbide is 2-3.88, the refractive index of silicon nitride is 1.9-3.88, the refractive index of silicon oxynitride is 1.45-3.88, the refractive index of silicon oxide is 1.45, and the refractive index of aluminum oxide is 1.63. It is understood that the refractive indexes of the above materials can be set to other values according to the actual use requirement, and are not limited in detail.

Furthermore, in an embodiment of the present invention, the outer layer of the first dielectric layer 30 and/or the second dielectric layer 60 is further provided with a magnesium fluoride layer, that is, on the basis of one or more selected from the group consisting of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer and a silicon oxide layer of the first dielectric layer 30 and the second dielectric layer 60, the outer layer of the first dielectric layer 30 and/or the second dielectric layer 60 may be further provided with a magnesium fluoride layer. The refractive index of the magnesium fluoride layer is required to be the lowest, and is generally set to 1.4, which is used for optical action of enhancing antireflection.

Further, in an embodiment of the present invention, an electric field layer or a floating junction is further disposed between the front surface of the silicon substrate 10 and the first dielectric layer 30, and specifically, the electric field layer is obtained by phosphorus diffusion of the silicon substrate 10, or the floating junction is obtained by boron diffusion of the silicon substrate 10, and the electric field layer or the floating junction is used as the front surface electric field of the solar cell.

Further, in an embodiment of the present invention, the front surface of the silicon substrate 10 is further subjected to a texturing process before the first dielectric layer 30 is prepared, so that the front surface thereof forms a topography including, but not limited to, an alkali polished surface, a mechanically polished surface, a random pyramid, an inverted pyramid, a spherical crown, a V-groove, and a topography between the foregoing topographies, and the surface topography formed on the front surface of the silicon substrate 10 is favorable for reducing the reflection of sunlight on the front surface, thereby improving the conversion efficiency of the solar cell.

In an embodiment of the present invention, the first conductive layer 40 and/or the second conductive layer 50 are TCO transparent conductive film and/or metal electrodes. The metal electrode comprises a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode or a silver-clad copper electrode. Further, the copper electrode is prepared by electroplating copper prepared by an electroplating process or physical vapor deposition. Wherein the electroplated copper uses nickel, chromium, titanium and tungsten electrodes as seed layers or protective layers. It should be noted that the first conductive layer 40 and the second conductive layer 50 may be the same or different, for example, the first conductive layer 40 and the second conductive layer 50 are both aluminum electrodes; or, for example, silver electrodes may be used for the first conductive layer 40 and aluminum electrodes may be used for the second conductive layer 50.

Further, in an embodiment of the present invention, the first conductive layer 40 is disposed on the first doped region 21 and disposed in the opening formed in the protection region 23, and the second conductive layer 50 is disposed on the second doped region 22. In this case, the second dielectric layer 60 is disposed on the backside contact structure 20 and between the first conductive layer 40 and the second conductive layer 50, and correspondingly, the second dielectric layer 60 is disposed on the outermost side of the backside of the entire silicon substrate 10 except for the first conductive layer 40 and the second conductive layer 50, as shown in fig. 2 and 3, and when the isolation region 24 is a trench, the second dielectric layer 60 covers the trench. Correspondingly, during the preparation, the second dielectric layer 60 may be completely covered on the entire back surface of the silicon substrate 10, and then the first conductive layer 40 thereof is electrically connected to the first doped region 21 by penetrating through the second dielectric layer 60 by means of a through hole or the like; the second conductive layer 50 is electrically connected to the second doped region 22 by, for example, vias through the second dielectric layer 60. The conductive polarities of the first conductive layer 40 and the second conductive layer 50 are determined according to the polarities of the first doped region 21 and the second doped region 22, and are not particularly limited herein.

EXAMPLE III

The third embodiment of the present invention further provides a battery module, which includes the solar cell of the second embodiment.

Example four

The fourth embodiment of the present invention further provides a photovoltaic system, which includes the battery module according to the third embodiment.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A back contact structure for a solar cell, comprising:

2. The back contact structure of claim 1, wherein the height of the first doped region is greater than the height of the second doped region.

3. The back contact structure of claim 1, wherein the passivation layer is a porous structure having the first doped layer and/or the second doped layer in a hole region.

4. The back contact structure of claim 3, wherein one of the first doped region and the second doped region is a P-type doped region and the other is an N-type doped region, and wherein a thickness of the passivation layer in the P-type doped region is greater than a thickness of the passivation layer in the N-type doped region.

5. The backside contact structure of claim 3, wherein one of the first doped region and the second doped region is a P-type doped region and the other is an N-type doped region, and the hole density of the passivation layer in the P-type doped region is greater than the hole density of the passivation layer in the N-type doped region.

6. The back contact structure of claim 3, wherein the doping polarity of said first doped layer and said second doped layer are the same.

7. The back contact structure of claim 2, wherein a height difference between the first doped region and the second doped region is 1-8 um.

8. The backside contact structure of claim 1 or 2, wherein a height difference between the second doped region and the isolation region is 0.5-8 um.

9. The backside contact structure of claim 3 wherein the pore size in the porous structure is less than 20 um.

10. The backside contact structure of claim 3 wherein the ratio of the area of the void region of the porous structure to the total area of the porous structure is less than 20%.

11. The backside contact structure of claim 3 wherein the passivation layer has a thickness of 0.5-10 nm.

12. The back contact structure of claim 1, wherein the passivation layer and/or the insulating layer is one or more of an oxide layer, a silicon carbide layer, and an amorphous silicon layer.

13. The back contact structure of claim 1, wherein a doping concentration of the first doped layer is between a doping concentration of the silicon substrate and a doping concentration of the second doped layer.

14. The back contact structure of claim 1, wherein the junction depth of the first doped layer is less than 1.5 um.

15. The back contact structure of claim 1, wherein the first doped layer is a doped monocrystalline silicon layer doped with a group iii or group v element.

16. The back contact structure of claim 1, wherein the second doped layer and/or the third doped layer comprises a doped polysilicon layer or a doped silicon carbide layer or a doped amorphous silicon layer.

17. The back contact structure of claim 16, wherein the doped silicon carbide layers in said second doped layer and/or said third doped layer are comprised of at least one doped silicon carbide film of different refractive index, and the refractive index of each of said doped silicon carbide films decreases sequentially from the silicon substrate outward.

18. The back contact structure of claim 16, wherein the doped silicon carbide layer in the second doped layer and/or the third doped layer comprises a doped hydrogenated silicon carbide layer having an electrical conductivity greater than 0.01S-cm and a thickness greater than 10 nm.

19. The back contact structure of claim 1, wherein the insulating layer has a thickness of 5-150 nm.

20. The back contact structure of claim 1, wherein the insulating layer has a thickness greater than a thickness of the passivation layer.

21. A solar cell, comprising:

a silicon substrate;

the backside contact structure of any of claims 1-20 disposed on the backside of the silicon substrate;

a first dielectric layer disposed on the front side of the silicon substrate;

22. The solar cell of claim 21, wherein the first dielectric layer and the second dielectric layer are one or more combinations of an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbide layer, an amorphous silicon layer, and a silicon oxide layer.

23. The solar cell of claim 22, wherein the first dielectric layer and/or the second dielectric layer is an aluminum oxide layer and a silicon carbide layer, or a silicon oxide layer and a silicon carbide layer;

24. The solar cell of claim 23, wherein the thickness of the aluminum oxide layer or silicon oxide layer in the first dielectric layer is less than 40nm, the thickness of the aluminum oxide layer or silicon oxide layer in the second dielectric layer is less than 25nm, and the thickness of the silicon carbide layer in the first dielectric layer and/or the second dielectric layer is greater than 10 nm.

25. The solar cell according to claim 22 or 23, wherein the silicon carbide layer in the first dielectric layer and/or the second dielectric layer is composed of at least one silicon carbide film having different refractive indexes, and the refractive index of each of the silicon carbide films is sequentially decreased from the silicon substrate to the outside.

26. The solar cell of claim 22, wherein an outer layer of the first dielectric layer and/or the second dielectric layer is further provided with a magnesium fluoride layer.

27. The solar cell of claim 21, wherein the first and second conductive layers are TCO transparent conductive films and/or metal electrodes.

28. The solar cell of claim 27, wherein the metal electrode comprises a silver electrode, a copper electrode, an aluminum electrode, a tin-clad copper electrode, or a silver-clad copper electrode.

29. The solar cell of claim 21, wherein an electric field layer or a floating junction is further disposed between the front surface of the silicon substrate and the first dielectric layer.

30. A battery module comprising a solar cell according to any of claims 21-29.

31. A photovoltaic system comprising the cell assembly of claim 30.