CN201616004U

CN201616004U - All-hardware time synchronizer

Info

Publication number: CN201616004U
Application number: CN 200920085598
Authority: CN
Inventors: 周海斌; 董旭东; 付毅
Original assignee: WUHAN GUODIAN-WUYI ELECTRIC POWER AUTOMATION EQUIPMENT Co Ltd
Current assignee: WUHAN GUODIAN-WUYI ELECTRIC Co Ltd
Priority date: 2009-05-11
Filing date: 2009-05-11
Publication date: 2010-10-27
Anticipated expiration: 2019-05-11

Abstract

An all-hardware time synchronizer comprises a mother board, a power supply plug-in unit, an optical fiber plug-in unit, a master clock plug-in unit, a time keeping plug-in unit and at least an extended output plug-in unit; the plug-in units are connected with the mother board for signal transmission and power supply. A system composed of a plurality of distributed data acquisition units needs a time synchronizer capable of receiving a reference clock source and outputting a standard time tick signal after conversion, and the time synchronizer is used for maintaining the clocks of the units in the system consistent. The traditional time synchronizer adopts a microprocessor to realize the decoding of a clock source signal, reference source selection and the encoding of an output signal, and is susceptible to interference and is difficult to compensate time delay. The all-hardware time synchronizer adopts hardware to realize the decoding and encoding of time signals, the selection and switching of the reference source and the accurate compensation of time delay, accordingly has higher reliability and stability.

Description

Full hardware time synchronizer

Technical Field

The utility model relates to a realize multiple clock source selection, decode with hardware completely, then encode the time synchronizer of standard time tick signals such as output pulse, serial ports, IRIG-B, DCF 77.

Background

A system, such as a substation automation system, is composed of a plurality of distributed data acquisition devices, and data analysis and comprehensive application require that clocks of the devices in the system are kept consistent, so that data recording time scales of the devices are consistent, and therefore, a time synchronization device for receiving a standard time synchronization signal converted by a reference clock source and outputting the standard time synchronization signal needs to be configured in the system.

The traditional time synchronization device adopts a microprocessor to realize the selection and decoding of a clock source signal and the encoding of an output signal, and has the following problems because the device runs according to a program:

1) under the strong electromagnetic interference environment, the program pointer can be interfered to run away, and the device can be temporarily disabled due to reset;

2) the delay from input to output is not fixed, so that the accurate compensation is difficult, and the stability of the output precision is poor.

Disclosure of Invention

In order to overcome the shortcoming of above-mentioned traditional time synchronizer, the utility model provides a full hardware time synchronizer adopts the selection and the switching of decoding, the code and the reference source of field programmable gate array FPGA chip realization time signal.

The utility model provides a technical scheme that its technical problem adopted is: the full hardware time synchronizer includes: the system comprises a motherboard, a power supply plug-in, a fiber-optic plug-in, a main clock plug-in, a time keeping plug-in and at least one extended output plug-in. Each card is connected to the motherboard, and signal transmission and power supply are performed through the motherboard.

The main clock plug-in adopts an FPGA chip to construct a hardware decoding circuit. The master clock plug-in comprises a satellite receiving module (4), a UTC signal decoder (5), an IRIG-B code decoder (6), an output signal encoder (7) and a monitoring module (8). The FPGA chip internally comprises a UTC signal decoder (5), an IRIG-B code decoder (6), an output signal encoder (7) and a monitoring module (8).

When the full hardware time synchronizer operates, the satellite receiving module (4) sends the received UTC signals to the FPGA chip, the FPGA chip decodes according to the specified time sequence and logic, then codes according to the time sequence and logic required by IRIG _ B, 1PPS, TXD and DCF77, and finally outputs a certain number of standard clock signals after being driven and isolated by the expansion plug-in.

As a further improvement and supplement of the scheme, in the scheme, besides the signal output by the satellite receiving module is the main clock signal, the FPGA also accesses a serial port pulse signal and an electric/optical input IRIG-B code signal as a standby clock signal. After the signals are accessed, decoding is firstly carried out, and then effectiveness analysis is carried out. When the satellite receiving system has faults, the FPGA selects and determines a certain effective signal as a reference clock signal according to the priority level.

The utility model has the advantages that: (1) the configuration of the time sequence and the logic relation in the FPGA is completed when the FPGA is powered on, so that the anti-interference capability and the reliability of the device are improved. (2) The FPGA chip works according to a fixed time sequence and logic, the time delay from input to output is determined, accurate compensation can be realized, and the stability of output precision is good.

Drawings

The present invention will be further explained with reference to the drawings and examples.

Fig. 1 is a block diagram of a substation time synchronization system architecture.

In the figure, 1 main time synchronizer, 2 extended time synchronizer, 3 optical fiber channel

FIG. 2 is a schematic diagram of an all hardware time synchronizer.

In the figure, 4, a GPS satellite receiving module, 5, a UTC signal decoder, 6, an IRIG-B code decoder, 7, an output signal encoder, 8, a monitoring module, 9, an IRIG-B code signal input (test), 10, a serial port pulse (test), 11, an optical fiber IRIG-B code input, 12, a backup clock input, 13, an LED display Beijing time, 14, a clock output, 15, a second pulse output, 16, a minute pulse output, 17, a serial port output, 18, an IRIG-B output, 19, a DCF77 output, 20, a time step-out alarm output and 21, a device power-loss alarm output.

Fig. 3 is a structural arrangement diagram of the embodiment.

In the figure, 22 is an optical fiber plug-in, 23 is a main clock plug-in, 24 is a timekeeping plug-in, 25 is a pulse plug-in, 26 is an AC B code plug-in, 27 is a serial plug-in, 28 is a DC B code plug-in, 29 is a DCF77 code plug-in, 30 is a comprehensive plug-in, 31 is a power supply plug-in, 32 is a time display screen, and 33 is a state display lamp.

Detailed Description

In fig. 2, the output of the GPS satellite receiving module (4) is used as a master clock source signal, and an EP2C5T144FPGA chip of the circle II series of the Altera company is used to construct a master clock plug-in. The FPGA comprises a UTC signal decoder (5), an IRIG-B code decoder (6), an output signal encoder (7) and a monitoring module (8) inside, wherein,

the UTC signal decoder (5) decodes the UTC signal output by the GPS satellite receiving module (4);

an IRIG-B code decoder (6) completes the signal decoding of an externally input IRIG-B code;

an output signal encoder (7) encodes the time information of the internal reference and outputs various time setting signals of IRIG _ B, 1PPS, TXD and DCF 77;

a monitoring module (8) monitors the validity of each input signal and selects to determine which input is used as a reference clock source according to the priority.

When the device is powered on, the FPGA of the main clock plug-in reads data in the EEPROM into the on-chip programming RAM, and after configuration is completed, the FPGA operates according to a set time sequence and logic. Generally, a signal output by a GPS satellite receiving module (4) is taken as a reference signal, decoding is carried out by an FPGA according to the time sequence and logic of an input signal, then coding is carried out according to the time sequence and logic required by IRIG B, 1PPS, TXD and DCF77, finally, the signal is transmitted to an expansion plug-in board through a motherboard, and a certain number of standard clock signals are output after being driven and isolated by the expansion plug-in board. When the GPS satellite receiving system has a fault, the FPGA selects a certain effective input signal as a reference clock signal according to the priority level.

Claims

1. Full hardware time synchronizer, characterized by: the system comprises a motherboard, a power supply plug-in, an optical fiber plug-in, a main clock plug-in, a timekeeping plug-in and at least one expansion output plug-in; each card is connected to the motherboard, and signal transmission and power supply are performed through the motherboard.

2. The all-hardware time synchronizer of claim 1, wherein: the master clock plug-in comprises a satellite receiving module (4), a UTC signal decoder (5), an IRIG-B code decoder (6), an output signal encoder (7) and a monitoring module (8); wherein,

the satellite receiving module (4) is connected with the UTC signal decoder (5) and used for converting the received satellite signals into UTC signals and sending the UTC signals to the UCT signal decoder (5);

the UTC signal decoder (5) is connected with the monitoring module (8) and the output encoder (7), decodes the received UTC signal into time information and then sends the time information to the output encoder (7);

the IRIG-B code decoder (6) is connected with the monitoring module (8) and the output encoder (7), decodes the IRIG-B code signal received by the optical fiber plug-in into a time signal and sends the time signal to the output encoder (7);

the monitoring module (8) monitors the validity of the time information sent by the decoder and selects a currently used clock source according to a preset priority;

the output signal encoder (7) encodes the received time signal and outputs a pulse, an IRIG-B code, a serial port signal and a DCF77 signal to each expansion plug-in.

3. The all-hardware time synchronizer of claim 1, wherein: the main clock plug-in adopts an FPGA chip to integrate the UTC signal decoder (5), the IRIG-B code decoder (6), the output signal encoder (7) and the monitoring module (8) in the chip; the functional modules are connected through the internal wiring of the chip in a communication mode.