CN204595397U - Display panel - Google Patents
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- CN204595397U CN204595397U CN201520167928.9U CN201520167928U CN204595397U CN 204595397 U CN204595397 U CN 204595397U CN 201520167928 U CN201520167928 U CN 201520167928U CN 204595397 U CN204595397 U CN 204595397U
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Abstract
The utility model embodiment provides a kind of display panel, it is characterized in that, display panel comprises: a first substrate; Scan line, is positioned on described first substrate; One channel layer, is configured on sweep trace; One data line, to be positioned on first substrate and to be crisscross arranged with sweep trace, data line has at least one overlapping region overlapping with sweep trace, and wherein data line also has a first area overlapping with channel layer in overlapping region, and first area is formed with a through hole; And a spacer, be positioned on data line, the described overlapping region that spacer corresponds to first area partially and corresponds to partially outside first area.The section difference structure of the active cell array layer of the active cell array layer that the display panel provided by the utility model embodiment is formed, increase friction force when spacer is subject to external force, to make spacer more not easily offset, reduce the liquid crystal deflection caused because of spacer skew further abnormal.
Description
Technical field
The utility model relates to a kind of structure of display panel, and refers to a kind of display panel with spacer especially.
Background technology
Thin Film Transistor-LCD (Thin film transistor liquid crystaldisplay, TFT-LCD) common at present comprises active component array base board, colored filter and backlight module.Active component array base board is arranged on substrate by thin film transistor (TFT), and thin film transistor (TFT) is in order to control the voltage of sub-pixel (sub-pixel), adjustable liquid crystal display molecule deflection angle by this, then through the GTG of the further determinant pixel of polaroid.The GTG collocation of the light therethrough sub-pixel sent by back light member or self-emission device is enameled optical filter, thus forms image frame.
Due to the improvement of touch technology, at present replace known mouse and keyboard equal controller to manipulate cursor on display panel and graphic etc. mainly with touch-control, and when user uses display panel, can touch the surface of display panel, now the substrate of display panel easily presses down slightly because of stressed.In general, also can press down along with substrate in order to the spacer of layout upper and lower base plate in display panel and modification or skew are slided, but the skew of spacer easily causes liquid crystal deflection abnormal, thus cause the image display of display panel abnormal.
Utility model content
The utility model embodiment provides a kind of display panel, and the active cell array layer that it is formed can improve the situation that spacer offsets because of stressed.
The utility model is a kind of display panel of providing of an embodiment wherein, and it comprises first substrate, second substrate, sweep trace, channel layer, data line and spacer.Sweep trace is positioned on first substrate.Channel layer is configured on sweep trace.Data line bit is on first substrate and be crisscross arranged with described sweep trace, described data line has at least one overlapping region overlapping with described sweep trace, wherein said data line also has a first area overlapping with described channel layer in described overlapping region, and described first area is formed with via clearance is positioned on data line, the described overlapping region that spacer corresponds to first area partially and corresponds to partially outside described first area.
Described overlapping region outside wherein said first area also comprises a second area and one the 3rd region, described sweep trace has a first side and a second side, described data line has one the 3rd side and a four side, described first area has the 5th side of a contiguous described first side and the 6th side of a contiguous described second side, and described second area is by described 5th side, described first side, described 3rd side and described four side formed, described 3rd region is by described 6th side, described second side, described 3rd side and described four side formed.
Described 5th side of wherein said first area and described 6th side are all parallel to the bearing of trend of described sweep trace.
Have one first bee-line between wherein said first side and described 5th side, have one second bee-line between described second side and described 6th side, wherein said first bee-line is greater than described second bee-line.
Wherein said spacer corresponds to described first area and described 3rd region partially.
Wherein said first substrate has a first surface and described data line has a second surface, in described first area, described second surface and described first surface are at a distance of one first height, in described 3rd region, described second surface and described first surface are at a distance of one second height, and described first is highly greater than described second height.
Wherein said display panel also comprises a pixel electrode, and described pixel electrode is covered in described first side.
Wherein said sweep trace has one first inner fovea part, and described data line is by described first inner fovea part.
Wherein said sweep trace also has one second inner fovea part, and described second inner fovea part and described first inner fovea part are oppositely arranged.
Wherein said channel layer is a metal oxide semiconductor layer.
A kind of display panel that the other embodiment of the utility model provides, it comprises first substrate, sweep trace, channel layer, data line and pixel electrode.Sweep trace to be positioned on first substrate and to have first side and second side.Channel layer is configured on sweep trace.Pixel electrode is positioned on first substrate.Data line bit is on first substrate and be crisscross arranged with sweep trace, and data line has at least one overlapping region overlapping with sweep trace, and wherein data line also has a first area overlapping with channel layer in overlapping region, and first area is formed with through hole.Wherein, have the first bee-line between first side and the 5th side, have the second bee-line between second side and six sides, wherein the first bee-line is greater than the second bee-line.
Wherein said display panel also comprises a spacer, and described spacer part corresponds to described first area.
Wherein said spacer part corresponds to the described overlapping region outside described first area.
Described overlapping region outside wherein said first area also comprises a second area and one the 3rd region, described data line has one the 3rd side and a four side, and described second area is made up of described 5th side, described first side, described 3rd side and described four side, described 3rd region is made up of described 6th side, described second side, described 3rd side and described four side, and described spacer corresponds to described first area and described 3rd region partially.
Wherein said first substrate has a first surface and described data line has a second surface, described spacer corresponds to described first area and described 3rd region partially, in described first area, described second surface and described first surface are at a distance of one first height, in described 3rd region, described second surface and described first surface are at a distance of one second height, and described first is highly greater than described second height.
Described 5th side of wherein said first area and described 6th side are all parallel to the bearing of trend of described sweep trace.
Wherein said sweep trace has one first inner fovea part, and described data line is by described first inner fovea part.
Wherein said sweep trace also has one second inner fovea part, and described second inner fovea part and described first inner fovea part are oppositely arranged.
Wherein said channel layer is a metal oxide semiconductor layer.
In sum, its spacer of display panel PS of providing of the utility model embodiment correspond to first area partially and correspond to partially second area and the 3rd region at least one of them.Furthermore, in the scope of corresponding overlapping region, data line is stacked on channel layer and sweep trace, and spacer partly corresponds on data line, channel layer and sweep trace.Due to the active cell array layer section of being formed difference structure, when user touches the second substrate of display panel, second substrate is stressed and press down slightly, and spacer is conflicted on data line.Because the spacer of part corresponds to first area, and the spacer of another part corresponds to second area or the 3rd region, thus spacer contacts at the section difference structure of the active cell array layer with the first height and the second height accordingly.Therefore, when spacer corresponds to first area partially and corresponds to second area or the 3rd region partially, by the section difference structure of active cell array layer, increase friction force when spacer is subject to external force, to make spacer more not easily offset, reduce the liquid crystal deflection caused because of spacer skew further abnormal.
In addition, channel layer can compared with the pixel electrode be electrically connected away from it relatively its pixel electrode be not electrically connected, the allocation position of pixel electrode can be partly overlapping with channel layer and be covered in the first side of sweep trace.In this, the protuberance of pixel electrode can be avoided because offset and easily overlapping with data line situation in manufacturing process, the back of the body formation of raceway groove or the situation of the increase of stray capacitance may to be improved further.
In addition, sweep trace can have the first inner fovea part, and in this, the sweep trace being formed with the first inner fovea part can reduce the area overlapping with data line, thus reduces the increase situation being present in the stray capacitance of sweep trace and data line overlapping.In addition, when preparing the step of data line on channel layer and sweep trace, because the gradient of the sweep trace of the first inner fovea part is more slow, compared to the sweep trace not being formed with the first inner fovea part, data line is easier to be produced on the sweep trace being formed with the first inner fovea part.
What deserves to be explained is, in other embodiments, sweep trace can also have the second inner fovea part, second inner fovea part and the first inner fovea part are oppositely arranged and are all arranged at the staggered place of sweep trace and data line, thus data line be more easily produced on be formed with the first inner fovea part and the second inner fovea part sweep trace on, and more preferably reduce and be present in the stray capacitance of sweep trace and data line overlapping.
Further understand feature of the present utility model and technology contents for enable, refer to following about detailed description of the present utility model and accompanying drawing, but institute's accompanying drawings only provides with reference to and use is described, be not used for the utility model in addition limitr.
Accompanying drawing explanation
Fig. 1 is the diagrammatic cross-section of the display panel of the utility model one embodiment.
Fig. 2 be the utility model one embodiment the diagrammatic top schematic diagram of first substrate.
Fig. 3 is the partial structurtes schematic diagram of the active cell array layer of the utility model one embodiment.
Fig. 4 A is the diagrammatic cross-section that in Fig. 3, M-M ' section along the line illustrates.
Fig. 4 B is the using state diagrammatic cross-section in Fig. 4 A.
Fig. 4 C is the using state diagrammatic cross-section that in Fig. 3, N-N ' section along the line illustrates.
Fig. 5 is the partial schematic schematic top plan view of the display panel of another embodiment of the utility model.
Fig. 6 is the partial schematic schematic top plan view of the display panel of another embodiment of the utility model.
Fig. 7 is the partial schematic schematic top plan view of the display panel of another embodiment of the utility model.
[the symbol simple declaration of figure]:
100 display panel 110 sweep traces
120 channel layer 130 data lines
131 drain electrode 140 protective seams
B1 first substrate B2 second substrate
CFa light shield layer CFb colored filter
LQ liquid crystal layer CF chromatic filter layer
T1 active cell array layer PI alignment film
PS spacer V1, V2 through hole
110a first inner fovea part AA overlapping region
A1 first area A2 second area
A3 the 3rd region
E1 first surface E2 second surface
F1, F2, FN sub-pixel unit H1 first height
H2 second height LQ liquid crystal layer
PI alignment film
PX, PX ' pixel electrode PX1 protuberance
S1 ~ S6 first side ~ the 6th side
U1 data line drive unit U2 scanning line driving unit
W1 first bee-line W2 second bee-line.
Embodiment
In alterations, show some exemplary embodiments, and hereafter will consult alterations to describe various exemplary embodiments more fully.What deserves to be explained is, the utility model concept may embody in many different forms, and should not be construed as be limited to herein the exemplary embodiments set forth.Specifically, these exemplary embodiments are provided to make the utility model for detailed and complete, and will will fully pass on the category of the utility model concept to those who familiarize themselves with the technology.In each is graphic, in order to make illustrated each layer and each region can be explicit, and the ratio of its relative size can be lavished praise on oneself, and similar numeral indicates like all the time.
Fig. 1 is the diagrammatic cross-section of the display panel of the utility model one embodiment.In the present embodiment, display panel 100 is a liquid crystal panel.Display panel 100 comprises first substrate B1, second substrate B2, chromatic filter layer CF, liquid crystal layer LQ, active cell array layer T1 and spacer PS.First substrate B1 is combined with second substrate B2, and liquid crystal layer LQ and active cell array layer T1 and spacer PS is between first substrate B1 and second substrate B2.In general, active cell array layer T1 is configured on first substrate B1, to form an active component array base board.Chromatic filter layer CF can be configured on second substrate B2 and to comprise the colored filter CFb of light shield layer CFa and multi-disc shades of colour.Liquid crystal layer LQ is configured at the gap between first substrate B1 and second substrate B2, in order to change the direction of incident light.In addition, display panel 100 can also comprise alignment film PI.Alignment film PI is folded in outside liquid crystal layer LQ haply between liquid crystal layer LQ and active cell array layer T1, controls liquid crystal sense of rotation through active cell array layer T1 and alignment film PI.
Fig. 2 is the diagrammatic top schematic diagram of the first substrate of the utility model one embodiment.Fig. 3 is the partial structurtes schematic diagram of the active cell array layer of the utility model one embodiment.Refer to Fig. 2 and Fig. 3, data line drive unit U1 be configured at active component array base board wherein, and scanning line driving unit U2 be configured at active component array base board in addition on one side.In the present embodiment, active cell array layer T1 comprises sweep trace 110, channel layer 120 and data line 130.Sweep trace 110 is positioned at B1 on first substrate, and channel layer 120 is configured on sweep trace 110, and data line 130 is positioned on first substrate and is crisscross arranged on B1 and with sweep trace 110, and is positioned on channel layer 120.In practice, multi-strip scanning line 110 with row direction extend and it is parallel to each other, and a plurality of data lines 130 with line direction extend and it is substantial parallel each other.Wherein, these sweep traces 110 and data line 130 are interlaced with each other stacked and define a plurality of sub-pixel unit FN, N and be greater than 1, such as, be F1, F2 etc.
Channel layer 120 is semi-conductor layer, the optional free polysilicon layer of its material, metal oxide semiconductor layer, one of them of group formed with amorphous silicon layer.In the present embodiment, the material of channel layer 120 can be selected from indium oxide gallium zinc (Indium-Gallium-Zinc Oxide, IGZO), zinc paste (Zinc oxide, ZnO), tin oxide (Stannous oxide, SnO), indium zinc oxide (Indium-ZincOxide, IZO), gallium oxide zinc (Gallium-Zinc Oxide, GaZnO), zinc-tin oxide (Zinc-TinOxide, ZTO), tin indium oxide (Indium-Tin Oxide, ITO) and to mix among the group that forms wherein a kind of.In the present embodiment, the material of channel layer 120 is indium oxide gallium zinc.But, the utility model is not limited this.Specifically, channel layer 120 can be through magnetic control sputtering plating method (magnetron sputtering), Metalorganic Chemical Vapor Deposition (metal organicchemical-vapor deposition, or pulsed laser vapour deposition method (pulsed laserdeposition, PLD) and making MOCVD).
Protective seam 140 is configured on channel layer 120, and causes electric characteristic abnormality in order to the etch stop layer (etch stop layer, ESL) as channel layer 120 to avoid follow-up channel layer 120 to be damaged in subsequent technique process.The material of protective seam 140 is monox (SiO
x) etc.Protective seam 140 can through lithography technique by protective seam 140 patterning to form through hole V1 and through hole V2 at protective seam 140, data line 130 to overlap on protective seam 140 and forms the source electrode contacted with channel layer 120 by through hole V1.In time forming data line and source electrode, form by same process or same technique the drain electrode 131 contacted with channel layer 120 at through hole V2 inwall, and described drain electrode 131 insulate with data line 130 and source electrode to arrange.
Spacer PS (Spacer), between the data line 130 and second substrate B2 of active cell array layer T1, is beneficial to maintain the gap (Cell gap) between first substrate B1 and second substrate B2.In the present embodiment, spacer PS is formed on chromatic filter layer CF and direction towards active cell array layer T1 extends.Haply, spacer PS corresponds to sweep trace 110 and data line 130 and to interlock part, and is roughly contacted with the alignment film PI be positioned at above data line 130.Specifically, spacer PS can be designed to spherical, polygon corner post shape, coniform, polygon pyramidal, Multilayer stack shape or separator plate like etc.What deserves to be explained is, spacer PS can be assorted or transparent photoresist, macromolecular material or silica material, formed with lithography process, sputter (Sputtering process), chemical vapour deposition technique (Chemical Vapor Deposition, CVD) or modes such as (Spray) of spraying.But, the utility model is not limited the design and craft condition of spacer PS.
Specifically, sweep trace 110 has first side S1 and second side S2, and data line 130 has the 3rd side S3 and four side S4.See it from spacer PS toward first substrate B1 direction from overlooking visual angle, data line 130 is positioned on sweep trace 110 to be established with staggered the folding of sweep trace 110, and some of data line 130 is positioned at directly over channel layer 120 and sweep trace 110.Therefore, data line 130 has the overlapping region AA of at least one sweep trace 110 overlap, and wherein data line also has the first area A1 overlapping with channel layer 130 in the AA of overlapping region.Overlapping region AA is formed by first side S1, second side S2, the 3rd side S3 and four side structure that S4 encloses, and first area A1 has the 5th side S5 and the 6th side S6 and first area A1 is formed by the 3rd side S1, four side S4, the 5th side S5 and the 6th side structure that S6 encloses.Wherein, the 5th side S5 is the side of the more contiguous first side S1 of first area A1, and the 6th side S6 is the side of the more contiguous second side S2 of overlapping region AA.In fact, the 5th side S5 and the 6th side S6 is all parallel to the bearing of trend of sweep trace 110.
It is seen from spacer PS toward first substrate B1 direction from overlooking visual angle, the data line 130 of some is only positioned on sweep trace 110 not overlapping with channel layer 120 in addition, therefore the overlapping region AA outside the A1 of first area also comprises second area A2 and the 3rd region A3.Wherein, second area A2 is made up of first side S1, the 3rd side S3, four side S4 and the 5th side S5, and the 3rd region A3 is made up of second side S2, the 3rd side S3, four side S4 and the 6th side S6.What deserves to be explained is, the overlapping region AA that spacer PS corresponds to first area A1 partially and corresponds to partially outside the A1 of first area, be such as second area A or the 3rd region A3 at least one of them.
Fig. 4 A is the diagrammatic cross-section that in Fig. 3, M-M ' section along the line illustrates.Fig. 4 B is the using state diagrammatic cross-section in Fig. 4 A.Fig. 4 C is the diagrammatic cross-section that in Fig. 3, N-N ' section along the line illustrates.Refer to Fig. 4 A to Fig. 4 C and coordinate contrast Fig. 3, in the present embodiment, spacer PS corresponds to first area A1 partially and corresponds to the 3rd region A3 partially.Furthermore, in the scope of corresponding first area A1, data line 130 is stacked on channel layer 120 and sweep trace 110, and spacer PS partly corresponds on data line 130, channel layer 120 and sweep trace 110, between the second surface E2 of the data line 130 and first surface E1 of first substrate B1, there is the first height H 1 apart.In the scope of corresponding 3rd region A3, data line 130 is only stacked on sweep trace 110 haply, spacer PS partly corresponds on data line 130 outside channel layer 120 and sweep trace 110, has the second height H 2 between the second surface E2 of the data line 130 and first surface E1 of first substrate B1 apart.Due in different regional extents (overlapping region AA and second area A2), lack the thickness of channel layer 120, so between the second surface E2 of the data line 130 and first surface E1 of first substrate B1, height is apart different, and the first height H 1 is greater than the second height H 2.Accordingly, active cell array layer T1 has multiple offset height, and forms break difference structure.
As Fig. 4 B and Fig. 4 C illustrate, when user touches the second substrate B2 of display panel 100, second substrate B2 is stressed and press down slightly, make spacer PS conflict on data line 130 (or alignment film PI).Because the spacer PS of part corresponds to first area A1, and the spacer PS of another part corresponds to the 3rd region A3, thus spacer PS contacts at the break difference structure of the active cell array layer T1 with the first height H 1 and the second height H 2 accordingly.Therefore, when spacer PS corresponds to overlapping region AA partially and corresponds to second area A2 partially, by the break difference structure of active cell array layer T1, increase friction force when spacer PS is subject to external force, to make spacer PS more not easily offset, reduce the liquid crystal deflection caused because spacer PS offsets further abnormal.
Fig. 5 is the partial schematic schematic top plan view of the display panel of another embodiment of the utility model.Refer to Fig. 5, have the first bee-line W1 between first side S1 and the 5th side S5, have the second bee-line between second side S2 and the 6th side S6, wherein the first bee-line W1 is greater than the second bee-line W2.That is, the 5th side S5 of first area A1 and the 6th side S6 respectively with the first side S1 of sweep trace 110 and second side S2 at a distance of the first bee-line W1 and the second bee-line W2.In one embodiment, preferably, the first bee-line W1 is greater than the second bee-line W2.That is, the 5th side S5 and first side S1 the first bee-line W1 is apart greater than the 6th side S6 and second side S2 the second bee-line W2 apart.What deserves to be explained is, seeing it from spacer PS toward first substrate B1 direction from overlooking visual angle, compared to by sweep trace 110 and data line 130 enclose the sub-pixel unit F1 of structure, the position of channel layer 120 can closer next sub-pixel unit F2.That is channel layer 120 is compared with the pixel electrode PX be electrically connected away from it, and relatively its pixel electrode PX ' be not electrically connected.
Therefore, when spacer PS corresponds to first area A1 partially and corresponds to the 3rd region A3 partially, namely spacer PS can be mapped to the break difference structure of active cell array layer T1 in shorter scope, thus spacer PS is subject to the friction force increase of external force and wish skew, spacer PS more not easily offsets.
Fig. 6 is the partial schematic schematic top plan view of the display panel of another embodiment of the utility model.Refer to Fig. 6, in practice, consider the condition that need meet process parameters design or LCD alignment, the shape of pixel electrode PX can be designed with at least one protuberance PX1.In one embodiment, preferably, when the first bee-line W1 is greater than the second bee-line W2, that is channel layer 120 compared with the pixel electrode PX be electrically connected away from it, relatively the allocation position of its pixel electrode PX ' be not electrically connected, pixel electrode PX can be partly overlapping with channel layer 120 and be covered in the first side S1 of sweep trace 110.In this, the protuberance PX1 of pixel electrode PX can be avoided because offset and easily overlapping with data line 130 situation in manufacturing process, the back of the body formation of raceway groove or the situation of the increase of stray capacitance may to be improved further.
Fig. 7 is the partial schematic schematic top plan view of the display panel of another embodiment of the utility model.Refer to Fig. 7, in one embodiment, sweep trace 110 extends with the direction of row haply and has the first inner fovea part 110a, and the first inner fovea part 110a is positioned at the staggered place of sweep trace 110 and data line 130.In this embodiment, the first inner fovea part 110a is positioned at the S1 place, first side of sweep trace 110, and is positioned at the staggered place of sweep trace 110 and data line 130.Data line 130 to be stacked on channel layer 120 and sweep trace 110 and by the first inner fovea part 110a.In this, the sweep trace 110 being formed with the first inner fovea part 110a can reduce the area overlapping with data line 130, that is reduces the area of second area A2, thus reduces the increase situation of the stray capacitance being present in sweep trace 110 and data line 130 overlapping.In addition, when preparing the step of data line 130 on channel layer 120 and sweep trace 110, because the gradient of the sweep trace 110 of the first inner fovea part 110a is more slow, compared to the sweep trace 110 not being formed with the first inner fovea part 110a, data line 130 be easier to be produced on the sweep trace 110 being formed with the first inner fovea part 110a position and do not have because sweep trace 110 height offset and cause the problem that data line 130 ruptures.What deserves to be explained is, in other embodiments, sweep trace 110 also can have the second inner fovea part (not illustrating), second inner fovea part and the first inner fovea part 110a are relatively arranged on sweep trace 110 dual side-edge and are all arranged at the staggered place of sweep trace 110 and data line 130, thus data line 110 be more easily produced on be formed with the first inner fovea part 110a and the second inner fovea part sweep trace 110 on, and reduce the area of second area A2 and the 3rd region A3, thus more preferably reduce the stray capacitance being present in sweep trace 110 and data line 130 overlapping.
(possible effect of embodiment)
In sum, its spacer of display panel PS of providing of the utility model embodiment correspond to first area partially and correspond to partially second area and the 3rd region at least one of them.Furthermore, in the scope of corresponding overlapping region, data line is stacked on channel layer and sweep trace, and spacer partly corresponds on data line, channel layer and sweep trace.Due to the active cell array layer section of being formed difference structure, when user touches the second substrate of display panel, second substrate is stressed and press down slightly, and spacer is conflicted on data line.Because the spacer of part corresponds to first area, and the spacer of another part corresponds to second area or the 3rd region, thus spacer contacts at the break difference structure of the active cell array layer with the first height and the second height accordingly.Therefore, when spacer corresponds to first area partially and corresponds to second area or the 3rd region partially, by the break difference structure of active cell array layer, increase friction force when spacer is subject to external force, to make spacer more not easily offset, reduce the liquid crystal deflection caused because of spacer skew further abnormal.
In addition, channel layer can compared with the pixel electrode be electrically connected away from it relatively its pixel electrode be not electrically connected, the allocation position of pixel electrode can be partly overlapping with channel layer and be covered in the first side of sweep trace.In this, the protuberance of pixel electrode can be avoided because offset and easily overlapping with data line situation in manufacturing process, the back of the body formation of raceway groove or the situation of the increase of stray capacitance may to be improved further.
In addition, sweep trace can have the first inner fovea part, and in this, the sweep trace being formed with the first inner fovea part can reduce the area overlapping with data line, thus reduces the increase situation being present in the stray capacitance of sweep trace and data line overlapping.In addition, when preparing the step of data line on channel layer and sweep trace, because the gradient of the sweep trace of the first inner fovea part is more slow, compared to the sweep trace not being formed with the first inner fovea part, data line is easier to be produced on the sweep trace being formed with the first inner fovea part.
What deserves to be explained is, in other embodiments, sweep trace can also have the second inner fovea part, second inner fovea part and the first inner fovea part are oppositely arranged and are all arranged at the staggered place of sweep trace and data line, thus data line be more easily produced on be formed with the first inner fovea part and the second inner fovea part sweep trace on, and more preferably reduce and be present in the stray capacitance of sweep trace and data line overlapping.
The foregoing is only better possible embodiments of the present utility model, non-ly therefore limit to the scope of the claims of the present utility model, therefore the equivalence techniques change of such as using the utility model instructions and graphic content to do, be all contained in protection domain of the present utility model.
Claims (19)
1. a display panel, is characterized in that, described display panel comprises:
One first substrate;
Scan line, is positioned on described first substrate;
One channel layer, is configured on described sweep trace;
One data line, to be positioned on described first substrate and to be crisscross arranged with described sweep trace, described data line has at least one overlapping region overlapping with described sweep trace, wherein said data line also has a first area overlapping with described channel layer in described overlapping region, and described first area is formed with a through hole; And
One spacer, is positioned on described data line, the described overlapping region that described spacer corresponds to described first area partially and corresponds to partially outside described first area.
2. display panel according to claim 1, described overlapping region outside wherein said first area also comprises a second area and one the 3rd region, described sweep trace has a first side and a second side, described data line has one the 3rd side and a four side, described first area has the 5th side of a contiguous described first side and the 6th side of a contiguous described second side, and described second area is by described 5th side, described first side, described 3rd side and described four side formed, described 3rd region is by described 6th side, described second side, described 3rd side and described four side formed.
3. display panel according to claim 2, described 5th side of wherein said first area and described 6th side are all parallel to the bearing of trend of described sweep trace.
4. display panel according to claim 2, between wherein said first side and described 5th side, there is one first bee-line, have one second bee-line between described second side and described 6th side, wherein said first bee-line is greater than described second bee-line.
5. display panel according to claim 4, wherein said spacer corresponds to described first area and described 3rd region partially.
6. display panel according to claim 5, wherein said first substrate has a first surface and described data line has a second surface, in described first area, described second surface and described first surface are at a distance of one first height, in described 3rd region, described second surface and described first surface are at a distance of one second height, and described first is highly greater than described second height.
7. display panel according to claim 4, wherein said display panel also comprises a pixel electrode, and described pixel electrode is covered in described first side.
8. display panel according to claim 1, wherein said sweep trace has one first inner fovea part, and described data line is by described first inner fovea part.
9. display panel according to claim 8, wherein said sweep trace also has one second inner fovea part, and described second inner fovea part and described first inner fovea part are oppositely arranged.
10. display panel according to claim 1, wherein said channel layer is a metal oxide semiconductor layer.
11. 1 display panels, is characterized in that, described display panel comprises:
One first substrate;
Scan line, is positioned on described first substrate, and wherein said sweep trace has a first side and a second side;
One channel layer, is configured on described sweep trace;
One pixel electrode, is positioned on described first substrate; And
One data line, to be positioned on first substrate and to be crisscross arranged with described sweep trace, described data line has at least one overlapping region overlapping with described sweep trace, wherein said data line also has a first area overlapping with described channel layer in described overlapping region, and described first area is formed with a through hole
Wherein, described first area has the 5th side of a contiguous described first side and the 6th side of a contiguous described second side, and between described first side and described 5th side, there is one first bee-line, between described second side and described 6th side, there is one second bee-line, and described first bee-line is greater than described second bee-line.
12. according to the display panel described in claim 11, and wherein said display panel also comprises a spacer, and described spacer part corresponds to described first area.
13. according to the display panel described in claim 12, and wherein said spacer part corresponds to the described overlapping region outside described first area.
14. according to the display panel described in claim 13, described overlapping region outside wherein said first area also comprises a second area and one the 3rd region, described data line has one the 3rd side and a four side, and described second area is made up of described 5th side, described first side, described 3rd side and described four side, described 3rd region is made up of described 6th side, described second side, described 3rd side and described four side, and described spacer corresponds to described first area and described 3rd region partially.
15. according to the display panel described in claim 14, wherein said first substrate has a first surface and described data line has a second surface, described spacer corresponds to described first area and described 3rd region partially, in described first area, described second surface and described first surface are at a distance of one first height, in described 3rd region, described second surface and described first surface are at a distance of one second height, and described first is highly greater than described second height.
16. according to the display panel described in claim 11, and described 5th side of wherein said first area and described 6th side are all parallel to the bearing of trend of described sweep trace.
17. according to the display panel described in claim 11, and wherein said sweep trace has one first inner fovea part, and described data line is by described first inner fovea part.
18. according to the display panel described in claim 17, and wherein said sweep trace also has one second inner fovea part, and described second inner fovea part and described first inner fovea part are oppositely arranged.
19. according to the display panel described in claim 11, and wherein said channel layer is a metal oxide semiconductor layer.
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| CN201520167928.9U CN204595397U (en) | 2015-03-24 | 2015-03-24 | Display panel |
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| CN201520167928.9U CN204595397U (en) | 2015-03-24 | 2015-03-24 | Display panel |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154648A (en) * | 2015-03-24 | 2016-11-23 | 群创光电股份有限公司 | Display floater |
| CN107065318A (en) * | 2017-05-24 | 2017-08-18 | 上海中航光电子有限公司 | A kind of liquid crystal display panel and display device |
| CN107664890A (en) * | 2017-09-20 | 2018-02-06 | 京东方科技集团股份有限公司 | Flexible array substrate and preparation method thereof |
-
2015
- 2015-03-24 CN CN201520167928.9U patent/CN204595397U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154648A (en) * | 2015-03-24 | 2016-11-23 | 群创光电股份有限公司 | Display floater |
| CN107065318A (en) * | 2017-05-24 | 2017-08-18 | 上海中航光电子有限公司 | A kind of liquid crystal display panel and display device |
| CN107664890A (en) * | 2017-09-20 | 2018-02-06 | 京东方科技集团股份有限公司 | Flexible array substrate and preparation method thereof |
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