CN1591824A - Structure of realizing 40 bit fast accumulation subtraction apparatus circuit with roundoff function - Google Patents
Structure of realizing 40 bit fast accumulation subtraction apparatus circuit with roundoff function Download PDFInfo
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- CN1591824A CN1591824A CN 03155314 CN03155314A CN1591824A CN 1591824 A CN1591824 A CN 1591824A CN 03155314 CN03155314 CN 03155314 CN 03155314 A CN03155314 A CN 03155314A CN 1591824 A CN1591824 A CN 1591824A
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Abstract
The present invention relates to a structure for implementing 40-digit quick progressive adder and progressive subtractor circuit with rounding-off function. Said structure includes an addition compression module, a substration compression module, an addition operation module, a substration operation module, a 15-digit adder, a 15-digit substrator and a 40-digit operation result selection multi-selector. Said invention also provides action of every module and its final operation result selection and output method.
Description
Technical field
The invention belongs to high speed, the low power consumption integrated circuit design in microelectronics field, be meant a kind of quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions especially.
Background technology
Multiplication adds up/tires out and subtracts the basic processing unit of computing as Digital Signal Processing, in complicated day by day digital signal processing, use very frequently, add up/special use that accumulation subtraction apparatus is realized, the focus that nextport universal digital signal processor NextPort (DSP) also becomes integrated circuit (IC) design of new generation based on multiplication.Be widely used in the fixed DSP in communication field, the multimedia consumption electronic product at present, adopt 16 data width mostly.
Add up/accumulation subtraction apparatus is as the important component part of parallel multiplication, and its function is along with the development of digital signal processing algorithm, and also becoming becomes increasingly complex.Comprise and to finish the various operations of rounding off, add up/tire out and subtract operation result to revise multiplication.Usually the operation of rounding off comprises and being rounded up to and to rounding off for a short time.The implication that is rounded up to is that the result to operand rounds off to its bigger numerical value direction under certain computing situation; To round down then is opposite, and the direction less to its numerical value rounds off.
In 16 fixed-point calculation processes, subtract the result owing to adding up/tiring out and reached 32, in order to keep the precision of continuous operation result, the accumulation result of some DSP is 40, comprises some carry extension bits.And in order to keep the easy to use of register, what 40 number disperseed usually is preserved respectively by three 16 bit registers.The function of operating that rounds off is that logarithm value is similar to than general orientation or less direction to it, to satisfy the requirement of some algorithm.This approximate not strict unified range criterion.For the convenience of computing and fast, according to general method, the operation of rounding off just realizes by the operation that adds round-off number on a certain position to operation result, for example, 40 the 16th of subtracting operation result of adding up/tire out are added round-off number " 1 ", promptly exactly 40 bit arithmetic results are added decimal number " 32768 ".By such computing, round-off result rounds off than general orientation to its numerical value.
The multiplication that comprises the operation of rounding off adds up/and accumulation subtraction apparatus becomes the critical path of sequential usually, and is in the universal digital signal processor, all the more so.Finish the multiply accumulating that is rounded up to or take advantage of repeated subtraction need expend a large amount of time.Become one of main bottleneck of DSP design.
Summary of the invention
The objective of the invention is to, a kind of quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions is provided, it is that the 40 bit strip roundoff functions of seeking high speed performance add up/implementation structure of accumulation subtraction apparatus circuit, in the hope of make multiplication add up/time delay was little when accumulation subtraction apparatus was applied to nextport universal digital signal processor NextPort, thereby promote the performance of whole DSP simultaneously.The method of operating that wherein rounds off is exactly that to 40 subtrahends that add up/tire out the 16th adds round-off number " 1 ".
The quick accumulation subtraction apparatus circuit implementation structure of a kind of 40 bit strip roundoff functions of the present invention is characterized in that, comprising:
One addition compression module is used for high 25 and the operand that rounds off of two input operands are compressed into two 25 positional operands, for the adder computing;
One subtraction compression module is used for high 25 and the operand that rounds off of two input operands are compressed into two 25 positional operands, for the subtracter computing;
One add operation module is used for two 25 positional operands of addition compression module output are added up;
One subtraction module is used for tired the subtracting of two 25 positional operands that the subtraction compressor module is exported;
One 15 adders, low 15 that are used for 40 positional operands are carried out accumulating operation;
One 15 subtracters, low 15 that are used for 40 positional operands are tired out and subtract computing;
One 40 bit arithmetic results select multi-selection device, are used for sending as final result being selected by two 40 positional operands of add operation module and the output of subtraction module respectively.
Wherein the addition compression module is made of a full adder and 24 half adders; Lowest order and the operand that rounds off " 1 " that three input operands of full adder are respectively two cumulative numbers; The input operand of 24 half adders is respectively the 2nd to the 25th of two 25 cumulative numbers;
Addition compression module output port is two 25 figure place O1 and O2.Wherein, the output o1 of a full adder sends as the 2nd of O1, and the output o1 of 23 half adders sends as the 3rd to the 25th the output number of O1 successively, and finish the half adder output number o1 that the input operand highest order adds up and abandon, and the lowest order zero padding of O1; The output of a full adder is counted o2 and is sent as the lowest order of compression module output number O2; The output o2 of 24 half adders sends as the 2nd to the 25th the output number of O2 successively.
Wherein the subtraction compression module comprises that one one three input adder-subtracter and 24 single-order subtracters constitute.Two add operation numbers of three input adder-subtracter inputs are respectively the lowest order and the operand that rounds off " 1 " of one 25 outside input numbers, and a reducing number is 25 minuend lowest orders of outside input.The input operand of 24 single-order subtracters is respectively two 25 subtrahends and minuend the 2nd to the 25th;
Subtraction compression module output port is two 25 figure place O3 and O4; Wherein, the output o1 of an adder-subtracter of three inputs sends as the 2nd of O3, the output o1 of 23 single-order subtracters sends as the 3rd to the 25th the output number of O3 successively, and the subtracter output number o1 that finishes input operand highest order subtraction abandons, and the lowest order zero padding of O3; The output of an adder-subtracter of three inputs is counted o2 and is sent as the lowest order of subtraction compression module output number O4; The output o2 of 24 subtracters sends as the 2nd to the 25th the output number of O4 successively.
Wherein add operation module comprises:
One 25 bit strip carry digit adders, its carry digit is set at " 0 ";
One 25 bit strip carry digit adders, its carry digit is set at " 1 ";
One alternative multi-selection device by the carry digit control of adder, is selected the output of 25 adders of two different carry digits; To realize concurrent operation, pick up speed;
The input of add operation module connects the output of addition compression module; Output port connects 40 results and selects multi-selection device.
Wherein the subtraction module comprises:
One 25 bit strip borrow position subtracters, its borrow position is set at " 0 ";
One 25 bit strip borrow position subtracters, its borrow position is set at " 1 ";
One alternative multi-selection device by the borrow position control of subtracter, is selected the output of 25 adders of two different borrow positions; To realize concurrent operation, pick up speed;
The input of subtraction module connects the output of subtraction compression module; Output port connects 40 results and selects multi-selection device.
Wherein 15 adders are in order to finish adding and computing of low 15 figure places of two accumulate-operand; Carry digit of output port connects the add operation module, and 15 bit arithmetics output port as a result connect 40 multi-selection devices as a result.
Wherein 15 subtracters are in order to finish the difference operation of asking of low 15 figure places of two repeated subtraction numbers; Borrow position of output port connects the subtraction module, and 15 bit arithmetics output port as a result connect 40 multi-selection devices as a result.
Wherein 40 bit arithmetic results select multi-selection device, its four input ports connect the output port of 25 add operation module, 25 subtraction module, 15 adders and 15 subtracters respectively, and sent into by the outside one adds up and subtracts operational pattern and select signal to select adding up of 40 of outputs or the tired operation result that subtracts.
Description of drawings
For further specifying technical characterictic of the present invention, below in conjunction with embodiment and accompanying drawing the present invention is done a detailed description, wherein:
Fig. 1 is a kind of quick accumulation subtraction apparatus circuit implementation structure diagram of 40 bit strip roundoff functions.
Fig. 2 is the addition compressor reducer detailed icon in the quick accumulation subtraction apparatus circuit implementation structure.
Fig. 3 is the subtraction compressor reducer detailed icon in the quick accumulation subtraction apparatus circuit implementation structure.
Embodiment
See also Fig. 1, a kind of quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions, comprising:
One addition compression module ACM is used for high 25 and the operand that rounds off of two input operands are compressed into two 25 positional operands, for the adder computing.Its detailed icon sees also Fig. 2.
One subtraction compression module SCM is used for high 25 and the operand that rounds off of two input operands are compressed into two 25 positional operands, for the subtracter computing.Its detailed icon sees also Fig. 3.
One add operation modules A M is used for two 25 positional operands of addition compression module output are added up.
One subtraction module SM is used for tired the subtracting of two 25 positional operands that the subtraction compressor module is exported.
One 15 adder A15, low 15 that are used for 40 positional operands are carried out accumulating operation.
One 15 subtracter S15, low 15 that are used for 40 positional operands are tired out and subtract computing.
One 40 bit arithmetic results select multi-selection device MUX_01, are used for sending as final result being selected by two 40 positional operands of add operation module and the output of subtraction module respectively.
See also Fig. 2, addition compression module ACM, comprising:
Addition compression module ACM is made of a full adder FA1 and 24 half adder HA2～HA25.Three input operands of full adder FA1 are respectively two cumulative number B
39B
0And A
39A
0Lowest order B
0, A
0With the operand that rounds off " 1 ".The input operand of 24 half adder HA2～HA25 is respectively two 25 cumulative number B
39B
0And A
39A
0The 2nd to the 25th, i.e. B
39B
1And A
39A
1
Submodule: a full adder FA1, its function truth table is:
| Input operand a | Input operand b | Input operand c | O1 is counted in output function | O2 is counted in output function |
| ????0 | ????0 | ????0 | ????0 | ????0 |
| ????0 | ????0 | ????1 | ????0 | ????1 |
| ????0 | ????1 | ????0 | ????0 | ????1 |
| ????0 | ????1 | ????1 | ????1 | ????0 |
| ????1 | ????0 | ????0 | ????0 | ????1 |
| ????1 | ????0 | ????1 | ????1 | ????0 |
| ????1 | ????1 | ????0 | ????1 | ????0 |
| ????1 | ????1 | ????1 | ????1 | ????1 |
Submodule: a half adder HA2～HA25, its function truth table is:
| Input operand a | Input operand b | O1 is counted in output function | O2 is counted in output function |
| ????0 | ????0 | ????0 | ????0 |
| ????0 | ????1 | ????0 | ????1 |
| ????1 | ????0 | ????0 | ????1 |
| ????1 | ????1 | ????1 | ????0 |
Addition compression module ACM output port is two 25 figure place O1 and O2.Wherein, the output o1 of a full adder FA1 sends as the 2nd of O1, and the output o1 of 23 half adder HA3～HA25 sends as the 3rd to the 25th the output number of O1 successively, finishes input operand highest order B
39And A
39The half adder HA25 output number o1 that adds up abandons, and the lowest order zero padding of O1.The output of a full adder FA1 is counted o2 and is sent as the lowest order of compression module output number O2.The output o2 of 24 half adder HA2～HA25 sends as the 2nd to the 25th the output number of O2 successively.
See also Fig. 3, the subtraction compression module, comprising:
The subtraction compression module comprises that one one three input adder-subtracter FS1 and 24 single-order subtracter HS2～HS25 constitute.Two add operation numbers of three input adder-subtracter FS1 inputs are respectively the lowest order B of one 25 outside input numbers
0With the operand that rounds off " 1 ", reducing number is 25 the minuend lowest order and the A of outside input
0The input operand of 24 single-order subtracter HS2～HS25 is respectively two 25 subtrahends and minuend the 2nd to the 25th, i.e. B
39B
1And A
39A
1
Submodule: one three input adder-subtracter FS1, its logic true value table is:
| Input operand a | Input operand b | Input operand s | O1 is counted in output function | O2 is counted in output function |
| ????0 | ????0 | ????0 | ????0 | ????0 |
| ????0 | ????0 | ????1 | ????0 | ????1 |
| ????0 | ????1 | ????0 | ????1 | ????1 |
| ????0 | ????1 | ????1 | ????0 | ????0 |
| ????1 | ????0 | ????0 | ????1 | ????1 |
| ????1 | ????0 | ????1 | ????0 | ????0 |
| ????1 | ????1 | ????0 | ????1 | ????0 |
| ????1 | ????1 | ????1 | ????1 | ????1 |
Submodule: single-order subtracter HS2～HS25, its logic true value table is:
| Input operand a | Input operand s | O1 is counted in output function | O2 is counted in output function |
| ??0 | ??0 | ??0 | ??0 |
| ??0 | ??1 | ??0 | ??1 |
| ??1 | ??0 | ??1 | ??1 |
| ??1 | ??1 | ??0 | ??0 |
Subtraction compression module SCM output port is two 25 figure place O3 and O4.Wherein, the output o1 of an adder-subtracter FS1 of three inputs sends as the 2nd of O3, and the output o1 of 23 single-order subtracter HS3～HS25 sends as the 3rd to the 25th the output number of O3 successively, finishes input operand highest order B
39And A
39The subtracter HS25 output number o1 of subtraction abandons, and the lowest order zero padding of O3.The output of an adder-subtracter FS1 of three inputs is counted o2 and is sent as the lowest order of subtraction compression module output number O4.The output o2 of 24 subtracter HS2～HS25 sends as the 2nd to the 25th the output number of O4 successively.
See also Fig. 1 again, add operation modules A M, comprising:
One 25 bit strip carry digit adder A0_25, its carry digit is set at " 0 ".
One 25 bit strip carry digit adder A1_25, its carry digit is set at " 1 ".
One alternative multi-selection device MUX_A, the output of 25 the adder A0_25 or the A1_25 of two different carry digits is selected in the control of the carry digit of adder A15.To realize concurrent operation, pick up speed.
The input of add operation modules A M connects the output of addition compression module.Output port connects 40 results and selects multi-selection device MUX_01.
See also Fig. 1 again, subtraction module SM wherein, comprising:
One 25 bit strip borrow position subtracter S0_25, its borrow position is set at " 0 ".
One 25 bit strip borrow position subtracter S1_25, its borrow position is set at " 1 ".
One alternative multi-selection device MUX_S, the output of 25 the adder S0_25 and the S1_25 of two different borrow positions is selected in the control of the borrow position of subtracter S15.To realize concurrent operation, pick up speed.
The input of subtraction module SM connects the output of subtraction compression module.Output port connects 40 results and selects multi-selection device MUX_S.
See also Fig. 1,15 adder A15 wherein are in order to finish adding and computing of low 15 figure places of two accumulate-operand.Carry digit of output port connects add operation modules A M, and 15 bit arithmetics output port as a result connect 40 multi-selection devices as a result.
15 subtracter S15 are in order to finish the difference operation of asking of low 15 figure places of two repeated subtraction numbers.Borrow position of output port connects subtraction module SM, and 15 bit arithmetics output port as a result connect 40 multi-selection devices as a result.
40 bit arithmetic results select multi-selection device MUX_01, its four input ports connect the output port of 25 add operation modules A M, 25 subtraction module SM, 15 adder A15 and 15 subtracter S15 respectively, and sent into by the outside one adds up and subtracts operational pattern and select signal to select adding up of 40 of outputs or the tired operation result that subtracts.
Claims (8)
1, a kind of quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions is characterized in that, comprising:
One addition compression module is used for high 25 and the operand that rounds off of two input operands are compressed into two 25 positional operands, for the adder computing;
One subtraction compression module is used for high 25 and the operand that rounds off of two input operands are compressed into two 25 positional operands, for the subtracter computing;
One add operation module is used for two 25 positional operands of addition compression module output are added up;
One subtraction module is used for tired the subtracting of two 25 positional operands that the subtraction compressor module is exported;
One 15 adders, low 15 that are used for 40 positional operands are carried out accumulating operation;
One 15 subtracters, low 15 that are used for 40 positional operands are tired out and subtract computing;
One 40 bit arithmetic results select multi-selection device, are used for sending as final result being selected by two 40 positional operands of add operation module and the output of subtraction module respectively.
2, the quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions according to claim 1 is characterized in that, wherein the addition compression module is linked to each other side by side with 24 half adders by a full adder and constitutes; Lowest order and the operand that rounds off " 1 " that three input operands of full adder are respectively two cumulative numbers; The input operand of 24 half adders is respectively the 2nd to the 25th of two 25 cumulative numbers;
Addition compression module output port is two 25 figure place O1 and O2.Wherein, the output o1 of a full adder sends as the 2nd of O1, and the output o1 of 23 half adders sends as the 3rd to the 25th the output number of O1 successively, and finish the half adder output number o1 that the input operand highest order adds up and abandon, and the lowest order zero padding of O1; The output of a full adder is counted o2 and is sent as the lowest order of compression module output number O2; The output o2 of 24 half adders sends as the 2nd to the 25th the output number of O2 successively.
3, the quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions according to claim 1 is characterized in that, wherein the subtraction compression module comprises one one three input adder-subtracter and 24 single-order subtracters formation that links to each other side by side.Two add operation numbers of three input adder-subtracter inputs are respectively the lowest order and the operand that rounds off " 1 " of one 25 outside input numbers, and a reducing number is 25 minuend lowest orders of outside input.The input operand of 24 single-order subtracters is respectively two 25 subtrahends and minuend the 2nd to the 25th;
Subtraction compression module output port is two 25 figure place O3 and O4; Wherein, the output o1 of an adder-subtracter of three inputs sends as the 2nd of O3, the output o1 of 23 single-order subtracters sends as the 3rd to the 25th the output number of O3 successively, and the subtracter output number o1 that finishes input operand highest order subtraction abandons, and the lowest order zero padding of O3; The output of an adder-subtracter of three inputs is counted o2 and is sent as the lowest order of subtraction compression module output number O4; The output o2 of 24 subtracters sends as the 2nd to the 25th the output number of O4 successively.
4, the quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions according to claim 1 is characterized in that wherein add operation module comprises:
One 25 bit strip carry digit adders, its carry digit is set at " 0 ";
One 25 bit strip carry digit adders, its carry digit is set at " 1 ";
One alternative multi-selection device by the carry digit control of adder, is selected the output of 25 adders of two different carry digits; To realize concurrent operation, pick up speed;
The input of add operation module connects the output of addition compression module; Output port connects 40 results and selects multi-selection device.
5, the quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions according to claim 1 is characterized in that wherein the subtraction module comprises:
One 25 bit strip borrow position subtracters, its borrow position is set at " 0 ";
One 25 bit strip borrow position subtracters, its borrow position is set at " 1 ";
One alternative multi-selection device by the borrow position control of subtracter, is selected the output of 25 adders of two different borrow positions; To realize concurrent operation, pick up speed;
The input of subtraction module connects the output of subtraction compression module; Output port connects 40 results and selects multi-selection device.
6, the quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions according to claim 1 is characterized in that, wherein 15 adders are in order to finish adding and computing of low 15 figure places of two accumulate-operand; Carry digit of output port connects the add operation module, and 15 bit arithmetics output port as a result connect 40 multi-selection devices as a result.
7, the quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions according to claim 1 is characterized in that, wherein 15 subtracters are in order to finish the difference operation of asking of low 15 figure places of two repeated subtraction numbers; Borrow position of output port connects the subtraction module, and 15 bit arithmetics output port as a result connect 40 multi-selection devices as a result.
8, the quick accumulation subtraction apparatus circuit implementation structure of 40 bit strip roundoff functions according to claim 1, it is characterized in that, wherein 40 bit arithmetic results select multi-selection device, its four input ports connect the output port of 25 add operation module, 25 subtraction module, 15 adders and 15 subtracters respectively, and sent into by the outside one adds up and subtracts operational pattern and select signal to select adding up of 40 of outputs or the tired operation result that subtracts.
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| CN 03155314 CN1591824A (en) | 2003-08-26 | 2003-08-26 | Structure of realizing 40 bit fast accumulation subtraction apparatus circuit with roundoff function |
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| CN 03155314 CN1591824A (en) | 2003-08-26 | 2003-08-26 | Structure of realizing 40 bit fast accumulation subtraction apparatus circuit with roundoff function |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101051261B (en) * | 2006-04-07 | 2011-04-27 | 冲电气工业株式会社 | Rounding computing method and computing device therefor |
| WO2016192411A1 (en) * | 2015-05-29 | 2016-12-08 | Huawei Technologies Co., Ltd. | Increment/decrement apparatus and method |
| US9836278B2 (en) | 2015-05-29 | 2017-12-05 | Huawei Technologies Co., Ltd. | Floating point computation apparatus and method |
| CN111191780A (en) * | 2020-01-03 | 2020-05-22 | 珠海亿智电子科技有限公司 | Average value pooling accumulation circuit, device and method |
-
2003
- 2003-08-26 CN CN 03155314 patent/CN1591824A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101051261B (en) * | 2006-04-07 | 2011-04-27 | 冲电气工业株式会社 | Rounding computing method and computing device therefor |
| WO2016192411A1 (en) * | 2015-05-29 | 2016-12-08 | Huawei Technologies Co., Ltd. | Increment/decrement apparatus and method |
| US9785405B2 (en) | 2015-05-29 | 2017-10-10 | Huawei Technologies Co., Ltd. | Increment/decrement apparatus and method |
| US9836278B2 (en) | 2015-05-29 | 2017-12-05 | Huawei Technologies Co., Ltd. | Floating point computation apparatus and method |
| CN111191780A (en) * | 2020-01-03 | 2020-05-22 | 珠海亿智电子科技有限公司 | Average value pooling accumulation circuit, device and method |
| CN111191780B (en) * | 2020-01-03 | 2024-03-19 | 珠海亿智电子科技有限公司 | Averaging pooling accumulation circuit, device and method |
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