CN1267120A - Boost up circuit method and electronic apparatus - Google Patents
Boost up circuit method and electronic apparatus Download PDFInfo
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- CN1267120A CN1267120A CN00103768A CN00103768A CN1267120A CN 1267120 A CN1267120 A CN 1267120A CN 00103768 A CN00103768 A CN 00103768A CN 00103768 A CN00103768 A CN 00103768A CN 1267120 A CN1267120 A CN 1267120A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/06—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode
- H02M7/10—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode arranged for operation in series, e.g. for multiplication of voltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Dc-Dc Converters (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Direct Current Feeding And Distribution (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
First, a terminal C1L of an auxiliary capacitor C1 is connected to a ground line and a terminal C1H of the auxiliary capacitor C1 is connected to the supply line of an input voltage Vin; secondly, a terminal C2L of an auxiliary capacitor C2 is connected to the ground line, the terminal C1L of the auxiliary capacitor C1 is switched to the supply line of the input voltage Vin, and the terminal C1H of the auxiliary capacitor C1 is switched and connected to a terminal C2H of the auxiliary capacitor C2; and thirdly, the terminal C2L of the auxiliary capacitor C2 is switched to the terminal C1H of the auxiliary capacitor C1, and the terminal C2H of the auxiliary capacitor C2 is switched and connected to the output line.
Description
The present invention relates to cut down the boost booster circuit, step-up method of number of needed charge storage element and the electronic instrument that the output of this booster circuit is used as power supply.
For example, in liquid crystal indicator,, when driving liquid crystal cell, need high-tension power supply in order to obtain good display characteristic.Therefore, the power circuit that uses of liquid crystal indicator is exactly to utilize booster circuit that the structure of the drive circuit that drives liquid crystal cell etc. is supplied with in the input voltage back of boosting.
Below, be that 4 times situation is the structure of the booster circuit that has earlier of example explanation with the multiple that boosts.Figure 13 is the circuit diagram of structure of the booster circuit 138 of this situation of expression, is made of transistor Q1～Q8, auxiliary capacitor C1, C2, C2p and output capacitor Cout.
Figure 14 is the timing chart that the control signal of this booster circuit 138 is supplied with in expression.Control signal a shown in this figure is the signal that the pulse duration with control signal b narrows down, and supplies with the signal of booster circuit 138 as wherein n channel transistor Q2, Q4, Q6, Q8.In addition, control signal b supplies with the signal of booster circuit 138 as wherein p channel transistor Q1, Q3, Q5, Q7.
When such control signal a, b supply with booster circuit 138, at first, by among Figure 14 1. shown in during, promptly have only control signal a be high level during, transistor Q2, Q4, Q6, Q8 conducting, and other transistors all end.Therefore, for auxiliary capacitor C1, as among Figure 15 1. shown in like that, terminal C1H is connected with the supply line of input voltage vin, the while, terminal C1L was connected with earth connection, so, charge with input voltage vin.In addition, for auxiliary capacitor C2, by thereafter 2. shown in during, be connected in parallel with auxiliary capacitor C2p and charge with 2Vin charging.After this, transistor Q1～Q8 all temporarily ends.
Secondly, by among Figure 14 2. shown in during, promptly control signal a, b all become low level during, transistor Q1, Q3, Q5, Q7 conducting, and other transistors all end.Therefore, as among Figure 15 2. shown in like that, the terminal C1L of auxiliary capacitor C1 switches to the supply line of input voltage vin and is connected, terminal C1H separates with the supply line of input voltage vin simultaneously, so the current potential of terminal C1H becomes the 2Vin of hot side that input voltage vin is offset to the output voltage V in of auxiliary capacitor C1.On the other hand, for auxiliary capacitor Cp, terminal CpH is connected with terminal C1H, and the result charges with the potential difference of 2Vin, so, above-mentioned 1. during, the current potential of terminal CpH becomes 2Vin.In addition, above-mentioned 1. during, because the terminal C2L of the auxiliary capacitor C2 that charges with 2Vin is connected with terminal C1H, so, the current potential of the terminal C2H of this auxiliary capacitor C2 becomes the 4Vin of hot side that the 2Vin as the current potential of terminal C1H (CpH, C2L) is offset to the output voltage 2Vin of auxiliary capacitor C2, after, just carry out smoothing processing by output capacitor Cout.Like this, by carry out 1. repeatedly, 2. during processing, input voltage vin is just boosted after 4 times and is exported.
In addition, when the multiple that will boost adopts high magnification, for example, when the multiple that will boost adopts 16 times, as shown in Figure 16, just use auxiliary capacitor C1, C2, C2p, C3, C3p, C4,7 capacitors such as C4p, at first, as among Figure 16 1. shown in like that, auxiliary capacitor C1 charges with input voltage vin, simultaneously, auxiliary capacitor C2 Figure 16 2. in, be connected in parallel with auxiliary capacitor C2p and charge with 2Vin charging, same, auxiliary capacitor C3 Figure 16 2. in, be connected in parallel with auxiliary capacitor C3p and charge with 4Vin charging, equally, auxiliary capacitor C4 Figure 16 2. in, be connected in parallel with auxiliary capacitor C2p and charge with 8Vin charging.
Secondly, as Figure 16 2. shown in like that, the 1st, auxiliary capacitor C2p utilizes the 2Vin of hot side that input voltage vin is offset to the output voltage V in of auxiliary capacitor C1 to charge, the 2nd, the 4Vin of hot side that auxiliary capacitor C3p utilizes the current potential with the 2Vin of auxiliary capacitor C1 to be offset to the output voltage 2Vin of auxiliary capacitor C2 charges, the 3rd, the 8Vin of hot side that auxiliary capacitor C4p utilizes the current potential with the 4Vin of auxiliary capacitor C2 to be offset to the output voltage 4Vin of auxiliary capacitor C3 charges, the 4th, be offset to the hot side of the output voltage 8Vin of auxiliary capacitor C4 by current potential, obtain boost 16 times 16Vin of input voltage vin with the 8Vin of auxiliary capacitor C3.
But, in the booster circuit that formerly has, except smmothing capacitor Cout, 4 times of 3 auxiliary capacitors of needs that boost, 16 times of 7 auxiliary capacitors of needs that boost, generally speaking, 2
nThe needed auxiliary capacitor that boosts doubly is exactly that (2n-1) is individual.Here, the power circuit that will comprise booster circuit carries out being difficult to the condenser network that capacitor is such and forming on semiconductor substrate when integrated, in addition, even can form, will cause hugeization of circuit size, so the number of the needed capacitor that boosts is cut down in hope sometimes as far as possible.
And in the booster circuit that formerly has, maximum problem is difficult to control arbitrarily the multiple that boosts exactly.Therefore, for the voltage after will boosting at desirable value stabilization, must increase voltage stabilizing circuits such as switching regulator in addition in the back level of booster circuit, thereby this part will make the scale of power circuit complicated.
The present invention is exactly in view of the above problems and motion that purpose aims to provide can cut down the such charge storage element of needed capacitor that boosts, simplified structure can more freely be controlled booster circuit, the step-up method of the multiple that boosts and the electronic instrument that the output of this booster circuit is used as power supply simultaneously.
In order to achieve the above object, booster circuit of the present invention is characterised in that: have the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment are connected simultaneously the 1st linkage unit that the terminal with the another side of above-mentioned the 1st charge storage element is connected with the 2nd line with current potential different with above-mentioned the 1st line, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd linkage unit that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of above-mentioned the 2nd charge storage element is switched to the terminal that is connected with the terminal of the another side of above-mentioned the 1st charge storage element simultaneously the another side of above-mentioned the 2nd charge storage element switch to the 3rd linkage unit that is connected with output line.
According to the present invention, at first, the 1st charge storage element is connected the 1st and is connected with the 2nd line, so during as reference potential, the terminal of the another side of the 1st charge storage element just becomes and the 2nd line equipotential with the 1st line.Secondly, the terminal on one side of the 1st charge storage element switches to when being connected with the 2nd line from the 1st line, the current potential of the terminal of the another side of the 1st charge storage element just become with the current potential of the 2nd line with the current potential side that applies to the 1st line in the opposite direction with the current potential of the output voltage biasing of the 1st charge storage element, so, become 2 times of current potentials of the 2nd line, Here it is charges by the 2nd charge storage element.And, the terminal on one side of the 2nd charge storage element switches to the terminal that is connected the another side of the 2nd charge storage element simultaneously with the terminal of the another side of the 1st charge storage element and switches to when being connected with output line from the terminal of the another side of the 1st charge storage element from the 1st line, the current potential of output line just become with have the 2nd line 2 times of current potentials the 1st charge storage element another side terminal current potential with the side that applies to the 1st line in the opposite direction with the current potential of the output voltage of the 2nd charge storage element biasing, so, become 4 times of current potentials of the 2nd line.Therefore, 2 of the 4 times of needed charge storage elements that boost of the potential difference between the 1st and the 2nd line are just much of that, so, can simplified structure.That is, though charge storage elements such as electric capacity also be difficult in addition form carrying out needing big area when integrated,, according to the present invention owing to can cut down needed charge storage element, so, can contribution be arranged to simplified structure.No matter when the current potential of the 1st line is higher than the 2nd line or the current potential of the 1st line is when being lower than the 2nd line, such structure can be distinguished correspondence.In addition, reference potential can be that the current potential of the 1st line also can be the current potential of the 2nd line.
Here, in booster circuit of the present invention, preferably have terminal with one side of above-mentioned the 2nd charge storage element be connected with above-mentioned the 1st line simultaneously the 4th linkage unit that the terminal with another side is connected with above-mentioned the 2nd line and control exclusively utilize above-mentioned the 2nd linkage unit above-mentioned the 2nd charge storage element be connected the control unit that is connected with above-mentioned the 2nd charge storage element that utilizes above-mentioned the 4th linkage unit.
According to this structure, suppose control unit will utilize be controlled to be during the connection of the 2nd charge storage element of the 2nd linkage unit complete during and be controlled to be at 0 o'clock during will utilizing the connection of the 4th linkage unit, as as mentioned above, the current potential of output line just becomes 4 times of current potentials of the 2nd line.On the other hand, control unit will utilize be controlled to be during the connection of the 2nd charge storage element of the 2nd linkage unit 0 and will utilize be controlled to be during the connection of the 2nd charge storage element of the 4th linkage unit complete during the time, then the output voltage of the 2nd charge storage element just is not to become the 1st line and the 2nd line 2 times of potential difference but equate, so the current potential of output line becomes 3 times of current potentials of the 2nd line.Therefore, when the ratio during the control connection is come the current potential of level and smooth output line, just the multiple no polar region between 4 times～3 times of boosting can be changed.
At this moment, based on the absolute value of the current potential of the current potential of above-mentioned the 2nd line or above-mentioned output line during less than the value of appointment, best above-mentioned control unit will utilize that to be controlled to be Billy during the connection of above-mentioned the 2nd charge storage element of above-mentioned the 2nd linkage unit long during with the connection of above-mentioned the 2nd charge storage element of above-mentioned the 4th linkage unit.The current potential that like this, just can make output line is certain between 4 times～3 times of the current potential of the 2nd line.
In addition, in booster circuit of the present invention, preferably have under the terminal on one side of above-mentioned the 1st charge storage element and state that above-mentioned the 2nd line is connected being connected and the control unit that is connected that utilizes above-mentioned the 5th linkage unit of above-mentioned the 2nd charge storage element that the 5th linkage unit that the terminal with the another side of above-mentioned the 1st charge storage element is connected with above-mentioned output line and control exclusively utilize the above-mentioned the 2nd or the 4th linkage unit.
According to this structure, suppose control unit will utilize be controlled to be during the connection of the 2nd charge storage element of the 2nd or the 4th linkage unit complete during and be controlled to be at 0 o'clock during will utilizing the connection of the 5th linkage unit, then the current potential of output line just becomes 4 times or 3 times of current potentials of the 2nd line as described above.On the other hand, control unit will utilize be controlled to be during the connection of the 2nd charge storage element of the 2nd or the 4th linkage unit 0 and will utilize be controlled to be during the connection of the 5th linkage unit complete during the time, output line just becomes the identical current potential of another terminal with the 1st charge storage element of 2 times of current potentials with the 2nd line.Therefore, during the current potential of the ratio during the control connection, level and smooth output line, the multiple no polar region between 4 times～2 times or 3 times～2 times of boosting is changed.
At this moment, based on the absolute value of the current potential of the current potential of above-mentioned the 2nd line or above-mentioned output line during less than the value of appointment, above-mentioned control unit will be controlled to be than long during the connection of above-mentioned the 5th linkage unit during preferably will utilizing the connection of above-mentioned the 2nd charge storage element of the above-mentioned the 2nd or the 4th linkage unit.The current potential that like this, just can make output line is certain between 4 times～2 times or 3 times～2 times of the current potential of the 2nd line.
In addition, in booster circuit of the present invention, preferably have the 6th linkage unit that above-mentioned the 2nd line is connected with above-mentioned output line and the connection and the control unit that is connected that utilizes above-mentioned the 6th linkage unit that are connected or utilize above-mentioned the 5th linkage unit of controlling above-mentioned the 2nd charge storage element that utilizes the above-mentioned the 2nd or the 4th linkage unit exclusively.
According to this structure, suppose control unit will utilize during the connection of the 2nd charge storage element of the 2nd or the 4th linkage unit or utilize the connection of the 5th linkage unit during be controlled to be complete during and be controlled to be at 0 o'clock during will utilizing the connection of the 6th linkage unit, then the current potential of output line just becomes 4 times, 3 times or 2 times of current potentials of the 2nd line as described above.On the other hand, with utilize during the connection of the 2nd charge storage element of the 2nd or the 4th linkage unit or utilize the connection of the 5th linkage unit during be controlled to be 0 and will utilize be controlled to be during the connection of the 6th linkage unit complete during the time, then output line just becomes the current potential identical with the 2nd line.Therefore, during the current potential of the ratio during the control connection, level and smooth output line, the multiple no polar region between 4 times～1 times, 3 times～1 times or 2 times～1 times of boosting is changed.
At this moment, based on the absolute value of the current potential of the current potential of above-mentioned the 2nd line or above-mentioned output line during less than the value of appointment, above-mentioned control unit preferably will utilize during the connection of above-mentioned the 2nd charge storage element of the above-mentioned the 2nd or the 4th linkage unit or utilize the connection of above-mentioned the 5th linkage unit during be controlled to be than long during the connection of above-mentioned the 6th linkage unit.The current potential that like this, just can make output line is certain between 4 times～1 times, 3 times～1 times or 2 times～1 times of the current potential of the 2nd line.
In addition; In order to achieve the above object, booster circuit of the present invention is characterised in that: have with the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment connect simultaneously with the terminal of the another side of above-mentioned the 1st charge storage element with have and be connected the 1st linkage unit that the 2nd line of the different current potential of the 1st line is connected, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd linkage unit that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of m (m is for satisfying the integer of 3≤m≤n) charge storage element is connected simultaneously terminal with one side of above-mentioned (m-1) charge storage element to be switched to be connected with the terminal of the another side of above-mentioned (m-2) charge storage element and the terminal of the another side of above-mentioned (m-1) accumulator element to be switched to the 3rd～the n linkage unit that is connected with the terminal of the another side of above-mentioned m charge storage element and terminal with one side of n charge storage element and switches to the terminal that is connected with the terminal of the another side of the charge storage element of (n-1) simultaneously the another side of above-mentioned n charge storage element and switch to (n+1) linkage unit that is connected with output line with above-mentioned the 1st line.
Below, for example get n and describe for " 4 ", at first, the 1st charge storage element is connected between the 1st and the 2nd line, so the terminal of the another side of the 1st charge storage element just becomes the current potential that equates with the 2nd line.Secondly, when the terminal on one side of the 1st charge storage element switches to and is connected with the 2nd line, the another side of the 1st charge storage element current potential just become 2 times of current potentials of the 2nd line, Here it is charges by the 2nd charge storage element.In addition, when the terminal on one side of the 2nd charge storage element switched to and is connected with the terminal of the another side of the 1st charge storage element, the current potential of the terminal of the another side of the 2nd charge storage element just became 4 times of current potentials of the 2nd line, and Here it is charges by the 3rd charge storage element.Then, when the terminal on one side of the 3rd charge storage element switched to and is connected with the terminal of the another side of the 2nd charge storage element, the current potential of the terminal of the another side of the 3rd charge storage element just became 8 times of current potentials of the 2nd line, and Here it is charges by the 4th charge storage element.And when the terminal on one side of the 4th charge storage element switched to and is connected with the terminal of the another side of the 3rd charge storage element, the current potential of the terminal of the another side of the 4th charge storage element just became 16 times of current potentials of the 2nd line.Therefore, when n is " 4 ", make the potential difference between the 1st and the 2nd line boost 2
4=16 times of needed charge storage elements are just much of that with 4, so, can simplified structure.That is, when considering that usually n is a integer more than 3, make the potential difference between the 1st and the 2nd line boost 2
nDoubly needed charge storage element uses n individual just much of that, so when particularly the n value was big, it was very desirable simplified structure.
In order to achieve the above object, step-up method of the present invention is characterised in that: comprise the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment are connected simultaneously the 1st process that the terminal with the another side of above-mentioned the 1st charge storage element is connected with the 2nd line with current potential different with above-mentioned the 1st line, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd process that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of above-mentioned the 2nd charge storage element is switched to the terminal that is connected with the terminal of the another side of above-mentioned the 1st charge storage element simultaneously the another side of above-mentioned the 2nd charge storage element switch to the 3rd process that is connected with output line.
Equally; In order to achieve the above object, step-up method of the present invention is characterised in that: comprise with have at least n the 1st charge storage element in (n is the integer 3 or more) charge storage element one side terminal and the current potential with appointment the connection of the 1st line simultaneously with the terminal of the another side of above-mentioned the 1st charge storage element with have and be connected the 1st process that the 2nd line of the different current potential of the 1st line is connected, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd process that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of m (m is for satisfying the integer of 3≤m≤n) charge storage element is connected simultaneously terminal with one side of above-mentioned (m-1) charge storage element to be switched to be connected with the terminal of the another side of above-mentioned (m-2) charge storage element and the terminal of the another side of above-mentioned (m-1) accumulator element to be switched to the 3rd～the n process that is connected with the terminal of the another side of above-mentioned m charge storage element and terminal with one side of n charge storage element and switches to the terminal that is connected with the terminal of the another side of the charge storage element of (n-1) simultaneously the another side of above-mentioned n charge storage element and switch to (n+1) process that is connected with output line with above-mentioned the 1st line.
In addition, in order to achieve the above object, electronic instrument of the present invention is characterised in that: have the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment are connected simultaneously the 1st linkage unit that the terminal with the another side of above-mentioned the 1st charge storage element is connected with the 2nd line with current potential different with above-mentioned the 1st line, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd linkage unit that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of above-mentioned the 2nd charge storage element is switched to the terminal that is connected with the terminal of the another side of above-mentioned the 1st charge storage element simultaneously the another side of above-mentioned the 2nd charge storage element switch to the 3rd linkage unit that is connected with output line, and will use as power supply based on the current potential of above-mentioned output line.
Equally, in order to achieve the above object, electronic instrument of the present invention is characterised in that: comprise the booster circuit that has n (n is the integer more than 3) charge storage element at least, this booster circuit has the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment is connected simultaneously the 1st linkage unit that the terminal with the another side of above-mentioned the 1st charge storage element is connected with the 2nd line with current potential different with above-mentioned the 1st line, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd linkage unit that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of m (m is for satisfying the integer of 3≤m≤n) charge storage element is connected simultaneously terminal with one side of above-mentioned (m-1) charge storage element switches to be connected with the terminal of the another side of above-mentioned (m-2) charge storage element and the terminal of the another side of above-mentioned (m-1) accumulator element to be switched to the 3rd～the n linkage unit that is connected with the terminal of the another side of above-mentioned m charge storage element and terminal and switch to the terminal that is connected with the terminal of the another side of the charge storage element of (n-1) simultaneously the another side of above-mentioned n charge storage element and switch to (n+1) linkage unit that is connected with output line with above-mentioned the 1st line, will use as power supply based on the current potential of above-mentioned output line with one side of n charge storage element.
Fig. 1 is the block diagram of structure of the power circuit of the expression booster circuit of using the embodiment of the invention 1.
Fig. 2 is the circuit diagram of structure of the booster circuit of the expression embodiment of the invention 1.
Fig. 3 is illustrated in the booster circuit of the present invention 4 times of control signal sequential charts when boosting.
Fig. 4 is the action specification figures of 4 times of booster circuit of the present invention when boosting.
Fig. 5 is the timing chart that is illustrated in the booster circuit of the present invention 3 times of control signals when boosting.
3 of booster circuit of the present invention times of action specification figure when boosting during Fig. 6.
Fig. 7 is the sequential chart that is illustrated in the booster circuit of the present invention 2 times of control signals when boosting.
2 of printed circuit of the present invention times of action specification figure when boosting during Fig. 8.
Fig. 9 is the sequential chart of the control signal when being illustrated in medium times of booster circuit of the present invention and boosting.
Figure 10 is the circuit diagram of structure of the booster circuit of the expression embodiment of the invention 2.
Figure 11 is the action specification figures of 16 times of booster circuit of the present invention when boosting.
Figure 12 is the block diagram of the electrical structure of expression liquid crystal indicator that the booster circuit of embodiment is used as power circuit.
Figure 13 is a circuit diagram of representing the structure of the booster circuit that has earlier.
Figure 14 is the sequential chart of 4 times of control signals when boosting in the booster circuit of representing formerly to have.
Figure 15 is 4 times of action specification figure when boosting in the booster circuit that formerly has.
Figure 16 is the action specification figures of 16 times of the booster circuit that has earlier when boosting.
Below, embodiments of the invention are described.
(embodiment 1)
At first, embodiment 1 as basic structure of the present invention is described.Fig. 1 is the block diagram of structure of the power circuit of the expression booster circuit of using present embodiment.As shown in the figure, power circuit 100 is made of voltage detecting circuit 110, boost control circuit 120 and booster circuit 130.Wherein, voltage detecting circuit 110 is used for the output voltage V out of test example such as booster circuit 130 and this testing result is supplied with boost control circuit 120.Boost control circuit 120 generates control signal a, b, c1, c2, the d of the multiple that boosts that is used to control booster circuit 130 according to the output voltage V out that is detected by voltage detecting circuit 110.
Below, the detailed structure of booster circuit 130 is described with reference to Fig. 2.This booster circuit 130 boosts input voltage vin from 1 times to 4 times according to the control signal a, the b that are generated by boost control circuit 120, c1, c2, d and exports as output voltage V out, by constituting as transistor Q2～Q8, the auxiliary capacitor C1 of switch element and C2 and output capacitor Cout.
In detail, the terminal C1L on one side that is exactly auxiliary capacitor C1 is by being connected as the n channel transistor Q4 of signal control signal a, simultaneously by control signal b is connected with the supply line of input voltage vin as the p channel transistor Q3 of signal with the earth connection with reference potential.
On the other hand, the terminal C1H of the another side of auxiliary capacitor C1 connects in the following manner, promptly, terminal C1H the 1st is by being connected as the n channel transistor Q2 of signal control signal a with the supply line of input voltage vin, the 2nd by being connected as the p channel transistor Q7 of signal control signal d with the terminal C2L on one side of auxiliary capacitor C2, in addition by control signal C2 is connected with earth connection as the n channel transistor Q8 of signal, the 3rd by being connected as the n channel transistor Q6 of signal control signal C1 with the terminal C2H of the another side of auxiliary capacitor C2, in addition by control signal d is connected with the output line of output voltage V out as the p channel transistor Q5 of signal.
And for smooth output voltage Vout, output capacitor Cout is connected in parallel between this output line and the earth connection.
(action of embodiment 1)
Below, the action of the power circuit 100 of said structure is described.Boost control circuit 120 was the multiple that boosts that does not have control booster circuit 130 in polar region according to output voltage V out originally, but for convenience of explanation, each action when the multiple that will boost being taken as 4 times, 3 times, 2 times, 1 times respectively here describes, the electrodeless control of the multiple that boosts is described then.
＜4 times boost 〉
Action when here, the multiple that boosts of explanation booster circuit 130 is 4 times earlier.At this moment, shown in the sequential chart of Fig. 3 like that, boost control circuit 120 generates control signal a, b, c1, c2, d respectively.As shown in the figure, control signal a is the signal that the pulse duration with control signal b narrows down.In addition, control signal c1, c2 are respectively the signals that control signal b is carried out again 1/2 frequency division after anti-phase.In addition, control signal d is the signal that control signal c1 or c2 are postponed half period after anti-phase again.
When such control signal is supplied with booster circuit 130, at first, by among Fig. 3 1. shown in during, promptly control signal a, b, d be high level and control signal c1, c2 be low level during, transistor Q2, Q4 conducting, and other transistors all end.Therefore, for auxiliary capacitor C1, as by among Fig. 4 1. shown in like that, terminal C1H is connected with the supply line of input voltage vin, simultaneously, terminal C1L is connected with earth connection, so, charge with input voltage vin.After this, transistor Q2～Q8 temporarily all ends.
Secondly, by among Fig. 3 2. shown in during, promptly control signal c1, c2, d be high level and control signal a, b be low level during, transistor Q3, Q6, Q8 conducting, and other transistors all end.Therefore, as by among Fig. 4 2. shown in like that, the terminal C1L of auxiliary capacitor C1 is connected with the supply line of input voltage vin, terminal C1H separates with the supply line of input voltage vin simultaneously, so the current potential of terminal C1H just becomes the 2Vin of hot side that input voltage vin is offset to the output voltage V in of auxiliary capacitor C1.On the other hand, for auxiliary capacitor C2, terminal C2H is connected with terminal C1H, and terminal C2L is connected with earth connection simultaneously, so, just charge with 2Vin as the potential difference between two-terminal.After this, transistor Q2～Q8 temporarily all ends.
And, by among Fig. 3 3. shown in during, promptly control signal a, b, c1, c2, d all become low level during, transistor Q3, Q5, Q7 conducting, and other transistors all end.Therefore, if among Fig. 4 3. shown in like that, under the terminal C1L of auxiliary capacitor C1 and state that the supply line of input voltage vin is connected, terminal C1H is connected with terminal C2L, simultaneously, terminal C2H is connected with the output line of output voltage V out.Therefore, the current potential of terminal C2H is the 4Vin of the hot side of the current potential of terminal C1H (C2L) the output voltage 2Vin that is offset to auxiliary capacitor C2 with regard to becoming 2Vin, after, just carry out smoothing processing by output capacitor Cout.When connecting loads on the output line, just carry out the discharge of output capacitor Cout, so, output voltage V out at transistor Q5 from during conducting, beginning little by little to reduce from 4Vin.
Like this, by repeatedly through 1., 2., 3. during, input voltage vin is just being boosted after 4 times and is being exported.
＜3 times boost 〉
Below, the action the when multiple that boosts that booster circuit 130 is described is 3 times.At this moment, boost control circuit 120 generates respectively by control signal a, b, c1, c2, the d shown in the sequential chart of Fig. 5.Here, control signal a, b are signals identical when 4 times boost as shown in the figure.In addition, control signal c1, c2 are the signals identical with control signal a, and same, control signal d is the signal identical with control signal b.
When such control signal is supplied with booster circuit 130, at first, by among Fig. 5 1. shown in during, that is, and control signal a, b, c1, c2, d all be high level during, transistor Q2, Q4, Q6, Q8 conducting, and other transistors all end.Therefore, auxiliary capacitor C1, C2 as Fig. 6 1. shown in like that, the supply line of terminal C1H and terminal C2H and input voltage vin is connected in parallel, terminal C1L and terminal C2L and earth connection are connected in parallel, so auxiliary capacitor C1, C2 charge with input voltage vin respectively.After this, transistor Q2～Q8 temporarily all ends.
Secondly, arrive among Fig. 5 2. shown in during the time, when promptly arriving control signal a, b, c1, c2, d and all becoming low level, transistor Q3, Q5, Q7 conducting, and other transistors all end.Therefore, as Fig. 6 2. shown in like that, the terminal C1L of auxiliary capacitor C1 is connected with the supply line of input voltage vin, so the current potential of terminal C1H just becomes the 2Vin of hot side that input voltage vin is offset to the output voltage V in of auxiliary capacitor C1.In addition, under this state, terminal C1H is connected with the terminal C2L of auxiliary capacitor C2, simultaneously, terminal C2H is connected with the output line of output voltage V out, so the current potential of terminal C2H is the 3Vin of the hot side of the current potential of terminal C1H (C2L) the output voltage V in that is offset to auxiliary capacitor C2 with regard to becoming 2Vin.When connecting loads on the output line, just carry out the discharge of output capacitor Cout, so, output voltage V out at transistor Q5 from during conducting, beginning little by little to reduce from 3Vin.
Like this, by repeatedly through 1., 2. during, input voltage vin is just being boosted after 3 times and is being exported.
＜2 times boost 〉
Below, the action the when multiple that boosts that booster circuit 130 is described is 2 times.At this moment, boost control circuit 120 generates respectively for example by control signal a, b, c1, c2, the d shown in the sequential chart of Fig. 7.Here, control signal a, b are signals identical when 4 times and 3 times boost as shown in the figure.In addition, control signal c1 is the signal after anti-phase with control signal b, the always low level signal of control signal c2.On the other hand, control signal d is the signal identical with control signal b.
When such control signal is supplied with booster circuit 130, at first, by among Fig. 7 1. shown in during, that is, and control signal a, b, c1, the d beyond the control signal c2 be high level during, with 4 times boost 1. during the same, transistor Q2, Q4 conducting, other transistors all end, so, as Fig. 8 1. shown in like that, auxiliary capacitor C1 just charges with voltage Vin.After this, transistor Q2～Q8 temporarily all ends.
Secondly, arrive Fig. 7 2. shown in during the time, promptly arrive control signal c1 and be high level and control signal a, b, c2, d be low level during the time, transistor Q3, Q5, Q6, Q7 conducting, and other transistors all end.Therefore, as Fig. 8 2. shown in like that, the terminal C1L of auxiliary capacitor C1 is connected with the supply line of input voltage vin, simultaneously, terminal C1H is connected with the output line of output voltage V out, so output voltage V out just becomes the 2Vin of hot side that input voltage vin is offset to the output voltage V in of auxiliary capacitor C1.
During this period, terminal C2L and terminal C2H short circuit be not so auxiliary capacitor C2 charges.In addition, when connecting loads on the output line, just carry out the discharge of output capacitor Cout, so, output voltage V out at transistor Q5 from during conducting, beginning little by little to reduce from Vin.
Like this, by repeatedly through 1., 2. during, input voltage vin is just being boosted after 2 times and is being exported.
＜1 times boosts 〉
Below, the action the when multiple that boosts that booster circuit 130 is described is 1 times.At this moment, boost control circuit 120 generates respectively by control signal a, b, c1, c2, the d shown in the sequential chart of Fig. 9.Here, control signal a as shown in the figure, and is the same when 4 times, 3 times, 2 times boost.In addition, the control signal b signal of high level always.On the other hand, control signal c1 is the signal identical with control signal a.In addition, the control signal c2 signal of high level always.And control signal d is the signal after anti-phase with control signal a or c1.
When such control signal is supplied with booster circuit 130, by among Fig. 5 1. shown in during, that is, and control signal a, b be high level and control signal d be low level during, transistor Q2, Q4, Q5, Q6, Q7 conducting, and other transistors all end.Therefore, the supply line of input voltage vin is connected with output line, so input voltage vin directly just becomes output voltage V out.During this period, terminal C2L and terminal C2H short circuit be not so auxiliary capacitor C2 charges.In addition, when connecting loads on the output line, just carry out the discharge of output capacitor Cout, so, output voltage V out at transistor Q5 from during conducting, beginning little by little to reduce from Vin.
Like this, during 1., input voltage vin is just directly exported as output voltage V out.
＜4 times～1 times electrodeless boosting 〉
Satisfy like this in the booster circuit of present embodiment, at first can carry out 4 times, 3 times, 2 times, 1 times boost, still,, be not limited to this, in fact can not have the polar region from 4 times to 1 times and boost for the multiple that boosts.That is, boost control circuit 120 can timesharing be supplied with the control signal of the different multiples that boosts, and the multiple that will boost is set at the value between this different multiple by controlling the ratio during this supply.
For example, if during identical, alternately supply with 4 times of control signal and 3 times of control signals when boosting when boosting respectively, then just become 3.5 times of input voltage vin, in fact just the multiple that boosts can be decided to be 3.5 times by the output voltage V out after the output capacitor Cout smoothing processing.In addition, for example, if alternately during 25%, supply with respectively 4 times when boosting control signal and during 75%, supply with 3 times of control signals when boosting, then in fact just the multiple that boosts can be decided to be 3.25 times.No matter which kind of situation, control signal a, b are the same, so it is just passable only to change control signal c1 (c2) and control signal d.
Here, in the present embodiment, as mentioned above, be that the connection of timesharing control auxiliary capacitor C1, C2 obtains 4Vin, 3Vin, each voltage of 2Vin, Vin, so the ratio during the supply of control control signal is exactly that timesharing is controlled exclusively and obtained the needed type of attachment of each voltage.
In addition, when the multiple that will boost is set between 4 times～3 times, for employed control signal, the combination of the control signal the when control signal when 4 times boost and 3 times boost, the control signal the when control signal in the time of also 4 times can being boosted and 2 times or 1 times boost makes up.If with the above-mentioned 3.5 times multiple that boosts is that example describes, then can be respectively alternately during 75%, supply with 4 times when boosting control signal and during 25%, supply with 2 times of control signals when boosting, in addition, with can be respectively alternately during 83.3%, supply with 4 times when boosting control signal and during 16.7%, supply with 1 times of control signal when boosting.
Equally, when the multiple that will boost is set between 3 times～2 times, for employed control signal, the combination of the control signal the when control signal when 3 times boost and 2 times boost, control signal when the control signal in the time of also 4 times can being boosted and 2 times or 1 times boost makes up, control signal when the control signal in the time of also 3 times can being boosted in addition, and 1 times boost makes up.Equally, when the multiple that will boost is set between 2 times～1 times, lose employed control signal, the combination of the control signal the when control signal when 2 times boost and 1 times boost, the control signal the when control signal in the time of also 3 times can being boosted and 1 times boost makes up.But, when should be noted that the control signal combination that the multiple difference of boosting is big, because the voltage that output capacitor Cout will be big with potential difference carries out smoothing processing, so the pulsation of output voltage will increase.
In fact, if the absolute value of output voltage V out is greater than target voltage Vref, short during the supply of the control signal when boosting than low power during the supply of the control signal when such control just makes high power boost, on the contrary, it is long during the supply of the control signal when boosting than low power during the supply of the control signal when if the absolute value of output voltage V out less than voltage Vref, just makes high power boost.Like this, output voltage V out just comes balanced with voltage Vref, maintain in a certain certain scope.
Therefore,, utilize booster circuit itself just can make output voltage certain according to such control, so, the advantage that voltage stabilizing circuit can be set in the back level had.In addition, even input voltage vin for example reduces in time, output voltage V out also can be by boost multiple and keep certain between Vin～4Vin of raising, so, can enlarge operating time of load.
Here, be the comparison according to target voltage Vref and output voltage V out, the control signal of the multiple that respectively boosts is supplied with in timesharing, and the such FEEDBACK CONTROL of ratio during its supply of utilization control makes output voltage V out keep certain, but the present invention is not limited to this.For example, also can adopt boost control circuit 120 according to the comparison of input voltage vin timesharing supply with the control signal of the multiple that respectively boosts, utilize its such FEEDBACK CONTROL of ratio during supplying with of control to make output voltage V out keep certain structure.
(embodiment 2)
Below, the booster circuit of the embodiment of the invention 2 is described.In the foregoing description 1, be that the multiple that boosts is taken as 4 times～1 times, in the present embodiment, then be taken as 16 times.Figure 10 is the circuit diagram of structure of the booster circuit 132 of expression present embodiment.The printed circuit 130 that illustrated booster circuit 132 is permutation graphs 1 is used as power circuit 100, as shown in the figure, this booster circuit 132 with the printed circuit 130 of embodiment 1 as basic circuit, the circuit that affix auxiliary capacitor C3, C4 form, details is as follows.
Promptly, the terminal C2H the 1st of auxiliary capacitor C2 is by being connected as the p channel transistor Q10 of signal control signal f with the terminal C3L on one side of auxiliary capacitor C3, and and then by control signal e is connected with earth connection as the n channel transistor Q11 of signal, the 2nd passes through control signal e is connected with the terminal C3H of the another side of auxiliary capacitor C3 as the n channel transistor Q9 of signal.
In addition, the terminal C3H the 1st of auxiliary capacitor C3 is by being connected as the p channel transistor Q14 of signal control signal g with the terminal C4L on one side of auxiliary capacitor C4, and and then by control signal h2 is connected with earth connection as the n channel transistor Q15 of signal, the 2nd passes through control signal h1 is connected with the terminal C4H of the another side of auxiliary capacitor C4 as the n channel transistor Q13 of signal, and and then by control signal g is connected with the output line of output voltage V out as the p channel transistor Q12 of signal.And output capacitor Cout is the same with embodiment, for smooth output voltage Vout, is connected in parallel between this output line and the earth connection.
In such structure, when carrying out 16 times boost, 1. boost control circuit 120 is divided into following～5. during supply with control signal, the break-make of each transistor Q2～Q15 of control booster circuit 130.
That is, the 1st, as Figure 11 1. shown in like that, boost control circuit 120 is connected terminal C1H with the supply line of input voltage vin, simultaneously terminal C1L is connected with earth connection.Like this, auxiliary capacitor C1 just charges with Vin.
The 2nd, as Figure 11 2. shown in like that, boost control circuit 120 is connected terminal C1L with the supply line of input voltage vin, terminal C1H is connected with terminal C2H, in addition, terminal C2L is connected with earth connection.Like this, the current potential of terminal C1H just becomes the 2Vin of hot side that input voltage vin is offset to the output voltage V in of auxiliary capacitor C1, so auxiliary capacitor C2 just charges with 2Vin.
The 3rd, as Figure 11 3. shown in like that, boost control circuit 120 is with under terminal C1L and the state that the supply line of input voltage vin is connected, control is connected terminal C1H with terminal C2L, terminal C2H is connected with terminal C3H, in addition, terminal C3L is connected with earth connection.Like this, the current potential of terminal C2H is with regard to becoming the 4Vin of hot side that current potential with terminal C1H (C2L) is offset to the output voltage 2Vin of auxiliary capacitor C2, so auxiliary capacitor C3 just charges with 4Vin.
The 4th, as Figure 11 4. shown in like that, boost control circuit 120 controls are connected with the supply line of input voltage vin with regard to terminal C1L, with under terminal C1H and the state that terminal C2L is connected, control is connected terminal C2H with terminal C3L, terminal C3H is connected with terminal C4H, in addition, terminal C4L is connected with earth connection.Like this, the current potential of terminal C3H just becomes the 8Vin of hot side that current potential 4Vin with terminal C2H (C3L) is offset to the output voltage 4Vin of auxiliary capacitor C3, so auxiliary capacitor C4 just charges with 8Vin.
The 5th, as Figure 11 5. shown in like that, boost control circuit 120 controls are connected with the supply line of input voltage vin with regard to terminal C1L, be connected with terminal C2L with regard to terminal C1H, in addition, with under terminal C2H and the state that terminal C3L is connected, terminal C3H is connected with terminal C4L, terminal C4H is connected with the output line of output voltage V out.Like this, the current potential of output line just becomes the 16Vin of hot side that current potential 8Vin with terminal C3H (C4L) is offset to the output voltage 8Vin of auxiliary capacitor C4.Like this, utilize 4 auxiliary capacitor C1～C4 just can carry out 16 times boosting.
In the present embodiment, as the development of embodiment 1, be to charge to auxiliary capacitor C1～C4 with following current potential respectively.
Promptly, for auxiliary capacitor C1, can charge with Vin, for auxiliary capacitor C2, can charge with Vin or 2Vin, for auxiliary capacitor C3, can charge with Vin, 2Vin, 3Vin or 4Vin, in addition, for auxiliary capacitor C4, can be with 0, Vin, 2Vin ..., 7Vin or 8Vin charge.Therefore, the output voltage that auxiliary capacitor C1～C4 suitably makes up is setovered by the supply line utilization that will supply with input voltage vin, just can obtain Vin, 2Vin, 3Vin ..., 16Vin output voltage V out.
Boost control circuit 1 20 is supplied with the control signal that regulation is given the multiple that boosts by timesharing, control the ratio during this supply, just can be with the multiple no polar region control between 16 times～1 times of boosting, simultaneously, ratio by during supplying with according to the comparative result control of output voltage V out and target voltage Vref just can make output voltage V out keep certain between 16Vin～Vin.
In addition, for the present invention, by expansion embodiment 1 and embodiment 2, promptly by adopting the structure of appending auxiliary capacitor equally, just can 32 times, 64 times ..., 2
nDoubly input voltage vin is boosted.At this moment, the number of the needed auxiliary capacitor that boosts uses n individual just much of that, so fine finishining can be simplified.In addition, can make the multiple that boosts 2
nNo polar region changes between～1 times, and can make output voltage V out keep certain in this interval voltage.
In addition,, in the structure of setovering again simultaneously of charging, used auxiliary capacitor, still,, be not limited to this, for example, also can use secondary cell for the present invention for the foregoing description 1 and embodiment 2.
In addition, for embodiment 1 and embodiment 2, what illustrate is that input voltage vin is positive side and the situation that the direction of biasing is adopted the positive supply of identical side of the positive electrode with respect to reference potential, but, the invention is not restricted to this, also can be applied to adopt minus side the direction of biasing not to be adopted the situation of the negative supply of minus side with respect to reference potential input voltage.
For embodiment 1 and embodiment 2, employing be the structure of carrying out the connection or the switching of auxiliary capacitor with transistor, still, the structure that also can adopt various switches such as utilizing analog switch or transmission gate to carry out the connection or the switching of auxiliary capacitor.
The electronic instrument of＜use power circuit 〉
The booster circuit 130 of embodiment 1 and the booster circuit 132 of the embodiment 2 and booster circuit of their expansions for example be can be used as to the power circuit of the each several part supply power of liquid crystal indicator used.Figure 12 is the block diagram of the electrical structure of expression liquid crystal indicator.As shown in the figure, on display panels 200, each intersection point at i bar data wire X1～Xi and j bar scan line Y1～Yj forms liquid crystal cell 202, and each liquid crystal cell 202 is structures that liquid crystal display key element (liquid crystal layer) 204 and thin film diode (Thin Film Diode: be called " TFD " later on) element 206 are connected in series.
And each scan line Y1～Yj is driven by scan signal drive circuit 210, and each data wire X1～Xi is driven by data-signal drive circuit 220.In addition, scan signal drive circuit 210 and data-signal drive circuit 220 are controlled by Drive and Control Circuit 230.Among Figure 12, be that TFD element 206 is connected with scan line one side, liquid crystal layer 204 is connected with data wire one side, still, in contrast, also can be TFD element 206 to be arranged on data wire one side and the structure that liquid crystal layer 204 is arranged on scan line one side.
When using such power circuit 100, even when the pixel by increasing conducting etc. increase load, output voltage also is suppressed in change in certain scope, so, can prevent the display quality reduction.In addition, even input voltage vin reduces in time, because output voltage is suppressed in change in certain scope, so, can work long hours.
As liquid crystal indicator, can adopt and use TFT (Thin FilmTransistor: active matrix mode thin-film transistor) or do not use the various display unit such as passive matrix mode of the switch element of TFD or TFT etc.In addition, be not limited to liquid crystal indicator, also can be applied on the insulating barrier of EL (electroluminescence) layer that has been covered, form the power circuit of the EL display unit of column electrode and row electrode.In addition, also be not limited to display unit, can also be applied to projecting apparatus, microcomputer, pager, LCD TV, view finder formula or monitor direct-viewing type video camera, car steering guider, electronic notebook, calculator, word processor, work station, mobile phone, video telephone, POS terminal, have the electronic instruments such as device of touch-screen.
As mentioned above, according to the present invention, boost 2
nDoubly needed charge storage element has n just much of that, so, can simplified structure, can more freely control the multiple that boosts simultaneously.
Claims (12)
1. booster circuit is characterized in that: have the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment are connected simultaneously the 1st linkage unit that the terminal with the another side of above-mentioned the 1st charge storage element is connected with the 2nd line with current potential different with above-mentioned the 1st line, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd linkage unit that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of above-mentioned the 2nd charge storage element is switched to the terminal that is connected with the terminal of the another side of above-mentioned the 1st charge storage element simultaneously the another side of above-mentioned the 2nd charge storage element switch to the 3rd linkage unit that is connected with output line.
2. by the described booster circuit of claim 1, it is characterized in that: have terminal with one side of above-mentioned the 2nd charge storage element and be connected simultaneously the 4th linkage unit that the terminal with another side is connected with above-mentioned the 2nd line and the control unit that is connected with above-mentioned the 2nd charge storage element that utilizes above-mentioned the 4th linkage unit of being connected of controlling above-mentioned the 2nd charge storage element that utilizes above-mentioned the 2nd linkage unit exclusively with above-mentioned the 1st line.
3. by the described booster circuit of claim 2, it is characterized in that: above-mentioned control unit is based on the absolute value of the current potential of the current potential of above-mentioned the 2nd line or above-mentioned output line during less than the value of appointment, and to be controlled to be Billy during the connection of above-mentioned the 2nd charge storage element of above-mentioned the 2nd linkage unit long during with the connection of above-mentioned the 2nd charge storage element of above-mentioned the 4th linkage unit with utilizing.
4. by claim 1 or 2 described booster circuits, it is characterized in that: have under the terminal on one side of above-mentioned the 1st charge storage element and state that above-mentioned the 2nd line is connected the 5th linkage unit that the terminal with the another side of above-mentioned the 1st charge storage element is connected with above-mentioned output line and control being connected and the control unit that is connected that utilizes above-mentioned the 5th linkage unit of above-mentioned the 2nd charge storage element that utilizes the above-mentioned the 2nd or the 4th linkage unit exclusively.
5. by the described booster circuit of claim 4, it is characterized in that: above-mentioned control unit is based on the absolute value of the current potential of the current potential of above-mentioned the 2nd line or above-mentioned output line during less than the value of appointment, is controlled to be than long during the connection of above-mentioned the 5th linkage unit during utilizing the connection of above-mentioned the 2nd charge storage element of the above-mentioned the 2nd or the 4th linkage unit.
6. by claim 1,2 or 4 described booster circuits, it is characterized in that: have the 6th linkage unit that above-mentioned the 2nd line is connected with above-mentioned output line and the connection and the control unit that is connected that utilizes above-mentioned the 6th linkage unit that are connected or utilize above-mentioned the 5th linkage unit of controlling above-mentioned the 2nd charge storage element that utilizes the above-mentioned the 2nd or the 4th linkage unit exclusively.
7. by the described booster circuit of claim 6, it is characterized in that: above-mentioned control unit is based on the absolute value of the current potential of the current potential of above-mentioned the 2nd line or above-mentioned output line during less than the value of appointment, with utilize during the connection of above-mentioned the 2nd charge storage element of the above-mentioned the 2nd or the 4th linkage unit or utilize the connection of above-mentioned the 5th linkage unit during be controlled to be than long during the connection of above-mentioned the 6th linkage unit.
8. booster circuit with n at least (n is the integer 3 or more) charge storage element is characterized in that: have with the 1st line connection of the terminal on one side of the 1st charge storage element and the current potential with appointment simultaneously with the terminal of the another side of above-mentioned the 1st charge storage element with have and be connected the 1st linkage unit that the 2nd line of the different current potential of the 1st line is connected, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd linkage unit that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of m (m is for satisfying the integer of 3≤m≤n) charge storage element is connected simultaneously terminal with one side of above-mentioned (m-1) charge storage element to be switched to be connected with the terminal of the another side of above-mentioned (m-2) charge storage element and the terminal of the another side of above-mentioned (m-1) accumulator element to be switched to the 3rd～the n linkage unit that is connected with the terminal of the another side of above-mentioned m charge storage element and terminal with one side of n charge storage element and switches to the terminal that is connected with the terminal of the another side of the charge storage element of (n-1) simultaneously the another side of above-mentioned n charge storage element and switch to (n+1) linkage unit that is connected with output line with above-mentioned the 1st line.
9. step-up method is characterized in that: comprise the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment are connected simultaneously the 1st process that the terminal with the another side of above-mentioned the 1st charge storage element is connected with the 2nd line with current potential different with above-mentioned the 1st line, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd process that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of above-mentioned the 2nd charge storage element is switched to the terminal that is connected with the terminal of the another side of above-mentioned the 1st charge storage element simultaneously the another side of above-mentioned the 2nd charge storage element switch to the 3rd process that is connected with output line.
10. step-up method is characterized in that: comprise with have at least n the 1st charge storage element in (n is the integer 3 or more) charge storage element one side terminal and the current potential with appointment the connection of the 1st line simultaneously with the terminal of the another side of above-mentioned the 1st charge storage element with have and be connected the 1st process that the 2nd line of the different current potential of the 1st line is connected, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd process that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of m (m is for satisfying the integer of 3≤m≤n) charge storage element is connected simultaneously terminal with one side of above-mentioned (m-1) charge storage element to be switched to be connected with the terminal of the another side of above-mentioned (m-2) charge storage element and the terminal of the another side of above-mentioned (m-1) charge storage element to be switched to the 3rd～the n process that is connected with the terminal of the another side of above-mentioned m charge storage element and terminal with one side of n charge storage element and switches to the terminal that is connected with the terminal of the another side of the charge storage element of (n-1) simultaneously the another side of above-mentioned n charge storage element and switch to (n+1) process that is connected with output line with above-mentioned the 1st line.
11. electronic instrument, it is characterized in that: have the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment are connected simultaneously the 1st linkage unit that the terminal with the another side of above-mentioned the 1st charge storage element is connected with the 2nd line with current potential different with above-mentioned the 1st line, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd linkage unit that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of above-mentioned the 2nd charge storage element is switched to the terminal that is connected with the terminal of the another side of above-mentioned the 1st charge storage element simultaneously the another side of above-mentioned the 2nd charge storage element switch to the 3rd linkage unit that is connected with output line, and will use as power supply based on the current potential of above-mentioned output line.
12. electronic instrument, it is the booster circuit that has n (n is the integer more than 3) charge storage element at least, it is characterized in that: this booster circuit has the terminal on one side of the 1st charge storage element and the 1st line of the current potential with appointment is connected simultaneously the 1st linkage unit that the terminal with the another side of above-mentioned the 1st charge storage element is connected with the 2nd line with current potential different with above-mentioned the 1st line, the terminal on one side of the 2nd charge storage element is connected simultaneously terminal with one side of above-mentioned the 1st charge storage element to be switched to and is connected with above-mentioned the 2nd line and the terminal of the another side of above-mentioned the 1st charge storage element is switched to the 2nd linkage unit that is connected with the terminal of the another side of above-mentioned the 2nd charge storage element with above-mentioned the 1st line, the terminal on one side of m (m is for satisfying the integer of 3≤m≤n) charge storage element is connected simultaneously terminal with one side of above-mentioned (m-1) charge storage element switches to be connected with the terminal of the another side of above-mentioned (m-2) charge storage element and the terminal of the another side of above-mentioned (m-1) accumulator element to be switched to the 3rd～the n linkage unit that is connected with the terminal of the another side of above-mentioned m charge storage element and terminal and switch to the terminal that is connected with the terminal of the another side of the charge storage element of (n-1) simultaneously the another side of above-mentioned n charge storage element and switch to (n+1) linkage unit that is connected with output line with above-mentioned the 1st line, will use as power supply based on the current potential of above-mentioned output line with one side of n charge storage element.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06521799A JP3316468B2 (en) | 1999-03-11 | 1999-03-11 | Booster circuit, boosting method and electronic device |
| JP65217/99 | 1999-03-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1267120A true CN1267120A (en) | 2000-09-20 |
Family
ID=13280537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN00103768A Pending CN1267120A (en) | 1999-03-11 | 2000-03-09 | Boost up circuit method and electronic apparatus |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6556064B1 (en) |
| EP (1) | EP1037367B1 (en) |
| JP (1) | JP3316468B2 (en) |
| KR (1) | KR100615837B1 (en) |
| CN (1) | CN1267120A (en) |
| DE (1) | DE60023775T2 (en) |
| TW (1) | TW527500B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104871108A (en) * | 2012-11-26 | 2015-08-26 | 北极砂技术有限公司 | Pump capacitor configuration for switched capacitor circuits |
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|---|---|---|---|---|
| DE10050496B4 (en) | 2000-10-11 | 2015-04-02 | Texas Instruments Deutschland Gmbh | DC converter |
| JP2004064937A (en) * | 2002-07-31 | 2004-02-26 | Nec Corp | Charge pump-type boosting circuit |
| AU2003255877A1 (en) * | 2002-08-28 | 2004-03-19 | Koninklijke Philips Electronics N.V. | Voltage doubler circuit |
| US6861894B2 (en) * | 2002-09-27 | 2005-03-01 | Sandisk Corporation | Charge pump with Fibonacci number multiplication |
| US6985024B2 (en) * | 2003-08-21 | 2006-01-10 | Analog Devices, Inc. | Voltage multiplier |
| JP3846478B2 (en) * | 2004-01-15 | 2006-11-15 | セイコーエプソン株式会社 | Boost circuit, power supply circuit, and liquid crystal drive device |
| JP3841083B2 (en) * | 2004-01-20 | 2006-11-01 | セイコーエプソン株式会社 | Boost circuit, power supply circuit, and liquid crystal drive device |
| JP4352937B2 (en) * | 2004-03-03 | 2009-10-28 | セイコーエプソン株式会社 | Power supply circuit, electro-optical device and electronic apparatus |
| JP2004248497A (en) * | 2004-03-08 | 2004-09-02 | Seiko Epson Corp | Power supply circuit, liquid crystal device, and electronic apparatus |
| JP3904579B2 (en) | 2004-12-03 | 2007-04-11 | ローム株式会社 | Power supply device, light emitting device using the same, and electronic device |
| JP4024814B2 (en) * | 2005-02-24 | 2007-12-19 | シャープ株式会社 | Charge pump type DC / DC converter circuit |
| US20060250177A1 (en) * | 2005-05-09 | 2006-11-09 | Thorp Tyler J | Methods and apparatus for dynamically reconfiguring a charge pump during output transients |
| US7236046B2 (en) | 2005-11-01 | 2007-06-26 | Catalyst Semiconductor, Inc. | LED bias current control using adaptive fractional charge pump |
| US7602232B2 (en) * | 2005-11-01 | 2009-10-13 | Semiconductor Components Industries, L.L.C. | Programmable fractional charge pump for DC-DC converter |
| US7557641B2 (en) * | 2005-11-01 | 2009-07-07 | Catalyst Semiconductor, Inc. | Fractional charge pump for step-down DC-DC converter |
| JP2007259519A (en) * | 2006-03-20 | 2007-10-04 | Rohm Co Ltd | Charge pump circuit, lcd driver ic, liquid crystal display |
| JP2008125145A (en) * | 2006-11-08 | 2008-05-29 | Mcm Japan Kk | Voltage step-up circuit and voltage step-down circuit |
| JP2008125269A (en) * | 2006-11-14 | 2008-05-29 | Mcm Japan Kk | Voltage step-up circuit and voltage step-down circuit |
| DE102006060011A1 (en) * | 2006-12-19 | 2008-07-03 | Austriamicrosystems Ag | Voltage converter for operating light arrangement, has level that has capacitor recharged by input voltage in capacitor voltage, and formed in way that capacitor voltage is tapped at output of level as voltage |
| US8068356B2 (en) * | 2008-05-28 | 2011-11-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Low power one-shot boost circuit |
| JP5600881B2 (en) * | 2009-03-06 | 2014-10-08 | セイコーエプソン株式会社 | DC-DC converter circuit, electro-optical device, and electronic apparatus |
| JP2011083141A (en) * | 2009-10-08 | 2011-04-21 | Renesas Electronics Corp | Step-up power supply circuit |
| KR101315143B1 (en) * | 2012-08-22 | 2013-10-14 | 전북대학교산학협력단 | High efficiency dc/dc power converter with high conversion ratio |
| JP5995940B2 (en) * | 2014-11-13 | 2016-09-21 | ラピスセミコンダクタ株式会社 | Boosting method |
| US10396776B2 (en) | 2017-06-29 | 2019-08-27 | Apple Inc. | Drive voltage booster |
| KR102695525B1 (en) * | 2019-05-30 | 2024-08-14 | 삼성전자주식회사 | Boost converter, and cell applicable to the boost converter |
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-
1999
- 1999-03-11 JP JP06521799A patent/JP3316468B2/en not_active Expired - Lifetime
-
2000
- 2000-03-03 TW TW089103831A patent/TW527500B/en not_active IP Right Cessation
- 2000-03-08 US US09/520,787 patent/US6556064B1/en not_active Expired - Lifetime
- 2000-03-09 CN CN00103768A patent/CN1267120A/en active Pending
- 2000-03-10 KR KR1020000011995A patent/KR100615837B1/en active IP Right Grant
- 2000-03-10 EP EP00301991A patent/EP1037367B1/en not_active Expired - Lifetime
- 2000-03-10 DE DE60023775T patent/DE60023775T2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104871108A (en) * | 2012-11-26 | 2015-08-26 | 北极砂技术有限公司 | Pump capacitor configuration for switched capacitor circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| DE60023775T2 (en) | 2006-06-29 |
| TW527500B (en) | 2003-04-11 |
| KR100615837B1 (en) | 2006-08-25 |
| EP1037367A3 (en) | 2000-11-02 |
| KR20010014560A (en) | 2001-02-26 |
| US6556064B1 (en) | 2003-04-29 |
| JP2000262045A (en) | 2000-09-22 |
| EP1037367B1 (en) | 2005-11-09 |
| JP3316468B2 (en) | 2002-08-19 |
| EP1037367A2 (en) | 2000-09-20 |
| DE60023775D1 (en) | 2005-12-15 |
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| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20000920 |
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| C20 | Patent right or utility model deemed to be abandoned or is abandoned |