CN113870780A - Pixel circuit and display panel - Google Patents
Pixel circuit and display panel Download PDFInfo
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- CN113870780A CN113870780A CN202111100940.4A CN202111100940A CN113870780A CN 113870780 A CN113870780 A CN 113870780A CN 202111100940 A CN202111100940 A CN 202111100940A CN 113870780 A CN113870780 A CN 113870780A
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- 230000000087 stabilizing effect Effects 0.000 claims description 12
- 230000006641 stabilisation Effects 0.000 claims 1
- 238000011105 stabilization Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 21
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 14
- 230000003071 parasitic effect Effects 0.000 description 9
- 239000003990 capacitor Substances 0.000 description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 7
- 229910052733 gallium Inorganic materials 0.000 description 7
- 229910052738 indium Inorganic materials 0.000 description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 239000011787 zinc oxide Substances 0.000 description 7
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Abstract
The invention discloses a pixel circuit and a display panel, wherein the pixel circuit comprises a driving module, a storage module, a light-emitting module, a data writing module, a first compensation and leakage suppression module and a second compensation and leakage suppression module. The first end of the first compensation and leakage suppression module is connected with the first end of the driving module, the second end of the first compensation and leakage suppression module is connected with the first end of the second compensation and leakage suppression module, and the second end of the second compensation and leakage suppression module is connected with the control end of the driving module. The first compensation and leakage suppression module comprises at least one transistor, the transistor in the first compensation and leakage suppression module is an N-type transistor, the second compensation and leakage suppression module comprises at least one transistor, and the transistor in the second compensation and leakage suppression module is a P-type transistor. The pixel circuit provided by the embodiment of the invention reduces the leakage current, ensures the display effect of low-frequency drive and improves the display quality.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a pixel circuit and a display panel.
Background
With the development of display products, the demand for low frequency refresh to reduce power consumption is increasing.
In the prior art, the LTPO technology is selected for a pixel circuit, an indium gallium zinc oxide thin film transistor (IGZO TFT) is used as a switching transistor connected to a driving transistor, and the problem of unstable gate voltage under low-frequency driving is solved by using the low leakage current of the IGZO TFT. However, the gate voltage of the driving transistor is unstable, which causes display abnormality.
Disclosure of Invention
The invention provides a pixel circuit and a display panel, which are used for reducing leakage current, ensuring a low-frequency driving display effect and improving display quality.
In a first aspect, an embodiment of the present invention provides a pixel circuit, including: the device comprises a driving module, a storage module, a light-emitting module, a data writing module, a first compensation and leakage suppression module and a second compensation and leakage suppression module;
the data writing module is used for writing data voltage into the control end of the driving module;
the storage module is connected with the control end of the driving module and used for storing the voltage of the control end of the driving module;
the driving module is used for generating driving current according to the voltage stored in the storage module and outputting the driving current from a first end to drive the light-emitting module to emit light;
a first end of the first compensation and leakage suppression module is connected with a first end of the driving module, a second end of the first compensation and leakage suppression module is connected with a first end of the second compensation and leakage suppression module, and a second end of the second compensation and leakage suppression module is connected with a control end of the driving module; the first compensation and leakage suppression module comprises at least one transistor, the transistor in the first compensation and leakage suppression module is an N-type transistor, the second compensation and leakage suppression module comprises at least one transistor, and the transistor in the second compensation and leakage suppression module is a P-type transistor.
Optionally, the pixel circuit further includes an initialization module, a first end of the initialization module is connected to the first end of the first compensation and leakage current suppression module, a second end of the initialization module is connected to the first end of the light emitting module, and the initialization module is configured to write an initialization voltage into the control end of the driving module and the first end of the light emitting module; the initialization module comprises at least two transistors, and the transistors in the initialization module are N-type transistors.
Optionally, the initialization module includes a first transistor and a second transistor, a first pole of the first transistor is connected to an initialization signal line, a second pole of the first transistor is connected to a first end of the first compensation and leakage suppression module, and a gate of the first transistor is connected to a first scan line;
a first pole of the second transistor is connected to the initialization signal line, a second pole of the second transistor is connected to a first end of the light emitting module, and a gate of the second transistor is connected to the first scan line.
Optionally, the first compensation and leakage suppression module includes a third transistor, a first pole of the third transistor is connected to the first end of the driving module, a second pole of the third transistor is connected to the first end of the second compensation and leakage suppression module, and a gate of the third transistor is connected to the second scan line.
Optionally, in a frame, a time interval of the pulse of the signal on the first scan line is within a time interval of the pulse of the signal on the second scan line.
Optionally, the second compensation and leakage suppression module includes a fourth transistor, a first pole of the fourth transistor is connected to the second end of the first compensation and leakage suppression module, a second pole of the fourth transistor is connected to the control end of the driving module, and a gate of the fourth transistor is connected to the third scan line. Optionally, the pixel circuit further includes a voltage stabilizing module;
the voltage stabilizing module is connected between the control end of the driving module and the fourth scanning line and used for stabilizing the voltage of the control end of the driving module;
the control end of the data writing module is connected with the fourth scanning line, the first end of the data writing module is connected with the data line, and the second end of the data writing module is connected with the second end of the driving module.
Optionally, the pixel circuit further includes a first light emission control module and a second light emission control module;
the first light-emitting control module is connected between a first power line and the second end of the driving module, the second light-emitting control module is connected between the first end of the driving module and the first end of the light-emitting module, the second end of the light-emitting module is connected with a second power line, and the control end of the first light-emitting control module and the control end of the second light-emitting control module are connected with a light-emitting control signal line.
Optionally, the first light-emitting control module includes a fifth transistor, the second light-emitting control module includes a sixth transistor, the driving module includes a seventh transistor, and the data writing module includes an eighth transistor;
a first pole of the fifth transistor is connected to the first power line, a second pole of the fifth transistor is connected to a first pole of the seventh transistor, a gate of the fifth transistor is connected to the light emission control signal line, a first pole of the sixth transistor is connected to a second pole of the seventh transistor, a second pole of the sixth transistor is connected to the first end of the light emitting module, a gate of the sixth transistor is connected to the light emission control signal line, and a gate of the seventh transistor is connected to the second end of the second compensation and leakage suppression module;
a first pole of the eighth transistor is connected to the data line, a second pole of the eighth transistor is connected to the first pole of the seventh transistor, and a gate of the eighth transistor is connected to the fourth scan line.
In a second aspect, an embodiment of the present invention further provides a display panel, where the display panel includes the pixel circuit described in any one of the first aspects.
The embodiment of the invention provides a pixel circuit and a display panel, wherein a transistor in a second compensation and leakage suppression module connected with a control end of a driving module in the pixel circuit is a P-type transistor, and the parasitic capacitance of the P-type transistor is smaller, so that the influence of the second compensation and leakage suppression module on the potential of the control end of the driving module after being turned off is smaller. The grid of the P-type transistor applies high voltage to be turned off, so that when the second compensation and leakage suppression module is turned off, the voltage of the control end of the driving module is increased, and the problem that the driving module is continuously turned off in a black state due to the fact that the grid voltage is reduced is solved. The transistors in the first compensation and leakage suppression module are N-type transistors, the leakage current is small, and the stability of the voltage of the control end of the driving module is favorably maintained.
Drawings
Fig. 1 is a schematic structural diagram of a pixel circuit in the prior art.
Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 9 is a timing diagram of a pixel circuit according to an embodiment of the invention;
fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, in the existing pixel circuit, the IGZO technology is complex and the process is sensitive, and the size of the transistor formed by the IGZO cannot be made smaller, so that the parasitic capacitance of the transistor formed by the IGZO is larger, the influence on the gate voltage of the driving transistor is increased, and the gate voltage of the driving transistor is changed greatly when the transistor formed by the IGZO is turned off. In addition, the conventional pixel circuit has large leakage current, so that the voltage of the grid electrode of the driving transistor cannot be kept stable for a long time, and the display effect of low-frequency driving cannot be ensured.
Exemplarily, fig. 1 is a schematic structural diagram of a conventional pixel circuit, and referring to fig. 1, the pixel circuit includes a driving transistor T0, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a light emitting module D1, the driving transistor T0, the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are P-type transistors, and the third transistor T3 and the fifth transistor T5 are N-type transistors. A first electrode of the fifth transistor T5 is connected to the first initialization signal line Vref1, a first electrode of the sixth transistor T6 is connected to the second initialization signal line Vref2, and a first electrode of the first transistor T1 is connected to the data line Vdata. In operation of the pixel driving circuit, during a light emission period, the signal provided by the first scan line S1 is at a low level, the signal provided by the second scan line S2 is at a high level, the signal provided by the third scan line S3 is at a high level, the signal provided by the fourth scan line S4 is at a low level, and the signal provided by the light emission control signal line is at a low level. At this time, the second transistor T2 and the fourth transistor T2 are turned on, and the second transistor T2 outputs the first power voltage supplied from the first power line Vdd to the first electrode of the driving transistor T0. The driving transistor T0 generates a driving current according to the voltage of the gate and the first electrode, and the driving current flows out through the second electrode to drive the light emitting module D1 to emit light. In the light emitting stage, the third transistor T3 and the fifth transistor T5 are turned off, but the third transistor T3 and the fifth transistor T5 still have leakage current, and the two leakage current paths make the leakage current large, the gate voltage of the driving transistor T0 cannot be kept stable for a long time, and the display effect of low-frequency driving cannot be ensured. The third transistor T3 is an N-type transistor, and has a large size, so that the parasitic capacitance thereof is large, and the larger the parasitic capacitance is, the larger the influence on the gate voltage of the driving transistor T0 is, and when the third transistor T3 is turned off, the gate voltage of the driving transistor T0 is changed greatly due to the parasitic capacitance thereof. When the third transistor T3 is turned off, the gate voltage of the driving transistor T0 is lowered. This causes the problem that the driving transistor T0 is turned off continuously in the black state, so that the black image display is bright.
To solve the above technical problem, an embodiment of the present invention provides a pixel circuit, and fig. 2 is a schematic structural diagram of the pixel circuit provided in the embodiment of the present invention, and referring to fig. 2, the pixel circuit includes: the driving module 100, the memory module 200, the light emitting module 300, the data writing module 400, the first compensation and leakage suppression module 500, and the second compensation and leakage suppression module 600;
the data writing module 400 is used for writing a data voltage into the control terminal G of the driving module 100;
the storage module 200 is connected to the control terminal G of the driving module 100, and is configured to store a voltage of the control terminal G of the driving module 100;
the driving module 100 is configured to generate a driving current according to the voltage stored in the storage module 200, and output the driving current from a first terminal to drive the light emitting module 300 to emit light;
a first end of the first compensation and leakage suppression module 500 is connected to a first end of the driving module 100, a second end of the first compensation and leakage suppression module 500 is connected to a first end of the second compensation and leakage suppression module 600, and a second end of the second compensation and leakage suppression module 600 is connected to a control end G of the driving module 100; the first compensation and leakage suppression module 500 includes at least one transistor, the transistors in the first compensation and leakage suppression module 500 are N-type transistors, the second compensation and leakage suppression module 600 includes at least one transistor, and the transistors in the second compensation and leakage suppression module 600 are P-type transistors.
Optionally, a first end of the data writing module 400 is connected to the data line Vdata, and a second end of the data writing module 400 is connected to the second end of the driving module 100.
Optionally, the pixel circuit further includes a light emitting control module 700, where the light emitting control module 700, the driving module 100, and the light emitting module 300 are connected between a first power line Vdd and a second power line Vss, and the light emitting control module 700 is configured to control the light emitting module 300 to emit light according to the driving current output by the driving module 100 according to the signal on the light emitting control signal line EM.
Optionally, the pixel circuit further includes an initialization module 800, a first end of the initialization module 800 is connected to the first end of the first compensation and leakage current suppression module 500, a second end of the initialization module 800 is connected to the first end of the light emitting module 300, and the initialization module 800 is configured to write an initialization voltage into the control end G of the driving module 100 and the first end of the light emitting module 300; the initialization block 800 includes at least two transistors, and the transistors in the initialization block 800 are N-type transistors.
The initialization module 800 is connected to the initialization signal line Vref, and for example, the initialization module 800 may include two transistors, one transistor being connected between the initialization signal line Vref and the first compensation and leakage suppression module 500, for writing the initialization voltage to the control terminal G of the driving module 100 through the first compensation and leakage suppression module 500 and the second compensation and leakage suppression module 600. The other transistor is connected between the initialization signal line Vref and the first terminal of the light emitting module 300, and is used for writing an initialization voltage into the first terminal of the light emitting module 300.
For example, the memory module 200 may be a storage capacitor, and the storage capacitor stores the voltage of the control terminal G of the driving module 100. The Light Emitting module 300 may be an Organic Light Emitting Diode (OLED), and the OLED emits Light under the driving of a driving current. The first compensation and leakage suppression module 500 may include one transistor or a plurality of transistors, and the number of transistors in the first compensation and leakage suppression module 500 is not specifically limited in this embodiment. The transistor in the first compensation and leakage suppression module 500 may be an indium gallium zinc oxide thin film transistor (IGZO TFT), and the indium gallium zinc oxide thin film transistor has a small leakage current, so that the leakage current of the pixel circuit can be reduced, and the display effect of low-frequency driving is ensured. The second compensation and leakage current suppression module 600 may include one transistor or a plurality of transistors, and the number of transistors in the second compensation and leakage current suppression module 600 is not specifically limited in this embodiment. The transistor in the second compensation and leakage suppression module 600 is a P-type transistor, the transistor in the second compensation and leakage suppression module 600 may be a low-temperature polysilicon transistor, and the parasitic capacitance of the P-type transistor is small, so that the second compensation and leakage suppression module 600 has a small influence on the potential of the control terminal G of the driving module 100 after being turned off. . The pixel circuit operation process may include three phases: initialization phase, data voltage writing and threshold value compensation phase and light emitting phase. In the initialization phase, the first compensation and leakage suppression module 500, the second compensation and leakage suppression module 600, and the initialization module 800 are turned on, and the data writing module 400 and the light emitting control module 700 are turned off. The initialization voltage provided by the initialization signal line Vref is written to the control terminal G of the driving module 100 through the initialization module 800, the first compensation and leakage suppression module 500, and the second compensation and leakage suppression module 600. Meanwhile, the initialization voltage is written to the first terminal of the light emitting module 300 through the initialization module 800. The initialization of the control terminal G of the driving module 100 and the first terminal of the light emitting module is realized in the initialization stage. In the data voltage writing and threshold compensation stages, the data writing module 400, the first compensation and leakage current suppression module 500, and the second compensation and leakage current suppression module 600 are turned on, and the initialization module 800 and the light emitting control module 700 are turned off. The data voltage provided by the data line Vdata is written into the control terminal G of the driving module 100 through the data writing module 400, the driving module 100, the first compensation and leakage suppression module 500, and the second compensation and leakage suppression module 600, and since the first compensation and leakage suppression module 500 and the second compensation and leakage suppression module 600 can compensate the threshold of the driving module 100, the voltage at the control terminal G of the driving module 100 can include the voltage associated with the data voltage and the threshold voltage, and the data voltage writing and the threshold compensation of the driving module 100 are realized. In the light emitting stage, the data writing module 400, the first compensation and leakage suppression module 500, the second compensation and leakage suppression module 600, and the initialization module 800 are turned off, the light emitting control module 700 is turned on, the light emitting control module 700 transmits the first power voltage on the first power line Vdd to the second end of the driving module 100, and the driving module 100 generates a driving current according to the voltages of the control end G and the second end and outputs the driving current to the light emitting module 300 through the first end, so as to drive the light emitting module 300 to emit light.
In the pixel circuit provided by this embodiment, the transistor in the second compensation and leakage suppression module connected to the control terminal of the driving module is a P-type transistor, and the parasitic capacitance of the P-type transistor is small, so that the influence of the second compensation and leakage suppression module on the potential of the control terminal of the driving module after being turned off is small. The grid of the P-type transistor applies high voltage to be turned off, so that when the second compensation and leakage suppression module is turned off, the voltage of the control end of the driving module is increased, and the problem that the driving module is continuously turned off in a black state due to the fact that the grid voltage is reduced is solved. The transistors in the first compensation and leakage suppression module are N-type transistors, and the leakage current is small, which is beneficial to maintaining the stability of the voltage of the control end of the driving module.
Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 3, optionally, the pixel circuit further includes a first light-emitting control module 710 and a second light-emitting control module 720;
the first light emission control module 710 is connected between the first power line Vdd and the second end of the driving module 100, the second light emission control module 720 is connected between the first end of the driving module 100 and the first end of the light emitting module 300, the second end of the light emitting module 300 is connected to the second power line Vss, and the control end of the first light emission control module 710 and the control end of the second light emission control module 720 are connected to the light emission control signal line EM.
In the initialization phase of the pixel circuit and the data voltage writing and threshold value compensation phase, the first and second light emission control modules 710 and 220 are turned off under the control of the light emission control signal line EM. In the light emitting phase, the first light emitting control module 710 and the second light emitting control module 720 are turned on under the control of the light emitting control signal line EM, the first power voltage provided by the first power line Vdd is written into the second end of the driving module 100 through the first light emitting control module 710, and the driving module 100 drives the light emitting module 300 to emit light according to the voltage at the control end G and the voltage at the second end.
Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 4, on the basis of the above embodiment, optionally, the initialization module 800 includes a first transistor T1 and a second transistor T2, a first pole of the first transistor T1 is connected to the initialization signal line Vref, a second pole of the first transistor T1 is connected to the first end of the first compensation and leakage suppression module 500, and a gate of the first transistor T1 is connected to the first scan line S1;
a first electrode of the second transistor T2 is connected to the initialization signal line Vref, a second electrode of the second transistor T2 is connected to the first terminal of the light emitting module 300, and a gate of the second transistor T2 is connected to the first scan line S1.
Illustratively, the storage module includes a storage capacitor Cst, and the first transistor T1 and the second transistor T2 are both indium gallium zinc oxide thin film transistors. The first transistor T1 and the second transistor T2 are turned on when the signal on the first scan line S1 is at a high level, and the first transistor T1 and the second transistor T2 are turned off when the signal on the first scan line S1 is at a low level.
In the initialization stage, the first scan line S1 provides a high level signal, and the first transistor T1 and the second transistor T2 are turned on, so that an initialization voltage is written into the control terminal G of the driving module 100 and the first terminal of the light emitting module 300, thereby initializing the control terminal G of the driving module 100 and the light emitting module 300. The first transistor T1 is an indium gallium zinc oxide thin film transistor, and has a small leakage current, and when the first transistor T1 is turned off, the change of the voltage at the first end of the first compensation and leakage current suppression module 500 is reduced, so that the magnitude of the leakage current of the second compensation and leakage current suppression module 600 is reduced, the change of the voltage at the control end G of the driving module 100 is finally reduced, the stability of the voltage at the control end G of the driving module 100 is maintained, and the display effect of low-frequency driving is ensured. The second transistor T2 is an indium gallium zinc oxide thin film transistor, and when the second transistor T2 is turned off, the voltage variation of the first end of the light emitting module 300 is reduced, the voltage of the first end of the light emitting module 300 is maintained to be stable, and the display uniformity is improved.
Fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 5, on the basis of the above embodiment, optionally, the first compensation and leakage suppression module 500 includes a third transistor T3, a first pole of the third transistor T3 is connected to the first end of the driving module 100, a second pole of the third transistor T3 is connected to the first end of the second compensation and leakage suppression module 600, and a gate of the third transistor T3 is connected to the second scan line S2.
Specifically, the third transistor T3 is an indium gallium zinc oxide thin film transistor, and has a small leakage current. When the signal on the second scan line S2 is at a high level, the third transistor T3 is turned on, and when the signal on the second scan line S2 is at a low level, the third transistor T3 is turned off. In the light emitting stage, the third transistor T3 is turned off, and the leakage current is small when the third transistor T3 is in the off state, so that the voltage variation of the first end of the second compensation and leakage suppression module 600 is reduced, the magnitude of the leakage current of the second compensation and leakage suppression module 600 is reduced when the second compensation and leakage suppression module is turned off, and finally the voltage variation of the control end G of the driving module 100 is reduced, which is beneficial to maintaining the voltage stability of the control end G of the driving module 100, and ensuring the display effect of low-frequency driving.
Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the invention, and referring to fig. 6, optionally, the second compensation and leakage suppression module includes a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the second end of the first compensation and leakage suppression module 500, a second pole of the fourth transistor T4 is connected to the control terminal G of the driving module 100, and a gate of the fourth transistor T4 is connected to the third scan line S3.
The fourth transistor T4 is a P-type transistor, and when the signal on the third scanning line S3 is at a low level, the fourth transistor T4 is turned on, and when the signal on the third scanning line S3 is at a high level, the fourth transistor T4 is turned off. The third scan line S3 provides a low level during the initialization stage, the data voltage writing stage and the threshold voltage compensation stage, so that the fourth transistor T4 is turned on, and initialization of the control terminal G of the driving module 100, and writing of the data voltage and compensation of the threshold voltage are achieved. The third scanning line S3 provides a high level in a light emitting stage, so that the fourth transistor T4 is turned off.
Fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, fig. 8 is a timing diagram of a pixel circuit according to an embodiment of the present invention, and the timing diagram shown in fig. 8 is applicable to the pixel circuit shown in fig. 7. Referring to fig. 7 and 8, on the basis of the above embodiment, optionally, the first light emitting control module 710 includes a fifth transistor T5, the second light emitting control module 720 includes a sixth transistor T6, the driving module 100 includes a seventh transistor T7, and the data writing module 400 includes an eighth transistor T8;
a first pole of the fifth transistor T5 is connected to the first power line Vdd, a second pole of the fifth transistor T5 is connected to the first pole of the seventh transistor T7, a gate of the fifth transistor T5 is connected to the emission control signal line EM, a first pole of the sixth transistor T6 is connected to the second pole of the seventh transistor T7, a second pole of the sixth transistor T6 is connected to the first terminal of the light emitting module 300, a gate of the sixth transistor T6 is connected to the emission control signal line EM, and a gate of the seventh transistor T7 is connected to the second terminal of the second compensation and leakage suppression module 600;
a first pole of the eighth transistor T8 is connected to the data line Vdata, a second pole of the eighth transistor T8 is connected to a first pole of the seventh transistor T7, and a gate of the eighth transistor T8 is connected to the fourth scan line S4.
For example, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all P-type transistors, and the operation of the pixel circuit is described with reference to fig. 8.
In the initialization stage T1, the signal on the fourth scan line S4 and the signal on the emission control signal line EM are at a high level, and the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are turned off. The signals on the first scan line S1 and the second scan line S2 are at a high level, the signal on the third scan line S3 is at a low level, and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor are turned on. The initialization voltage supplied from the initialization signal line Vref is transmitted to the gate of the seventh transistor T7 through the first transistor T1, the third transistor T3, and the fourth transistor T4, thereby initializing the gate of the seventh transistor T7. Meanwhile, the initialization voltage provided from the initialization signal line Vref is transmitted to the first terminal of the light emitting module 300 through the second transistor T2, and the light emitting module 300 is initialized.
In the data voltage writing and threshold compensation period T2, the signal on the first scan line S1 is at a low level, the signal on the emission control signal line EM is at a high level, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off. The signals on the third scan line S3 and the fourth scan line S4 are at a low level, the signal on the second scan line S2 is at a high level, the fourth transistor T4, the eighth transistor T8 and the third transistor T3 are turned on, the data voltage on the data signal line Vdata is written to the gate of the seventh transistor T7 through the eighth transistor T8, the seventh transistor T7, the third transistor T3 and the fourth transistor T4, and the writing of the data voltage to the gate of the seventh transistor T7 and the compensation of the threshold voltage of the seventh transistor T7 are realized.
In the light emitting period T3, the signals on the first scan line S1 and the second scan line S2 are at a low level, the signals on the third scan line S3 and the fourth scan line S4 are at a high level, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the eighth transistor T8 are turned off. The signal on the emission control signal line EM is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. The first power voltage on the first power line Vdd is transmitted to the first pole of the seventh transistor T7 through the fifth transistor T5, and the seventh transistor T7 drives the light emitting module 300 to emit light according to the voltage of the gate thereof and the voltage of the first pole.
In the light emitting period, when the fourth transistor T4 is turned off, the gate voltage of the seventh transistor T7 changes by an amount Δ V (VGH-VGL) × C2/(C1+ C2), where VGL is a voltage applied to the gate of the fourth transistor T4 when the fourth transistor T4 is turned on, and VGH is a voltage applied to the gate of the fourth transistor T4 when the fourth transistor T4 is turned off. VGL <0, VGH >0, C1 is the capacitance of the storage capacitor Cst, and C2 is the parasitic capacitance of the fourth transistor T4 itself. As can be seen from the above formula, when the fourth transistor T4 is turned off, the gate voltage of the seventh transistor T7 changes by an amount Δ V >0, that is, the gate voltage of the seventh transistor T7 increases, thereby improving the problems of black-off and white-black image caused by gate voltage reduction.
Optionally, in one frame, the time interval of the pulse of the signal on the first scan line S1 is within the time interval of the pulse of the signal on the second scan line S2.
When the first transistor T1, the second transistor T2, and the third transistor T3 are all N-type transistors, the time interval during which the signal on the first scan line S1 is at the high level is within the time interval during which the signal on the second scan line S2 is at the high level in one frame. The first scan line S1 provides a high level signal during the initialization phase, such that the first transistor T1 and the second transistor T2 are turned on, the initialization voltage provided by the initialization signal line Vref is written into the control terminal G of the driving module 100, the third transistor T3 and the second compensation and leakage suppression module 600 must be turned on, and therefore, the signal on the second scan line S2 is also high during the initialization phase. During the data voltage writing and threshold compensation stages, the third transistor T3 still needs to be turned on, so the time interval of the high level signal on the second scan line S2 is longer than the time interval of the high level signal on the first scan line S1. The time interval of the pulse of the signal on the first scan line S1 is within the time interval of the pulse of the signal on the second scan line S2, so that in the initialization phase, the first transistor T1 and the third transistor T3 are both turned on, and the initialization voltage provided by the initialization signal line Vref is written into the control terminal G of the driving module 100.
Fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 9, optionally, the pixel circuit further includes a voltage stabilizing module 900, where the voltage stabilizing module 900 is connected between the control terminal G of the driving module 100 and the fourth scan line S4, and is used for stabilizing a voltage of the control terminal G of the driving module 100;
the control terminal of the data writing module 400 is connected to the fourth scan line S4, the first terminal of the data writing module 400 is connected to the data line Vdata, and the second terminal of the data writing module 400 is connected to the second terminal of the driving module 100.
For example, the voltage stabilizing module 900 may be a voltage stabilizing capacitor C0, and during the lighting phase, when the fourth transistor T4 is turned off, the variation Δ V of the gate voltage of the seventh transistor T7 is (VGH-VGL) × C2/(C1+ C2+ C3), where VGL is the voltage applied to the gate of the fourth transistor T4 when the fourth transistor T4 is turned on, and VGH is the voltage applied to the gate of the fourth transistor T4 when the fourth transistor T4 is turned off. VGL <0, VGH >0, C1 is the capacitance of the storage capacitor Cst, C2 is the parasitic capacitance of the fourth transistor T4 itself, and C3 is the capacitance of the voltage stabilizing capacitor C0. As can be seen from the above formula, after the voltage stabilizing capacitor C0 is added, the variation Δ V of the gate voltage of the seventh transistor T7 is reduced, so that the variation of the gate voltage of the seventh transistor T7 can be further reduced, which is beneficial to ensuring the stability of the display.
The embodiment of the invention also provides a display panel which comprises the pixel circuit.
Fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 10, the display device 01 includes the display panel 02 described above. The display device 01 may be a mobile phone shown in fig. 10, or may be a computer, a television, an intelligent wearable display device, and the like, which is not particularly limited in this embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A pixel circuit, comprising: the device comprises a driving module, a storage module, a light-emitting module, a data writing module, a first compensation and leakage suppression module and a second compensation and leakage suppression module;
the data writing module is used for writing data voltage into the control end of the driving module;
the storage module is connected with the control end of the driving module and used for storing the voltage of the control end of the driving module;
the driving module is used for generating driving current according to the voltage stored in the storage module and outputting the driving current from a first end to drive the light-emitting module to emit light;
a first end of the first compensation and leakage suppression module is connected with a first end of the driving module, a second end of the first compensation and leakage suppression module is connected with a first end of the second compensation and leakage suppression module, and a second end of the second compensation and leakage suppression module is connected with a control end of the driving module; the first compensation and leakage suppression module comprises at least one transistor, the transistor in the first compensation and leakage suppression module is an N-type transistor, the second compensation and leakage suppression module comprises at least one transistor, and the transistor in the second compensation and leakage suppression module is a P-type transistor.
2. The pixel circuit according to claim 1, further comprising an initialization module, a first terminal of the initialization module is connected to the first terminal of the first compensation and leakage current suppression module, a second terminal of the initialization module is connected to the first terminal of the light emitting module, and the initialization module is configured to write an initialization voltage into the control terminal of the driving module and the first terminal of the light emitting module; the initialization module comprises at least two transistors, and the transistors in the initialization module are N-type transistors.
3. The pixel circuit according to claim 2, wherein the initialization module comprises a first transistor and a second transistor, a first pole of the first transistor is connected to an initialization signal line, a second pole of the first transistor is connected to a first end of the first compensation and leakage current suppression module, and a gate of the first transistor is connected to a first scan line;
a first pole of the second transistor is connected to the initialization signal line, a second pole of the second transistor is connected to a first end of the light emitting module, and a gate of the second transistor is connected to the first scan line.
4. The pixel circuit according to claim 3, wherein the first compensation and leakage suppression module comprises a third transistor, a first pole of the third transistor is connected to the first end of the driving module, a second pole of the third transistor is connected to the first end of the second compensation and leakage suppression module, and a gate of the third transistor is connected to the second scan line.
5. The pixel circuit according to claim 4, wherein a time interval of the pulse of the signal on the first scan line is within a time interval of the pulse of the signal on the second scan line within one frame.
6. The pixel circuit according to claim 1, wherein the second compensation and leakage suppression module comprises a fourth transistor, a first pole of the fourth transistor is connected to the second terminal of the first compensation and leakage suppression module, a second pole of the fourth transistor is connected to the control terminal of the driving module, and a gate of the fourth transistor is connected to a third scan line.
7. The pixel circuit according to claim 1, further comprising a voltage stabilization module;
the voltage stabilizing module is connected between the control end of the driving module and the fourth scanning line and used for stabilizing the voltage of the control end of the driving module;
the control end of the data writing module is connected with the fourth scanning line, the first end of the data writing module is connected with the data line, and the second end of the data writing module is connected with the second end of the driving module.
8. The pixel circuit according to claim 7, further comprising a first light emission control module and a second light emission control module;
the first light-emitting control module is connected between a first power line and the second end of the driving module, the second light-emitting control module is connected between the first end of the driving module and the first end of the light-emitting module, the second end of the light-emitting module is connected with a second power line, and the control end of the first light-emitting control module and the control end of the second light-emitting control module are connected with a light-emitting control signal line.
9. The pixel circuit according to claim 8, wherein the first light emission control module includes a fifth transistor, the second light emission control module includes a sixth transistor, the driving module includes a seventh transistor, and the data writing module includes an eighth transistor;
a first pole of the fifth transistor is connected to the first power line, a second pole of the fifth transistor is connected to a first pole of the seventh transistor, a gate of the fifth transistor is connected to the light emission control signal line, a first pole of the sixth transistor is connected to a second pole of the seventh transistor, a second pole of the sixth transistor is connected to the first end of the light emitting module, a gate of the sixth transistor is connected to the light emission control signal line, and a gate of the seventh transistor is connected to the second end of the second compensation and leakage suppression module;
a first pole of the eighth transistor is connected to the data line, a second pole of the eighth transistor is connected to the first pole of the seventh transistor, and a gate of the eighth transistor is connected to the fourth scan line.
10. A display panel comprising the pixel circuit according to any one of claims 1 to 9.
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| CN202111100940.4A CN113870780A (en) | 2021-09-18 | 2021-09-18 | Pixel circuit and display panel |
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| CN202111100940.4A CN113870780A (en) | 2021-09-18 | 2021-09-18 | Pixel circuit and display panel |
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