CN113394237B

CN113394237B - Display panel, driving method thereof and display device

Info

Publication number: CN113394237B
Application number: CN202110687645.7A
Authority: CN
Inventors: 庞玉乾
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd
Priority date: 2021-06-21
Filing date: 2021-06-21
Publication date: 2022-09-06
Anticipated expiration: 2041-06-21
Also published as: CN113394237A

Abstract

The embodiment of the invention discloses a display panel, a driving method thereof and a display device. The display panel includes: the liquid crystal display comprises a substrate, and a thin film transistor, a scanning line and a data line which are positioned on the substrate; the grid electrode of the data writing transistor is connected with the first scanning line, and the grid electrode of the compensation transistor is connected with the second scanning line; the first scanning line extends along a first direction and is positioned on the first metal layer; the second scanning line comprises a first routing part and a second routing part which are arranged along the first direction, the first routing part is electrically connected with the second routing part, the first routing part is positioned on the first metal layer, the second routing part is positioned on the second metal layer, and the source/drain of the thin film transistor is positioned on the second metal layer; the second metal layer further comprises a switching part, and the active layer of the compensation transistor and the active layer of the driving transistor are electrically connected through the switching part. The technical scheme of the embodiment of the invention is beneficial to avoiding the influence on the work of the pixel circuit caused by the formation of redundant thin film transistors in the display panel.

Description

Display panel, driving method thereof and display device

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.

Background

With the continuous maturity of display technology, the demand of users for refresh rate of display screens is increasing. The existing display panel has more film layer structures, and a redundant structure is easily generated to influence the work of a pixel circuit, thereby influencing the display effect.

Disclosure of Invention

Embodiments of the present invention provide a display panel, a driving method thereof and a display device, so as to prevent a pixel circuit from being affected by the formation of redundant thin film transistors in the display panel.

In a first aspect, an embodiment of the present invention provides a display panel, including:

a substrate;

the thin film transistor, the scanning line and the data line are positioned on the substrate;

the thin film transistor comprises a data writing transistor, a driving transistor and a compensating transistor, wherein the data writing transistor is used for writing a data voltage on the data line into a grid electrode of the driving transistor, and the compensating transistor is used for compensating a threshold voltage of the driving transistor; the scanning lines comprise a first scanning line and a second scanning line, the grid electrode of the data writing transistor is connected with the first scanning line, and the grid electrode of the compensation transistor is connected with the second scanning line;

the first scanning line extends along a first direction and is positioned on the first metal layer; the second scanning line comprises a first routing part and a second routing part which are arranged along the first direction, the first routing part is electrically connected with the second routing part, the first routing part is positioned on the first metal layer, the second routing part is positioned on the second metal layer, and the source/drain of the thin film transistor is positioned on the second metal layer; the second metal layer further comprises a switching part, and the active layer of the compensation transistor and the active layer of the driving transistor are electrically connected through the switching part.

Optionally, the active layer of the driving transistor is located on one side of the first scan line, and the active layer of the compensation transistor and the second scan line are both located on the other side of the first scan line.

Optionally, the data writing transistor is connected between the data line and the driving transistor, and a width of the active layer on a side where the data writing transistor is connected to the driving transistor is larger than a width of the active layer on a side where the data writing transistor is connected to the data line.

Optionally, the storage capacitor further includes a first plate of the storage capacitor located in the first metal layer, a second plate of the storage capacitor located in a third metal layer, and the third metal layer located between the first metal layer and the second metal layer;

and the vertical projection of the second polar plate of the storage capacitor on the substrate covers the vertical projection of the active layer on one side of the data writing transistor, which is connected with the driving transistor, on the substrate.

Optionally, the display panel further includes a power line, where the power line includes a third routing portion and a fourth routing portion arranged along a second direction, the second direction intersects with the first direction, and the third routing portion is electrically connected to the fourth routing portion;

the third routing portion is located on the second metal layer, and the third routing portion is separated from the second routing portion of the second scanning line; the fourth routing part is located on a fourth metal layer, and the fourth metal layer is located on one side, far away from the substrate, of the second metal layer.

Optionally, the data line extends along the second direction, and the data line is located in the fourth metal layer.

Optionally, the display panel includes i rows of pixel circuits and i stages of cascade-connected scanning circuits;

a scanning signal output terminal of the scanning circuit of the nth stage is connected to the first scanning line to which the data writing transistor in the pixel circuit of the nth row is connected, and a scanning signal output terminal of the scanning circuit of the (n + 2) (k-1) th stage is connected to the second scanning line to which the compensation transistor in the pixel circuit of the nth row is connected; wherein k is the pulse number of the scanning signals on the first scanning line and the second scanning line in one frame, i, n and k are integers, k is more than 1, and n +2(k-1) is less than or equal to i.

Optionally, the display panel includes i rows of pixel circuits, i stages of cascade-connected first scanning circuits, and i stages of cascade-connected second scanning circuits;

a scanning signal output terminal of the first scanning circuit of the nth stage is connected to the first scanning line to which the data writing transistor in the pixel circuit of the nth row is connected, and a scanning signal output terminal of the second scanning circuit of the nth stage is connected to the second scanning line to which the compensation transistor in the pixel circuit of the nth row is connected; wherein i and n are integers, and n is less than or equal to i.

In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, where the display panel includes:

a substrate;

the first scanning line extends along a first direction and is positioned on the first metal layer; the second scanning line comprises a first routing part and a second routing part which are arranged along the first direction, the first routing part is electrically connected with the second routing part, the first routing part is positioned on the first metal layer, the second routing part is positioned on the second metal layer, and the source/drain of the thin film transistor is positioned on the second metal layer; the second metal layer further comprises a switching part, and an active layer of the compensation transistor and an active layer of the driving transistor are electrically connected through the switching part;

the driving method of the display panel includes:

applying a first scanning signal to the first scanning line and applying a second scanning signal to the second scanning line; the conducting level signal of the first scanning signal is overlapped with the conducting level signal of the second scanning signal, and the starting time of the conducting level signal of the second scanning signal is later than that of the conducting level signal of the first scanning signal.

In a third aspect, an embodiment of the present invention further provides a display device, including the display panel described in the first aspect.

According to the display panel, the driving method thereof and the display device provided by the embodiment of the invention, the gate of the data writing transistor is connected with the first scanning line, the gate of the compensation transistor is connected with the second scanning line, the first wire routing part of the second scanning line is electrically connected with the second wire routing part, the first wire routing part is positioned on the first metal layer, and the second wire routing part is positioned on the second metal layer, so that the second scanning line and active layers of other areas except the active layer of the compensation transistor are prevented from being overlapped to form redundant thin film transistors to influence the work of a pixel circuit; the active layer of the compensation transistor and the active layer of the driving transistor are electrically connected through the switching part in the second metal layer, so that the phenomenon that the redundant thin film transistor is formed by overlapping the area where the compensation transistor and the active layer of the driving transistor are electrically connected with the scanning line in the first metal layer to influence the work of a pixel circuit is avoided; in addition, the on and off of the data writing transistor and the compensation transistor can be controlled by different scanning signals respectively, when the on time periods of the data writing transistor and the compensation transistor are controlled to be overlapped and the on time of the compensation transistor is later than that of the data writing transistor, the scheme can control the compensation transistor to be continuously switched on after the data writing transistor is controlled to be switched off in the data writing stage, so that the data voltage is continuously written into the grid electrode and the storage capacitor of the driving transistor through the driving transistor and the compensation transistor, and the charging time of the pixel circuit is prolonged, and the display effect is improved.

Drawings

Fig. 1 is a top view of a display panel according to an embodiment of the present invention;

fig. 2 is a cross-sectional view of a display panel according to an embodiment of the present invention;

fig. 3 is a cross-sectional view of another display panel provided in an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 5 is a cross-sectional view of another display panel provided in an embodiment of the present invention;

fig. 6 is a cross-sectional view of another display panel provided in an embodiment of the present invention;

FIG. 7 is a schematic diagram of another display panel according to an embodiment of the present invention;

FIG. 8 is a timing diagram of a driving method according to an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 10 is a flowchart illustrating a driving method of a display panel according to an embodiment of the invention;

fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As described in the background art, the conventional display panel has a plurality of film structures, and a redundant structure is easily generated. The inventor researches and finds that the reason for the problems is that: the display panel comprises a pixel circuit, the pixel circuit is composed of a thin film transistor and a capacitor, and a signal line in the pixel circuit, an active layer and a source/drain electrode of the thin film transistor and a polar plate of the capacitor are positioned in a plurality of film layers of the display panel, so that the structure in each film layer of the display panel is more, redundant structures are easily formed in different structures, for example, redundant thin film transistors can be formed by the active layer and a metal layer, and the work of the pixel circuit is influenced, and the display effect is influenced.

In view of the foregoing problems, embodiments of the present invention provide a display panel. Fig. 1 is a top view of a display panel according to an embodiment of the present invention, which only shows a part of pixel circuits in the display panel and active layers and metal layers constituting the pixel circuits; fig. 2 is a cross-sectional view of a display panel according to an embodiment of the present invention, which may be a cross-sectional schematic view of the display panel shown in fig. 1 cut along a cross-sectional line AA'; fig. 3 is a cross-sectional view of another display panel provided in an embodiment of the present invention, which may be specifically a cross-sectional schematic view obtained by cutting the display panel shown in fig. 1 along a cross-sectional line BB'; fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. With reference to fig. 1 to 4, the display panel includes:

a substrate 10;

a thin film transistor, a scan line and a data line DL on the substrate 10;

the thin film transistor comprises a data writing transistor T1, a driving transistor DT and a compensating transistor T2, wherein the data writing transistor T1 is used for writing a data voltage Vdata on the data line DL into the grid electrode of the driving transistor DT, and the compensating transistor T2 is used for compensating the threshold voltage of the driving transistor DT; the scanning lines comprise a first scanning line S1 and a second scanning line S2, the gate of the data writing transistor T1 is connected with the first scanning line S1, and the gate of the compensation transistor T2 is connected with the second scanning line S2;

the first scan line S1 extends along the first direction X and is located on the first metal layer 30; the second scan line S2 includes a first wire trace portion S21 and a second wire trace portion S22 arranged along the first direction X, the first wire trace portion S21 and the second wire trace portion S22 are electrically connected, the first wire trace portion S21 is located on the first metal layer 30, the second wire trace portion S22 is located on the second metal layer 40, and a source/drain of the thin film transistor is located on the second metal layer 40; the second metal layer 40 further includes a transfer portion 410, and the active layer of the compensation transistor T2 and the active layer of the driving transistor DT are electrically connected through the transfer portion 410.

Specifically, the substrate 10 may provide cushioning, protection, or support for the display panel. The substrate 10 may be a flexible substrate, and the material of the flexible substrate may be Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like, or may be a mixture of these materials. The substrate 10 may be a hard substrate formed of glass or the like.

The display panel comprises a pixel circuit composed of a thin film transistor and a storage capacitor, the pixel circuit is connected with a light-emitting device, a scanning line and a data line DL, the scanning line is used for transmitting scanning signals to the pixel circuit, the data line DL is used for transmitting data voltages to the pixel circuit, and the pixel circuit can control the light-emitting device to perform light-emitting display according to the received data voltages under the control of the scanning signals. Exemplarily, fig. 4 shows a case where the pixel circuit includes seven thin film transistors and one storage capacitor, and the pixel circuit specifically includes a driving transistor DT, a data writing transistor T1, a compensating transistor T2, a first initializing transistor T3, a second initializing transistor T4, a first light emission controlling transistor T5, a second light emission controlling transistor T6, and a storage capacitor Cst. The data writing transistor T1 is connected between the data line DL and the first source/drain of the driving transistor DT, the compensating transistor T2 is connected between the second source/drain of the driving transistor DT and the gate, one of the first source/drain and the second source/drain is a source, and the other is a drain.

Referring to fig. 4, the operation process of the pixel circuit at least includes: an initialization phase, a data writing phase and a light emitting phase. In the initialization stage, the first initialization transistor T3 is used to write an initialization signal Vref to the gate of the driving transistor DT to initialize the gate potential of the driving transistor DT, and the second initialization transistor T4 is used to write the initialization signal Vref to the first pole (e.g., the first pole is an anode) of the light emitting device D1 to initialize the potential of the first pole of the light emitting device D1; in the data writing phase, the data writing transistor T1 is turned on in response to the first Scan signal Scan1 on the first Scan line S1, the compensation transistor T2 is turned on in response to the second Scan signal Scan2 on the second Scan line S2 to write the data voltage Vdata on the data line DL to the gate of the driving transistor DT and the storage capacitor Cst through the data writing transistor T1, the driving transistor DT and the compensation transistor T2, and the compensation transistor T2 can also compensate for the threshold voltage of the driving transistor DT; in the light emitting phase, the first light emitting control transistor T5 and the second light emitting control transistor T6 are both turned on, the first power signal VDD is written into the first source/drain of the driving transistor DT, the second power signal VSS is written into the second pole of the light emitting device D1, and the driving transistor DT drives the light emitting device D1 to perform light emitting display with corresponding brightness according to the data voltage Vdata stored in the storage capacitor Cst.

The gate of the thin film transistor may be located on the first metal layer 30, the first Scan line S1 overlaps with a vertical projection of the active layer of the data writing transistor T1 on the substrate 10, and the first Scan signal Scan1 writes the gate of the data writing transistor T1 through the first Scan line S1. The first wire trace portion S21 of the second Scan line S2 is located on the first metal layer 30, the second wire trace portion S22 is located on the second metal layer 40, the first wire trace portion S21 and the second wire trace portion S22 can be electrically connected through a via, and the second Scan signal Scan2 is written to the gate of the compensation transistor T2 sequentially through the second wire trace portion S22 and the first wire trace portion S21. In this way, the first wire trace portion S21 may be disposed to overlap a vertical projection of the active layer of the compensation transistor T2 on the substrate 10, and the first wire trace portion S21 may not overlap a vertical projection of the active layer of another region except the active layer of the compensation transistor T2 on the substrate 10, so as to help prevent the first wire trace portion S21 from overlapping the active layer 20 of another region to form an excessive thin film transistor, so as to prevent the excessive thin film transistor from affecting the operation of the pixel circuit. In addition, the second wire trace portion S22 is located on the second metal layer 40, and even if the second wire trace portion S22 overlaps with the active layer 20 in other regions, the second metal layer 40 and the active layer 20 are at least separated by the first metal layer 30, which helps to prevent the second wire trace portion S22 from overlapping with the active layer 20 in other regions to form an unnecessary thin film transistor.

The active layer 20 of the thin film transistor includes an active layer 210 of a compensation transistor T2 and an active layer 220 of a driving transistor DT, an area E where the active layer 210 of the compensation transistor T2 is located and an area F where the active layer 220 of the driving transistor DT is located are schematically marked in fig. 1, and the active layer 210 of the compensation transistor T2 and the active layer 220 of the driving transistor DT are schematically marked in fig. 3, and in conjunction with fig. 1 to 4, the transition portion 410 may be electrically connected to the active layer 210 of the compensation transistor T2 and the active layer 220 of the driving transistor DT through a via hole, respectively, so that there is an advantage in that an area where the active layer of the compensation transistor T2 and the active layer of the driving transistor DT are electrically connected is prevented from overlapping with a scan line in the first metal layer 30 to form an unnecessary thin film transistor, so that the unnecessary thin film transistor does not affect the operation of the pixel circuit.

In the prior art, the data writing transistor and the compensation transistor are usually controlled by the same scanning signal, so that the data writing transistor and the compensation transistor are turned on and off simultaneously in the data writing phase. Compared with the prior art, the scheme has the advantages that the gate of the data writing transistor T1 is connected with the first scanning line S1, the gate of the compensation transistor T2 is connected with the second scanning line S2, and the on or off of the data writing transistor T1 and the compensation transistor T2 can be controlled by different scanning signals respectively. Exemplarily, a first Scan signal Scan1 is applied to the first Scan line S1, and a second Scan signal Scan2 is applied to the second Scan line S2; the turn-on level signal of the first Scan signal Scan1 overlaps the turn-on level signal of the second Scan signal Scan2, and the start time of the turn-on level signal of the second Scan signal Scan2 is later than the start time of the turn-on level signal of the first Scan signal Scan 1. Taking the data writing transistor T1 and the compensating transistor T2 as P-channel transistors as an example, the on level signals of the first Scan signal Scan1 and the second Scan signal Scan2 are both low level signals that control the transistors to be on. The turn-on level signal of the first Scan signal Scan1 overlaps the turn-on level signal of the second Scan signal Scan2 so that the turn-on periods of the data write transistor T1 and the compensation transistor T2 overlap, and the turn-on level signal of the second Scan signal Scan2 starts at a timing later than the start timing of the turn-on level signal of the first Scan signal Scan1 so that the turn-on timing of the compensation transistor T2 is later than the turn-on timing of the data write transistor T1. Thus, in the data writing phase, the data writing transistor T1 is turned on earlier than the compensation transistor T2, when the compensation transistor T2 is turned on, the data voltage Vdata on the data line DL is written into the gate electrode of the driving transistor DT and the storage capacitor Cst through the turned-on data writing transistor T1 and the compensation transistor T2, and when the data writing transistor T1 is turned off, the compensation transistor T2 is still turned on, and the data voltage Vdata can be continuously written into the gate electrode of the driving transistor DT and the storage capacitor Cst through the driving transistor DT and the compensation transistor T2 to charge the gate electrode of the driving transistor DT and the storage capacitor Cst, thereby extending the charging time of the pixel circuit.

According to the technical scheme, the gate of the data writing transistor is connected with the first scanning line, the gate of the compensation transistor is connected with the second scanning line, the first routing part and the second routing part of the second scanning line are electrically connected, the first routing part is located on the first metal layer, and the second routing part is located on the second metal layer, so that the situation that the second scanning line and active layers of other areas except the active layer of the compensation transistor are overlapped to form redundant thin film transistors to influence the work of a pixel circuit is avoided; the active layer of the compensation transistor and the active layer of the driving transistor are electrically connected through the switching part in the second metal layer, so that the phenomenon that the redundant thin film transistor is formed by overlapping the area where the compensation transistor and the active layer of the driving transistor are electrically connected with the scanning line in the first metal layer to influence the work of a pixel circuit is avoided; in addition, the on and off of the data writing transistor and the compensation transistor can be controlled by different scanning signals respectively, when the on time periods of the data writing transistor and the compensation transistor are controlled to be overlapped and the on time of the compensation transistor is later than that of the data writing transistor, the scheme can control the compensation transistor to be continuously switched on after the data writing transistor is controlled to be switched off in the data writing stage, so that the data voltage is continuously written into the grid electrode and the storage capacitor of the driving transistor through the driving transistor and the compensation transistor, and the charging time of the pixel circuit is prolonged, and the display effect is improved.

With reference to fig. 1 to 4, on the basis of the above scheme, optionally, the active layer of the driving transistor DT is located on one side of the first scan line S1, and the active layer of the compensation transistor T2 and the second scan line S2 are both located on the other side of the first scan line S1. Specifically, the second scan line S2 is located on the other side of the first scan line S1, so that there is no overlap between the first scan line S1 and the second scan line S2, the active layer 220 of the driving transistor DT and the active layer 210 of the compensation transistor T2 are respectively located on both sides of the first scan line S1, and the active layer 210 of the compensation transistor T2 and the active layer 220 of the driving transistor DT are electrically connected through the junction 410, so that there is no overlap between the active layer 210 of the compensation transistor T2 and the first scan line S1, and there is no overlap between the active layer of the compensation transistor T2 and the active layer of the driving transistor DT electrical connection region and the first scan line S1, which helps to prevent the active layer of the compensation transistor T2 and the driving transistor DT electrical connection region and the first scan line S1 from overlapping to form an unnecessary thin film transistor and thus affecting the operation of the pixel circuit. In the prior art, the gates of the data writing transistor and the compensating transistor are connected to the same scan line, the scan line overlaps with the active layers of the data writing transistor and the compensation transistor, and the active layers of the compensation transistor and the driving transistor are directly electrically connected, therefore, the active layer of the compensation transistor is distributed on both sides of the scan line, and compared with the prior art, the present solution, by disposing the active layer of the driving transistor DT on one side of the first scan line S1 and the active layer of the compensation transistor T2 and the second scan line S2 on the other side of the first scan line S1, on one hand, helps to control the on and off of the data writing transistor and the compensation transistor by using the scan signals on different scan lines, the charging time of the pixel circuit is prolonged, and on the other hand, the influence on the operation of the pixel circuit caused by the redundant thin film transistor formed by the overlapping of the active layer of the electric connection area of the compensation transistor and the driving transistor and the first scanning line is avoided.

Fig. 5 is a cross-sectional view of another display panel according to an embodiment of the present invention, which may be a cross-sectional schematic view of the display panel shown in fig. 1, which is cut along a cross-sectional line HH'. Referring to fig. 1 to 5, optionally, the data writing transistor T1 is connected between the data line DL and the driving transistor DT, and the width of the active layer on the side where the data writing transistor T1 is connected to the driving transistor DT is greater than the width of the active layer on the side where the data writing transistor T1 is connected to the data line DL.

For example, fig. 1 shows a region G where the data writing transistor T1 is connected to the active layer on the driving transistor DT side, fig. 2 shows an active layer 240 on the data line DL side and its width W2 of the data writing transistor T1, fig. 5 shows an active layer 230 on the driving transistor DT side and its width W1 of the data writing transistor T1, and W1 > W2. In the related art, the width of the active layer of the data writing transistor (the width in the first direction X in fig. 1) is generally equal everywhere. Compared with the prior art, the width W1 of the active layer 230 on the side where the data writing transistor T1 is connected with the driving transistor DT is set to be larger than the width W2 of the active layer 240 on the side where the data writing transistor T1 is connected with the data line DL, which is equivalent to increasing the width of the active layer 230 on the side where the data writing transistor T1 is connected with the driving transistor DT, so that the resistance of the active layer 230 on the side where the data writing transistor T1 is connected with the driving transistor DT is reduced, that is, the resistance of the source/drain region on the side where the data writing transistor T1 is connected with the driving transistor DT is reduced, and the data writing transistor T1 is favorable for writing the data voltage Vdata to the gate and the storage capacitor of the driving transistor DT, thereby improving the charging effect of the pixel circuit and improving the display effect.

On the basis of the above scheme, optionally, the display panel further includes a storage capacitor Cst, wherein the first plate C1 of the storage capacitor Cst is located on the first metal layer 30, the second plate C2 of the storage capacitor Cst is located on the third metal layer 50, and the third metal layer 50 is located between the first metal layer 30 and the second metal layer 40; the vertical projection of the second plate C2 of the storage capacitor Cst on the substrate 10 is the vertical projection of the active layer 230 on the substrate 10 covering the side of the data writing transistor T1 connected to the driving transistor DT.

Specifically, the first plate C1 of the storage capacitor Cst is a plate connected to the gate of the driving transistor DT, the second plate C2 is a plate connected to the first power signal VDD, and the vertical projection of the second plate C2 on the substrate 10 covers the vertical projection of the active layer 230 of the data writing transistor T1 connected to the driving transistor DT on the substrate 10, so as to help shield the active layer 230 of the data writing transistor T1 connected to the driving transistor DT by the second plate C2 of the storage capacitor Cst, and since the third metal layer 50 further includes the second metal layer 40 and other metal layers, which are provided with signal lines, and the second plate C2 is provided to help shield the active layer 230 of the data writing transistor T1 connected to the driving transistor DT, so as to prevent the potential jump of the signal lines in the second metal layer 40 and other metal layers from affecting the active layer 230 of the data writing transistor T1 connected to the driving transistor DT The potential, thereby affecting the charging effect of the pixel circuit. In addition, by disposing the second plate C2 to vertically project on the substrate 10, the vertical projection of the active layer 230 on the substrate 10 covering the side where the data writing transistor T1 is connected to the driving transistor DT is equivalent to increasing the second plate C2 of the storage capacitor Cst, which is helpful to improve the charging effect of the pixel circuit.

Fig. 6 is a cross-sectional view of another display panel according to an embodiment of the present invention, which may be a cross-sectional schematic view of the display panel shown in fig. 1, which is cut along a cross-sectional line JJ'. With reference to fig. 1 to 6, optionally, the display panel further includes a power supply line including a third wire running portion L1 and a fourth wire running portion L2 arranged along a second direction Y, the second direction Y intersecting the first direction X, the third wire running portion L1 and the fourth wire running portion L2 being electrically connected; the third wire trace portion L1 is located on the second metal layer 40, and the third wire trace portion L1 is disposed apart from the second wire trace portion S22 of the second scan line S2; the fourth wire trace portion L2 is located on the fourth metal layer 60, and the fourth metal layer 60 is located on a side of the second metal layer 40 away from the substrate 10.

Illustratively, the power line may be a signal line transmitting the first power signal VDD to the pixel circuit, the first metal layer 30, the third metal layer 50, the second metal layer 40, and the fourth metal layer 60 are sequentially disposed on a side of the active layer 20 away from the substrate 10, the third wire trace portion L1 of the power line is located on the second metal layer 40, the fourth wire trace portion L2 is located on the fourth metal layer 60, vertical projections of the third wire trace portion L1 and the fourth wire trace portion L2 on the substrate 10 overlap, the third wire trace portion L1 and the fourth wire trace portion L2 are electrically connected through a via, and the third wire trace portion L1 of the power line is disposed apart from the second wire trace portion S22 of the second scan line S2. Compared with the scheme that the power line is directly arranged on the second metal layer 40, the scheme helps to prevent the power line in the second metal layer 40 from influencing the wiring of the second scan line S2, and by arranging the third wire portion L1 and the fourth wire portion L2 to be electrically connected, the scheme also helps to reduce the resistance of the power line, so that the voltage Drop (IR Drop) generated on the power line by the first power signal VDD is reduced, and the display effect is improved.

On the basis of the above scheme, optionally, the data line DL is disposed to extend along the second direction Y, and the data line DL is located in the fourth metal layer 60. Specifically, the data line DL is located in the fourth metal layer 60, and the data line DL is disposed separately from the fourth wire portion L2 of the power line, which helps to avoid the data line DL from affecting the wiring of the second scan line S2 by using the wiring space of the fourth metal layer 60, compared to the scheme in which the data line DL is disposed in the second metal layer 40.

Fig. 7 is a schematic structural diagram of another display panel provided in an embodiment of the present invention, and in conjunction with fig. 4 and fig. 7, on the basis of the foregoing solutions, optionally, the display panel includes i rows of pixel circuits 100 and i stages of scanning circuits 200 connected in cascade; a scanning signal output terminal of the nth stage scanning circuit 200 is connected to the first scanning line S1 to which the data writing transistor T1 in the nth row pixel circuit 100 is connected, and a scanning signal output terminal of the (n + 2) (k-1) th stage scanning circuit 200 is connected to the second scanning line S2 to which the compensation transistor T2 in the nth row pixel circuit 100 is connected; wherein k is the pulse number of the scanning signals on the first scanning line S1 and the second scanning line S2 in one frame, i, n and k are integers, and n +2(k-1) is less than or equal to i.

Specifically, the scan circuit 200 includes an input terminal and a scan signal output terminal, and the scan circuit 200 is configured to shift and output a signal at the input terminal through the scan signal output terminal, and transmit a scan signal to a corresponding pixel circuit row through a scan line connected to the scan signal output terminal. The driving chip 300 in the display device is connected to the data lines DL for transmitting data voltages to the data lines DL. The input end of the 1 st scanning circuit 200 is connected to the start signal IN, the scanning signal output end of the previous scanning circuit 200 is connected to the input end of the next scanning circuit 200, and the scanning signal output by the previous scanning circuit 200 is used as the input signal of the next scanning circuit 200, so that the start signal IN is output by shifting the scanning circuits 200 IN stages and is used as the scanning signal of the pixel circuits 100 IN each row. The Scan signal output terminal of the nth stage Scan circuit 200 is connected to the first Scan line S1 to which the data write transistor T1 in the nth row of pixel circuits 100 is connected, for supplying the first Scan signal Scan1 to the gate of the data write transistor T1 in the nth row of pixel circuits 100, and the Scan signal output terminal of the (n + 2) (k-1) th stage Scan circuit 200 is connected to the second Scan line S2 to which the compensation transistor T2 in the nth row of pixel circuits 100 is connected, for supplying the second Scan signal Scan2 to the gate of the compensation transistor T2 in the nth row of pixel circuits 100.

The number of pulses of the first Scan signal Scan1 and the second Scan signal Scan2 received by each row of pixel circuits in one frame is k, that is, the first Scan signal Scan1 and the second Scan signal Scan2 received by each row of pixel circuits in one frame each include signals in which an on level signal (i.e., a signal for controlling the transistor to be turned on) and an off level signal (i.e., a signal for controlling the transistor to be turned off) are alternated, and the number of the on level signals is k. Illustratively, taking as an example that the pulse widths of the on-level signal and the off-level signal in the Scan signals are equal, and each stage of the Scan circuit 200 shifts the timing of the input signal by one pulse signal, when k is 2, the first Scan signal Scan1 and the second Scan signal Scan2 each include 2 pulse signals, then the first Scan signal Scan1 of the pixel circuit 100 in the nth row is provided by the nth stage Scan circuit 200, the second Scan signal Scan2 is provided by the n +2 th stage Scan circuit 200, the second Scan signal Scan2 is shifted by 2 pulse signal timings (corresponding to the timing of one on-level signal and one off-level signal) with respect to the first Scan signal Scan1, and the second on-level signal of the first Scan signal Scan1 overlaps the timing of the first on-level signal of the second Scan signal Scan 2. Similarly, when k is equal to 3, the first Scan signal Scan1 and the second Scan signal Scan2 both include 3 pulse signals, the first Scan signal Scan1 of the pixel circuit 100 in the nth row is provided by the nth stage Scan circuit 200, the second Scan signal Scan2 is provided by the (n + 4) th stage Scan circuit 200, the second Scan signal Scan2 is shifted backward by 4 pulse signals with respect to the first Scan signal Scan1, and the third turn-on level signal of the first Scan signal Scan1 overlaps with the first turn-on level signal of the second Scan signal Scan 2. By analogy, schemes corresponding to different values of k can be determined. This arrangement has the advantage that the timing of the second Scan signal Scan2 corresponding to each row of pixel circuits 100 lags behind the timing of the first Scan signal Scan1, and the last turn-on level signal of the first Scan signal Scan1 overlaps the timing of the first turn-on level signal of the second Scan signal Scan2, and the compensation transistor T2 turns on later than the data writing transistor T1 in the data writing phase of each row of pixel circuits, and the compensation transistor T2 remains on when the data writing transistor T1 turns off, so that the data voltage Vdata can continue to be written into the gate of the driving transistor DT and the storage capacitor Cst via the driving transistor DT and the compensation transistor T2 to charge the gate of the driving transistor DT and the storage capacitor Cst, thereby prolonging the charging time of the pixel circuits.

Fig. 7 schematically shows the first 6 rows of pixel circuits 100 and the first 6 stages of scanning circuits 200 in the display panel, and illustratively, when k is 3, the scanning signal output terminal of the 5 th stage of scanning circuit 200 is connected to the second scanning line S2 to which the compensation transistor T2 in the 1 st row of pixel circuits 100 is connected, the scanning signal output terminal of the 6 th stage of scanning circuit 200 is connected to the second scanning line S2 to which the compensation transistor T2 in the 2 nd row of pixel circuits 100 is connected, and so on, the scanning signal output terminal of the n +4 th stage of scanning circuit 200 is connected to the second scanning line S2 to which the compensation transistor T2 in the n th row of pixel circuits 100 is connected. Fig. 8 is a driving timing chart according to an embodiment of the present invention, which can be used to control the operation of the pixel circuit shown in fig. 4. For example, referring to fig. 1, fig. 4, fig. 7 and fig. 8, still taking an example that k is 3, that is, the scan signals for controlling the data writing transistor T1, the compensating transistor T2, the first initializing transistor T3 and the second initializing transistor T4 in one frame all include three pulse signals, and each stage of the scan circuit 200 shifts the timing of the input signal by one pulse signal. Optionally, the display panel further includes a third Scan line S3/4, the Scan signal output terminal of the m-th Scan circuit 200 is further connected to the third Scan line S3/4 corresponding to the m-th row of pixel circuits 100, the gate of the second initialization transistor T4 in the m-th row of pixel circuits 100 is connected to the third Scan line S3/4 corresponding to the row of pixel circuits 100, the gate of the first initialization transistor T3 is connected to the third Scan line S3/4 corresponding to the m-1-th row of pixel circuits 100, where m ≦ i, the gate of the second initialization transistor T4 in the previous row of pixel circuits 100 is connected to the fourth Scan signal Scan4, the timing is the same as the timing of the gate of the third Scan signal Scan3 connected to the gate of the first initialization transistor T3 in the next row of pixel circuits 100, the gate of the first initialization transistor T3 in the first row of pixel circuits 100 is directly connected to the third Scan signal Scan line 3, and the gate-on first Scan signal Scan1 of the data write transistor T1 in each row of pixel circuits 100 is in the same timing as the gate-on fourth Scan signal Scan4 of the second initialization transistor T4.

Illustratively, the operation phase of each row of pixel circuits includes at least: a first initialization phase t0, a second initialization phase t1, a data writing phase t2 and a light emitting phase.

In the first initialization phase T0, the first initialization transistor T3 is turned on in response to a low level signal in the third Scan signal Scan3, and writes the initialization signal Vref to the gate of the driving transistor DT when turned on, initializing the gate potential of the driving transistor DT.

In the second initialization period T1, the second initialization transistor T4 is turned on in response to a low level signal in the fourth Scan signal Scan4, and writes the initialization signal Vref to the first pole of the light emitting device D1 when turned on, initializing the potential of the first pole of the light emitting device D1.

In the data writing phase T2, the data writing transistor T1 is turned on in response to a low level signal in the first Scan signal Scan1, and transmits the data voltage Vdata on the data line DL to the driving transistor DT when turned on. The nth stage Scan circuit 200 supplies the first Scan signal Scan1 to the gate of the data write transistor T1 in the nth row pixel circuit 100, and the n +4 th stage Scan circuit 200 supplies the second Scan signal Scan2 to the gate of the compensation transistor T2 in the nth row pixel circuit 100, so that the timing of the second Scan signal Scan2 is shifted back by the timing of four low-level signals as compared to the first Scan signal Scan 1. When the first Scan signal Scan1 changes from a high level signal to a third low level signal, the second Scan signal Scan2 changes from a high level signal to a low level signal, the data writing transistor T1 and the compensation transistor T2 are both turned on, and the data voltage Vdata on the data line DL is written into the gate of the driving transistor DT and the storage capacitor Cst through the data writing transistor T1, the driving transistor DT and the compensation transistor T2. After the third low level signal of the first Scan signal Scan1 is finished, the data writing transistor T1 is turned off, the compensation transistor T2 can still be turned on in response to the last two low level signals of the second Scan signal Scan2, and the data voltage Vdata can continue to be written into the gate electrode of the driving transistor DT and the storage capacitor Cst through the driving transistor DT and the compensation transistor T2 to charge the gate electrode of the driving transistor DT and the storage capacitor Cst, thereby prolonging the charging time of the pixel circuit.

In the period corresponding to the first two low level signals of the first Scan signal Scan1, the data voltage on the data line DL may be the data voltage corresponding to the first two rows of pixel circuits, and in this stage, the compensation transistor T2 is turned off, so that the data voltage is not written into the gate of the driving transistor DT and the storage capacitor Cst of the pixel circuit in this row. The first initialization phase t0 of the pixel circuits in the row is completed before the first Scan signal Scan1 changes from the high-level signal to the third low-level signal, the gate potential of the driving transistor DT is initialized, and the data line DL starts to write the data voltage of the pixel circuits in the row when the first Scan signal Scan1 changes from the high-level signal to the third low-level signal.

In the light emitting phase, the first light emitting control transistor T5 and the second light emitting control transistor T6 are both turned on, the first power signal VDD is written into the first source/drain of the driving transistor DT, the second power signal VSS is written into the second pole of the light emitting device D1, and the driving transistor DT drives the light emitting device D1 to perform light emitting display with corresponding brightness according to the data voltage Vdata stored in the storage capacitor Cst.

It should be noted that, the above embodiment is only schematically illustrated by taking k as an example of 3, and in practical applications, the number of on level signals in the scanning signals of each frame may be set according to practical situations, and accordingly, the scanning circuit that provides the second scanning signal to each row of pixel circuits may be determined, which is not limited in this embodiment of the present invention.

Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and in combination with fig. 4 and fig. 9, on the basis of the foregoing solutions, optionally, the display panel includes i rows of pixel circuits 100, i stages of cascade-connected first scan circuits 400, and i stages of cascade-connected second scan circuits 500; a scanning signal output terminal of the nth stage first scanning circuit 400 is connected to the first scanning line S1 to which the data writing transistor T1 in the nth row pixel circuit 100 is connected, and a scanning signal output terminal of the nth stage second scanning circuit 500 is connected to the second scanning line S2 to which the compensation transistor T2 in the nth row pixel circuit 100 is connected; wherein i and n are integers, and n is less than or equal to i.

Specifically, the input terminal of the 1 st stage first scan circuit 400 is connected to the first start signal IN1, the scan signal output terminal of the previous stage first scan circuit 400 is connected to the input terminal of the next stage first scan circuit 400, and the scan signal output by the previous stage first scan circuit 400 is used as the input signal of the next stage first scan circuit 400, so that the first start signal IN1 is output by shifting the stages of the first scan circuits 400 one by one as the scan signal of each row of pixel circuits 100. The Scan signal output terminal of the nth stage first Scan circuit 400 is connected to the first Scan line S1 to which the data write transistor T1 in the nth row of pixel circuits 100 is connected, and is used to supply the first Scan signal Scan1 to the gate of the data write transistor T1 in the nth row of pixel circuits 100. The input end of the 1 st-stage second scanning circuit 500 is connected to the second start signal IN2, the scanning signal output end of the previous-stage second scanning circuit 500 is connected to the input end of the next-stage second scanning circuit 500, and the scanning signal output by the previous-stage second scanning circuit 500 is used as the input signal of the next-stage second scanning circuit 500, so that the second start signal IN2 is output by shifting the stages of the second scanning circuits 500, and is used as the scanning signal of each row of pixel circuits 100. The Scan signal output terminal of the nth stage second Scan circuit 500 is connected to the second Scan line S2 to which the compensation transistor T2 in the nth row pixel circuit 100 is connected, for supplying the second Scan signal Scan2 to the gate of the compensation transistor T2 in the nth row pixel circuit 100.

This scheme allows the first Scan circuit 400 to supply the first Scan signal Scan1 to the gate of the data write transistor T1 in the pixel circuit 100, and the second Scan circuit 500 to supply the second Scan signal Scan2 to the gate of the compensation transistor T2 in the pixel circuit 100, so that the first Scan signal Scan1 and the second Scan signal Scan2 can be supplied by different Scan circuits, respectively, and thus the timings of the on-level signals in the first Scan signal Scan1 and the second Scan signal Scan2 can be flexibly set to control the turn-on and turn-off of the data write transistor T1 and the compensation transistor T2, respectively. The turn-on level signal of the first Scan signal Scan1 overlaps the turn-on level signal of the second Scan signal Scan2, and the start time of the turn-on level signal of the second Scan signal Scan2 is later than the start time of the turn-on level signal of the first Scan signal Scan 1. Taking the data writing transistor T1 and the compensating transistor T2 as P-channel transistors as an example, the on level signals of the first Scan signal Scan1 and the second Scan signal Scan2 are both low level signals that control the transistors to be on. The turn-on level signal of the first Scan signal Scan1 overlaps the turn-on level signal of the second Scan signal Scan2 so that the turn-on periods of the data write transistor T1 and the compensation transistor T2 overlap, and the turn-on level signal of the second Scan signal Scan2 starts at a timing later than the start timing of the turn-on level signal of the first Scan signal Scan1 so that the turn-on timing of the compensation transistor T2 is later than the turn-on timing of the data write transistor T1. In the data writing phase, the on-level signal of the first Scan signal Scan1 overlaps the on-level signal of the second Scan signal Scan2, and the start time of the on-level signal of the second Scan signal Scan2 is later than the start time of the on-level signal of the first Scan signal Scan1, this scheme can control the compensation transistor T2 to be still turned on when the data writing transistor T1 is turned off, so that the data voltage Vdata can be continuously written into the gate of the driving transistor DT and the storage capacitor Cst through the driving transistor DT and the compensation transistor T2 to charge the gate of the driving transistor DT and the storage capacitor Cst, thereby prolonging the charging time of the pixel circuit.

Alternatively, on the basis of the above scheme, the Scan signal output terminal of the n-1 st stage first Scan circuit 400 is further connected to the third Scan line S3/4 corresponding to the nth row of pixel circuits 100, the gates of the first initialization transistor T3 and the second initialization transistor T4 in the nth row of pixel circuits 100 are both connected to the third Scan line S3/4 corresponding to the present row of pixel circuits, the first Scan signal Scan1 connected to the gate of the data write transistor T1 in the previous row of pixel circuits 100, the timing of the third Scan signal Scan3 to which the gate of the first initialization transistor T3 in the next row of pixel circuits 100 is turned on and the fourth Scan signal Scan4 to which the gate of the second initialization transistor T4 is turned on are the same, and the gate of the first initialization transistor T3 and the gate of the second initialization transistor T4 in the first row of pixel circuits 100 are directly turned on by the same Scan signal. In this way, the first Scan signal Scan1 corresponding to the pixel circuit in the current row can be used as the third Scan signal Scan3 and the fourth Scan signal Scan4 corresponding to the pixel circuit in the next row.

The embodiment of the invention further provides a driving method of a display panel, and fig. 10 is a flow diagram illustrating the driving method of the display panel provided by the embodiment of the invention. Referring to fig. 1 to 4, the display panel includes:

a substrate 10;

a thin film transistor, a scan line and a data line DL on the substrate 10;

the thin film transistor comprises a data writing transistor T1, a driving transistor DT and a compensating transistor T2, wherein the data writing transistor T1 is used for writing the data voltage Vdata on the data line DL into the grid electrode of the driving transistor DT, and the compensating transistor T2 is used for compensating the threshold voltage of the driving transistor DT; the scanning lines comprise a first scanning line S1 and a second scanning line S2, the gate of the data writing transistor T1 is connected with the first scanning line S1, and the gate of the compensation transistor T2 is connected with the second scanning line S2;

the first scan line S1 extends along the first direction X and is located on the first metal layer 30; the second scan line S2 includes a first wire trace portion S21 and a second wire trace portion S22 arranged along the first direction X, the first wire trace portion S21 and the second wire trace portion S22 are electrically connected, the first wire trace portion S21 is located on the first metal layer 30, the second wire trace portion S22 is located on the second metal layer 40, and a source/drain of the thin film transistor is located on the second metal layer 40; the second metal layer 40 further includes a transfer section 410, and the active layer 20 of the compensation transistor T2 and the active layer 20 of the driving transistor DT are electrically connected through the transfer section 410;

accordingly, as shown in fig. 10, the driving method of the display panel includes:

and S110, applying a first scanning signal to the first scanning line.

And S120, applying a second scanning signal to the second scanning line.

The conducting level signal of the first scanning signal is overlapped with the conducting level signal of the second scanning signal, and the starting time of the conducting level signal of the second scanning signal is later than that of the conducting level signal of the first scanning signal.

Illustratively, the turn-on level signal of the first Scan signal Scan1 overlaps the turn-on level signal of the second Scan signal Scan2, and the start time of the turn-on level signal of the second Scan signal Scan2 is later than the start time of the turn-on level signal of the first Scan signal Scan 1. Taking the data writing transistor T1 and the compensating transistor T2 as P-channel transistors as an example, the on level signals of the first Scan signal Scan1 and the second Scan signal Scan2 are both low level signals that control the transistors to be on. The turn-on level signal of the first Scan signal Scan1 overlaps the turn-on level signal of the second Scan signal Scan2 so that the turn-on periods of the data write transistor T1 and the compensation transistor T2 overlap, and the turn-on level signal of the second Scan signal Scan2 starts at a timing later than the start timing of the turn-on level signal of the first Scan signal Scan1 so that the turn-on timing of the compensation transistor T2 is later than the turn-on timing of the data write transistor T1. In this way, in the data writing phase, the data writing transistor T1 is turned on earlier than the compensating transistor T2, when the compensating transistor T2 is turned on, the data voltage Vdata on the data line DL is written into the gate electrode of the driving transistor DT and the storage capacitor Cst through the turned-on data writing transistor T1 and the compensating transistor T2, and when the data writing transistor T1 is turned off, the compensating transistor T2 is still turned on, and the data voltage Vdata can be continuously written into the gate electrode of the driving transistor DT and the storage capacitor Cst through the driving transistor DT and the compensating transistor T2 to charge the gate electrode of the driving transistor DT and the storage capacitor Cst, thereby extending the charging time of the pixel circuit.

According to the technical scheme, the grid electrode of the data writing transistor is connected with the first scanning line, the grid electrode of the compensation transistor is connected with the second scanning line, the connection and disconnection of the data writing transistor and the compensation transistor can be controlled by different scanning signals respectively, when the connection time of the data writing transistor and the compensation transistor is controlled to be overlapped, and the connection time of the compensation transistor is later than the connection time of the data writing transistor, after the data writing transistor is controlled to be disconnected in the data writing stage, the compensation transistor is controlled to be continuously connected, so that data voltage is continuously written into the grid electrode of the driving transistor and the storage capacitor through the driving transistor and the compensation transistor, the charging time of a pixel circuit is prolonged, and the display effect is improved; the first routing part and the second routing part of the second scanning line are arranged to be electrically connected, the first routing part is located on the first metal layer, and the second routing part is located on the second metal layer, so that the phenomenon that the second scanning line and active layers of other areas except the active layer of the compensation transistor are overlapped to form redundant thin film transistors to influence the work of a pixel circuit is avoided; the active layer of the compensation transistor and the active layer of the driving transistor are electrically connected through the switching part in the second metal layer, so that the phenomenon that the pixel circuit works because the region where the compensation transistor and the active layer of the driving transistor are electrically connected is overlapped with the scanning line in the first metal layer to form an extra thin film transistor is avoided.

The embodiment of the invention also provides a display device, and fig. 11 is a schematic structural diagram of the display device provided by the embodiment of the invention. Fig. 11 schematically shows a case where the display device 600 is a mobile phone, and in practical applications, the display device 600 may also be a device with a display function, such as a computer or a tablet computer. The display device provided by the embodiment of the present invention includes the display panel provided by any of the embodiments of the present invention, and therefore, the display device provided by the embodiment of the present invention has the functional structure and the beneficial effects of the display panel provided by any of the embodiments of the present invention, and details are not repeated herein.

It is to be noted that the foregoing description is only exemplary of the invention and that the principles of the technology may be employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, comprising:

a substrate;

2. The display panel according to claim 1, wherein the active layer of the driving transistor is located on one side of the first scan line, and wherein the active layer of the compensation transistor and the second scan line are located on the other side of the first scan line.

3. The display panel according to claim 1, wherein the data writing transistor is connected between the data line and the driving transistor, and a width of an active layer on a side where the data writing transistor is connected to the driving transistor is larger than a width of an active layer on a side where the data writing transistor is connected to the data line.

4. The display panel according to claim 3, further comprising a storage capacitor, wherein a first plate of the storage capacitor is located in the first metal layer, a second plate of the storage capacitor is located in a third metal layer, and the third metal layer is located between the first metal layer and the second metal layer;

and the vertical projection of the second polar plate of the storage capacitor on the substrate covers the vertical projection of an active layer on one side of the data writing transistor, which is connected with the driving transistor, on the substrate.

5. The display panel according to claim 1, further comprising a power supply line including a third routing portion and a fourth routing portion arranged in a second direction, the second direction crossing the first direction, the third routing portion and the fourth routing portion being electrically connected;

the third routing portion is located on the second metal layer, and the third routing portion is separated from the second routing portion of the second scanning line; the fourth wire routing part is located on a fourth metal layer, and the fourth metal layer is located on one side, far away from the substrate, of the second metal layer.

6. The display panel of claim 5, wherein the data line extends in the second direction and the data line is located in the fourth metal layer.

7. The display panel according to any one of claims 1 to 6, wherein the display panel comprises i rows of pixel circuits and i stages of cascade-connected scanning circuits;

8. The display panel according to any one of claims 1 to 6, wherein the display panel comprises i rows of pixel circuits, a first scanning circuit of i-stage cascade connection, and a second scanning circuit of i-stage cascade connection;

9. A driving method of a display panel, the display panel comprising:

a substrate;

the driving method of the display panel includes:

10. A display device characterized by comprising the display panel according to any one of claims 1 to 8.