CN113314591A - Lateral diffusion metal oxide semiconductor field effect transistor with low saturation current - Google Patents
Lateral diffusion metal oxide semiconductor field effect transistor with low saturation current Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 230000005669 field effect Effects 0.000 title claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 10
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 10
- 238000009792 diffusion process Methods 0.000 title claims abstract description 9
- 210000000746 body region Anatomy 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 16
- 229920005591 polysilicon Polymers 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 3
- 229910052760 oxygen Inorganic materials 0.000 claims 2
- 239000001301 oxygen Substances 0.000 claims 2
- 238000005468 ion implantation Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Power Engineering (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A lateral diffusion metal oxide semiconductor field effect transistor with low saturation current comprises a P-type substrate, an N-type drift region is arranged on a P-type substrate, a P-type body region and a drain N-type heavily doped region are arranged in the N-type drift region, a source P-type heavily doped region and a source N-type heavily doped region are arranged in the P-type body region, the source P-type heavily doped region and the source N-type heavily doped region are led out by source metal to jointly form a source electrode of the device, the drain N-type heavily doped region is led out by drain metal to form a drain electrode of the device, a field oxide is arranged above the N-type drift region, a polysilicon gate and a polysilicon field plate are arranged in the field oxide, it is characterized in that a P-top buried layer is also arranged in the N-type drift region and is connected to the source electrode of the device through source electrode metal, the polysilicon field plate starts above the P-top buried layer and extends to the upper part of the N-type drift region.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a lateral diffusion metal oxide semiconductor field effect transistor for reducing saturation current based on a silicon carbide material.
Background
The development of semiconductor materials has undergone three generations of revolution, the first generation being a first generation semiconductor material represented by silicon (Si) and germanium (Ge), the second generation being a second generation semiconductor material represented by gallium arsenide (GaAs), and the third generation being a third generation wide bandgap semiconductor material represented by silicon carbide and gallium nitride. Over half a century of semiconductor device development, the performance of silicon material based power semiconductor devices has approached their physical limits. Therefore, the development of third generation semiconductor materials represented by silicon carbide (SiC), gallium nitride (GaN), and the like has been receiving attention.
Compared with the SiC longitudinal power device, the SiC transverse device has unique advantages in the aspects of easy integration with other devices, cost reduction and circuit overall performance enhancement. The high-voltage SiC-LDMOS device is mainly applied to the fields of automobile electronics, intelligent power ICs, industrial motor driving, medical equipment and the like as a power switch. With the continuous development of industrial automation, mobile communication, automotive electronics and aerospace technologies, the demand is continuously improved, and higher requirements are provided for the breakdown voltage, the frequency characteristic, the output power, the switching power consumption and the short circuit safety of the SiC-LDMOS device under extreme conditions. When the power device is in short circuit, the current inside the device is the saturation current of the device, and the larger the saturation current of the device is, the more serious the short circuit performance of the device is reduced, so that the reduction of the saturation current has great significance for improving the short circuit safety of the device.
Disclosure of Invention
Aiming at the problems, the invention provides a lateral diffusion metal oxide semiconductor field effect transistor with low saturation current, which can effectively reduce the saturation current of a device; a further improvement is that the saturation current of the device is reduced at the same time, maintaining the current in the linear region of the device.
The technical scheme of the invention is as follows:
a lateral diffusion metal oxide semiconductor field effect transistor with low saturation current comprises a P-type substrate, an N-type drift region is arranged on a P-type substrate, a P-type body region and a drain N-type heavily doped region are arranged in the N-type drift region, a source P-type heavily doped region and a source N-type heavily doped region are arranged in the P-type body region, the source P-type heavily doped region and the source N-type heavily doped region are led out by source metal to jointly form a source electrode of the device, the drain N-type heavily doped region is led out by drain metal to form a drain electrode of the device, a field oxide is arranged above the N-type drift region, a polysilicon gate and a polysilicon field plate are arranged in the field oxide, it is characterized in that a P-top buried layer is also arranged in the N-type drift region and is connected to the source electrode of the device through source electrode metal, the polysilicon field plate starts above the P-top buried layer and extends to the upper part of the N-type drift region.
Compared with the prior art, the structure of the invention has the following advantages:
1. the device has a lower saturation current than conventional structures. The invention has the innovation point that the device is provided with a P-top buried layer doped with P type in an N type drift region. The P-top buried layer when grounded is used for reducing the potential at the tail end of the channel, so that the number of electrons entering the drift region in unit time unit area is reduced, and the saturation current of the device is reduced. When positive voltage is applied to the grid (G) and positive voltage is applied between the source and the drain, an inversion layer is formed below the polysilicon grid, and when electrons start from the N-type heavily doped region of the source and enter the drift region through the inversion layer, the number of electrons reaching the drain through the drift region in unit time is reduced due to the influence of the potential reduction at the tail end of the channel, so that the saturation current of the device is obviously reduced.
2. Compared with the traditional structure, the structure of the invention has the same current in the linear region. Because the current in the linear region and the current in the saturation region have positive correlation, the current in the linear region can be obviously reduced while the current in the saturation region is reduced in the traditional structure, and the overall performance of the device is further influenced. According to the structure, the N-well buried layer with the doping concentration higher than that of the drift region is introduced, and the N-well buried layer is used for reducing the resistance between the P-top buried layer and the P-type body region, so that the influence of the introduction of the P-top buried layer on linear region current is eliminated. Therefore, compared with the traditional structure, the structure of the invention has the same linear region current while reducing the saturation current, and ensures other performances of the device on the premise of improving the short-circuit performance of the device.
3. The structure of the invention is completely compatible with the manufacturing process of the traditional structure, the whole manufacturing process can be realized by increasing the number of the mask plates, and the complexity and the cost of the process are not increased. The specific manufacturing process comprises the following steps:
(1) growing an N-type drift region on the 4H-SiC substrate;
(2) forming a P-type body region by four times of ion implantation;
(3) forming a P-top buried layer by four times of ion implantation;
(4) forming an N-well buried layer by four times of ion implantation;
(5) four times of ion implantation in the P-type body region form a source N-type heavily doped region, and four times of ion implantation in the N-type drift region form a drain N-type heavily doped region;
(6) four times of ion implantation in the P-type body region form a source P-type heavily doped region, and four times of ion implantation in the P-top buried layer form a P-type heavily doped region;
(7) the field oxide, gate, source, drain and field plate are fabricated on the surface.
Drawings
Fig. 1 is a block diagram showing a conventional structure.
Fig. 2 is a structural view showing the structure of the present invention.
Fig. 3 is a diagram showing a potential distribution of the conventional structure.
Fig. 4 shows the potential distribution diagram of the structure of the present invention.
FIG. 5 is an I-V comparison of the structure of the present invention with a conventional structure.
Detailed Description
A lateral diffusion metal oxide semiconductor field effect transistor with low saturation current comprises a P-type substrate 1, an N-type drift region 2 is arranged on a P-type substrate 1, a P-type body region 3 and a drain N-type heavily doped region 10 are arranged in the N-type drift region 2, a source P-type heavily doped region 4 and a source N-type heavily doped region 5 are arranged in the P-type body region 3, the source P-type heavily doped region 4 and the source N-type heavily doped region 5 are led out through source metal 6 to jointly form a source electrode of the device, the drain N-type heavily doped region 10 is led out through drain metal 9 to form a drain electrode of the device, a field oxide 8 is arranged above the N-type drift region 2, a polysilicon grid 7 and a polysilicon field plate 14 are arranged in the field oxide 8, and a P-top buried layer 12 is arranged in the N-type drift region 2, the P-top buried layer 12 is connected to the source electrode of the device through a source electrode metal 6, the polysilicon field plate 14 starts above the P-top buried layer 12 and extends above the N-type drift region 2. In the present embodiment, it is preferred that,
an N-type doped N-well buried layer 11 is arranged between the P-type body region 3 and the P-type doped P-top buried layer 12, two boundaries of the N-type doped N-well buried layer 11 are respectively connected to the boundary of the P-type body region 3 and the boundary of the P-type doped P-top buried layer 12, and the doping concentration of the N-type doped N-well buried layer 11 is higher than that of the drift region 2, for example: the doping concentration of the N-well buried layer 11 doped in the N type can be 2.0 x 1017cm-3The doping concentration of the drift region 2 may be 1.0 × 1016cm-3(ii) a The polysilicon gate 7 starts above the source N-type heavily doped region 5 and extends to the upper part of the N-well buried layer 11 after passing through the P-type body region 3; in order to further improve the linear current of the device, the length of the N-well buried layer 11 is 1.5-2.0 μm, the junction depth is 0.55-0.60 μm, and the doping concentration of the N-well buried layer 11 is 1.8 multiplied by 1017～2.0×1017cm-3。
In the embodiment, a P-type heavily doped region 13 is arranged in a P-top buried layer 12, and the P-top buried layer 12 is connected to the source of the device through the P-type heavily doped region 13 and a source metal 6.
In order to reduce the saturation current of the device, the length of the P-top buried layer 12 is 1.5-2.0 microns, the junction depth is 0.50-0.55 microns, and the doping concentration of the P-top buried layer 12 is 1.6 multiplied by 1017～1.7×1017cm-3。
The present invention will be described in detail with reference to the accompanying drawings.
The working principle of the invention is further explained below with reference to the attached drawings:
when a forward voltage is applied to the polysilicon gate 7, an electron conduction channel is inverted in the P-type body region 3 therebelow. When a forward voltage is applied to the drain 10 of the device, electrons in the source N-type heavily doped region 5 are influenced by the rising of the potential at the end of the channel, and enter the N-type drift region 2 from the source N-type heavily doped region 5 through the conducting channel region. As the voltage of the drain 10 increases, the potential at the end of the channel increases, electrons entering the N-type drift region 2 increase, and the current of the device increases. By introducing a grounded P-top buried layer 12, the potential at the end of the channel is affected by potential modulation of the P-top buried layer 12, and therefore the potential at the end of the channel is lowered compared to the conventional structure. As shown in fig. 3 and 4. When the voltage of the drain 10 is 400V, the potential of the channel end of the structure of the invention is 4.5V, while the potential of the channel end of the conventional structure is 6.2V. Therefore, under the same drain voltage, the potential of the tail end of the channel of the structure is lower, and the potential of the tail end of the channel is reduced, so that the number of electrons entering a drift region in unit time of the structure is reduced, and the aim of reducing saturation current is fulfilled.
By introducing the N-well buried layer 11, the electron concentration between the P type body region 3 and the P-top buried layer 12 is improved, so that the resistance in the N-well buried layer 11 is reduced, when electrons are injected into the N type drift region 2 from a channel inversion layer, the resistance of the electrons is smaller because the resistance of the N-well buried layer 11 is lower than that of the N type drift region 2, the number of the electrons entering the N type drift region 2 in unit time is more, so that when a device is in a linear working region, the N-well buried layer 11 compensates the influence of the P-top buried layer 12, and the linear region of the device is not reduced. As shown in the figure five, on the basis of realizing the reduction of the saturation current by 24.2%, the current of a linear area is 26.05mA/mm, the linear current (26mA/mm) which is basically the same as that of the traditional structure is maintained, and other basic performances of the device are not degraded.
Therefore, the potential at the end of the channel is lowered by the P-top buried layer 12, thereby lowering the saturation current of the device. The influence of the P-top buried layer 12 on the linear current is reduced by the N-well buried layer 11. The aim of reducing saturation current and keeping the current in the linear region of the device is fulfilled.
The structure of the invention is completely compatible with the manufacturing process of the traditional structure, the whole manufacturing process can be realized by increasing the number of the mask plates, and the complexity and the cost of the process are not increased. The specific manufacturing process comprises the following steps:
(1) growing an N-type drift region 2 on a 4H-SiC substrate 1;
(2) forming a P-type body region 3 by four times of ion implantation;
(3) forming a P-top buried layer 12 by four times of ion implantation;
(4) forming an N-well buried layer 11 by four times of ion implantation;
(5) four times of ion implantation in the P type body region 3 form a source N type heavily doped region 5, and four times of ion implantation in the N type drift region 2 form a drain N type heavily doped region 10;
(6) performing four times of ion implantation in the P type body region 3 to form a source P type heavily doped region 4, and performing four times of ion implantation in the P-top buried layer 12 to form a P type heavily doped region 13;
(7) the field oxide 8, gate 7, source 6, drain 9 and field plate 14 are fabricated at the surface.
Claims (7)
1. A lateral diffusion metal oxide semiconductor field effect transistor with low saturation current comprises a P-type substrate (1), an N-type drift region (2) is arranged on the P-type substrate (1), a P-type body region (3) and a drain N-type heavily doped region (10) are arranged in the N-type drift region (2), a source P-type heavily doped region (4) and a source N-type heavily doped region (5) are arranged in the P-type body region (3), the source P-type heavily doped region (4) and the source N-type heavily doped region (5) are led out through source metal (6) to jointly form a source electrode of the device, the drain N-type heavily doped region (10) is led out through drain metal (9) to form a drain electrode of the device, field oxygen (8) is arranged above the N-type drift region (2), a polysilicon gate (7) and a polysilicon field plate (14) are arranged in the field oxygen (8), and the lateral diffusion metal oxide semiconductor field effect transistor is characterized in that a P-top buried layer (12), the P-top buried layer (12) is connected to the source electrode of the device through a source electrode metal (6), and the polysilicon field plate (14) starts above the P-top buried layer (12) and extends to the upper part of the N-type drift region (2).
2. The LDMOS transistor with low saturation current according to claim 1, wherein an N-type doped buried N-well layer (11) is disposed between the P-type body region (3) and the P-type doped buried P-top layer (12), and two boundaries of the N-type doped buried N-well layer (11) are respectively connected to a boundary of the P-type body region (3) and a boundary of the P-type doped buried P-top layer (12), and a doping concentration of the N-type doped buried N-well layer (11) is higher than a doping concentration of the drift region (2); the polysilicon gate (7) starts above the source N-type heavily doped region (5) and extends to the upper part of the N-well buried layer (11) after passing through the P-type body region (3).
3. A low saturation current ldmosfet according to claim 1 or 2, wherein a heavily P-doped region (13) is provided in the P-top buried layer (12), and the P-top buried layer (12) is connected to the source of the device through the heavily P-doped region (13) and the source metal (6).
4. The LDMOS transistor of claim 1, wherein the buried N-well layer (11) has a length of 1.5-2.0 μm and a junction depth of 0.55-0.60 μm.
5. The LDMOS transistor of claim 4, wherein the buried N-well layer (11) has a doping concentration of 1.8 x 1017～2.0×1017cm-3。
6. The LDMOS transistor of claim 1, wherein the P-top buried layer (12) has a length of 1.5-2.0 μm and a junction depth of 0.50-0.55 μm.
7. Lateral diffused metal oxide semiconductor field effect transistor with low saturation current according to claim 6, characterized in that the P-top buried layer (12) has a doping concentration of 1.6 x 1017～1.7×1017cm-3。
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090206402A1 (en) * | 2008-02-15 | 2009-08-20 | Advanced Analogic Technologies, Inc. | Lateral Trench MOSFET with Bi-Directional Voltage Blocking |
| US20130069712A1 (en) * | 2011-09-15 | 2013-03-21 | Tanya Trajkovic | Power semiconductor devices and fabrication methods |
| US20140264587A1 (en) * | 2013-03-12 | 2014-09-18 | Dongbu Hitek Co., Ltd. | Laterally diffused metal oxide semiconductor and method for fabricating the same |
| CN106549062A (en) * | 2015-09-22 | 2017-03-29 | 德克萨斯仪器股份有限公司 | The double mode conduction of P N reduces surface field（RESURF）LDMOS |
-
2021
- 2021-05-26 CN CN202110577494.XA patent/CN113314591A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090206402A1 (en) * | 2008-02-15 | 2009-08-20 | Advanced Analogic Technologies, Inc. | Lateral Trench MOSFET with Bi-Directional Voltage Blocking |
| US20130069712A1 (en) * | 2011-09-15 | 2013-03-21 | Tanya Trajkovic | Power semiconductor devices and fabrication methods |
| US20140264587A1 (en) * | 2013-03-12 | 2014-09-18 | Dongbu Hitek Co., Ltd. | Laterally diffused metal oxide semiconductor and method for fabricating the same |
| CN106549062A (en) * | 2015-09-22 | 2017-03-29 | 德克萨斯仪器股份有限公司 | The double mode conduction of P N reduces surface field（RESURF）LDMOS |
Non-Patent Citations (1)
| Title |
|---|
| LONG ZHANG 等: "Simulation Study of A 1200V 4H-SiC Lateral MOSFET With Reduced Saturation Current", 《IEEE ELECTRON DEVICE LETTERS》 * |
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