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CN112764342B - Time measuring device and method - Google Patents

Time measuring device and method Download PDF

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Publication number
CN112764342B
CN112764342B CN201911060092.1A CN201911060092A CN112764342B CN 112764342 B CN112764342 B CN 112764342B CN 201911060092 A CN201911060092 A CN 201911060092A CN 112764342 B CN112764342 B CN 112764342B
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measurement
time
delay
signal
measuring
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CN112764342A (en
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夏冰冰
石拓
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Zvision Technologies Co Ltd
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Zvision Technologies Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483Details of pulse systems
    • G01S7/486Receivers
    • GPHYSICS
    • G04HOROLOGY
    • G04FTIME-INTERVAL MEASURING
    • G04F10/00Apparatus for measuring unknown time intervals by electric means

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Abstract

The invention provides a time measuring device and a method, wherein the time measuring device comprises a signal splitter, a signal receiving unit and a time measuring unit, wherein the signal splitter is used for receiving a signal to be measured and dividing the signal to be measured into a plurality of sub-signals to be measured; each measuring channel in the plurality of measuring channels is used for measuring a sub-signal to be measured in the plurality of sub-signals to be measured; each measurement channel includes: the device comprises a delay module, a measurement module and a compensation module; and the arithmetic operation unit is used for calculating a final measurement result according to the approximate time measurement results when no less than a preset number of the approximate time measurement results exist in the group of second measurement results. The technical scheme of the invention can solve the problem of inaccurate measurement caused by metastable state in the laser radar ranging system, improve the accuracy of time measurement and further improve the precision of the ranging system.

Description

Time measuring device and method
Technical Field
The present invention relates to the field of electronic circuits, and in particular, to a time measuring apparatus and method.
Background
In a ranging system such as a laser radar, in order to obtain a ranging result, a time interval between transmitting a laser pulse and receiving the laser pulse needs to be measured, and the distance between the laser radar and a target object can be obtained by multiplying the time interval by a light speed. Since the speed of light is very fast, the measurement accuracy of the time interval can seriously affect the final ranging accuracy. Therefore, the high-precision time measuring device has important significance for improving the measuring precision of the laser radar.
In the prior art, a programmable gate array such as an fpga (field programmable gate array) can be used to implement the time measurement. In an FPGA, the case where a flip-flop or latch cannot reach an identifiable state within some specified period of time is called a meta-stable state. For example, if the data transfer does not satisfy the condition of the flip-flop, or the reset signal is released during the reset process for an insufficient recovery time with respect to the active clock edge, a meta-stable condition may occur, in which the flip-flop output is in an indeterminate state for a relatively long time after the active clock edge, during which the flip-flop output is in an oscillating state between 0 and 1. Even if the time later stabilizes to 0 or 1, the steady state is random and has no necessary connection with the input, resulting in errors in the final time measurement. Therefore, how to eliminate the influence of the metastable state is a problem to be solved when the FPGA is adopted to realize the time measurement.
Disclosure of Invention
The invention aims to provide a time measuring device and a time measuring method for a laser radar ranging system, which can eliminate the influence of a metastable state in an FPGA (field programmable gate array) and improve the accuracy of time measurement.
The technical scheme provided by the invention is as follows:
the invention provides a time measuring device, comprising a signal splitter, a plurality of measuring channels and an arithmetic operation unit; the signal splitter is used for receiving a signal to be tested and dividing the signal to be tested into a plurality of sub-signals to be tested; each of the plurality of measurement channels is configured to measure one of the plurality of sub-signals to be measured; each measurement channel of the plurality of measurement channels comprises: the delay module is used for carrying out first delay on the input sub-signal to be detected to obtain a signal after the first delay; the measuring module is used for measuring the first delayed signal to obtain a first measuring result; the compensation module is used for compensating the first measurement result according to the first delay to obtain a compensated second measurement result; and the arithmetic operation unit is used for calculating a final measurement result according to the approximate time measurement results when no less than a preset number of the approximate time measurement results exist in a group of second measurement results.
Optionally, the time measuring device calculates a final measurement result according to the approximate time measurement result, including: calculating the average value of all similar time measurement results to obtain a final measurement result; or deleting the highest value and the lowest value in the similar time measurement results, and calculating the average value of the rest similar time measurement results to obtain the final measurement result.
Optionally, the number of the plurality of measurement channels in the time measurement device is N, and the preset number of similar time measurement results is a minimum integer not less than (N + 1)/2.
Optionally, the measurement module comprises: a plurality of second delay sub-modules; and the input end of each flip-flop in the plurality of flip-flops is connected with the output end of each second delay submodule of the plurality of second delay submodules through a tap respectively.
Optionally, in the time measuring device, the approximate time measurement result includes a time measurement result that is different from each other by less than a preset threshold value in the group of second measurement results; wherein the preset threshold is at least related to a second delay of the plurality of second delay submodules. .
Optionally, the compensation module includes a subtractor, configured to subtract the first delay from the first measurement result to obtain the second measurement result.
Optionally, the clock period of the time measurement device is set to a metastable time window greater than 2 times.
Optionally, the first delay time of the first delay module in each of the plurality of measurement channels for delaying the input signal is set to be distributed in an arithmetic progression.
Optionally, the time interval T of the first delay time is 1/N system cycles.
The invention also provides a time measuring method, which comprises the following steps:
receiving a signal to be detected by adopting a signal splitter, and dividing the signal to be detected into a plurality of sub-signals to be detected;
measuring each sub-signal to be measured in the plurality of sub-signals to be measured by adopting each measuring channel in a plurality of measuring channels;
performing first time delay on the input sub-signal to be detected by adopting a time delay module in each measuring channel of the plurality of measuring channels to obtain a first time-delayed signal;
measuring the first delayed signal by using a measurement module in each of the plurality of measurement channels to obtain a first measurement result;
compensating the first measurement result by adopting a compensation module in each of the plurality of measurement channels according to the first delay to obtain a compensated second measurement result;
and when the group of second measurement results has no less than a preset number of similar time measurement results, calculating a final measurement result according to the similar time measurement results by adopting an arithmetic operation unit.
Optionally, in the time measurement method, calculating a final measurement result according to the approximate time measurement result includes: calculating the average value of all similar time measurement results to obtain a final measurement result; or deleting the highest value and the lowest value in the similar time measurement result sum, and calculating the average value of the rest similar time measurement results to obtain the final measurement result.
Optionally, in the time measurement method, the number of the plurality of measurement channels is N, and the preset number of similar time measurement results is a minimum integer not less than (N + 1)/2.
Optionally, in the time measurement method, a first delay of the first delay module in each of the plurality of measurement channels to delay the input signal is set to be an arithmetic progression distribution.
Optionally, in the time measurement method, a time interval T of the first delay time is 1/N system cycles.
By adopting the technical scheme of the invention, the problem of inaccurate measurement caused by metastable state in the laser radar ranging system can be solved, the accuracy of time measurement is improved, and the precision of the ranging system is further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural view of a time measuring apparatus according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of the operation of a measurement module in a time measurement device according to an embodiment of the present invention.
Fig. 3 is a flow chart of a time measurement method according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of systems consistent with certain aspects of the invention, as detailed in the appended claims.
Fig. 1 is a schematic structural view of a time measuring apparatus according to an embodiment of the present invention. As shown in fig. 1, the time measuring apparatus includes a signal splitter 11, a plurality of measuring channels 12, and an arithmetic operation unit 13, where the signal splitter 11 is configured to receive a signal to be measured and divide the signal to be measured into a plurality of sub-signals to be measured; each of the plurality of measurement channels 12 (N measurement channels are taken as an example in fig. 1) is configured to measure one sub-signal under test of the plurality of sub-signals under test; each measurement channel of the plurality of measurement channels 12 comprises: the first delay module YSA is used for carrying out first delay on the input sub-signal to be detected to obtain a first delayed signal; the measurement module CL is used for measuring the signal after the first time delay to obtain a first measurement result; the compensation module BC is used for compensating the first measurement result according to the first delay to obtain a compensated second measurement result; and an arithmetic operation unit 13 for calculating a final measurement result according to the approximate time measurement results when the compensated group of second measurement results has not less than a preset number of the approximate time measurement results.
According to an embodiment of the present invention, when the compensated second measurement results are not similar, it cannot be determined which measurement channel has the correct measurement result, and at this time, the current measurement may be considered as an error, and the current measurement result may be discarded. When the measurement is wrong, the arithmetic operation module 13 may further output an error prompt message.
According to one embodiment of the invention, the final measurement is calculated from the close time measurements by calculating an average of all close time measurements.
According to another embodiment of the present invention, a final measurement result is calculated according to the close time measurement results, and after deleting the highest value and the lowest value in the close time measurement results, an average value of the remaining close time measurement results is calculated to obtain the final measurement result.
In an embodiment of the present invention, the number of the plurality of measurement channels is N, and the predetermined number may be an integer rounded up by (N +1)/2, that is, a minimum integer not less than (N +1)/2, for a time measurement result not less than a predetermined number of the close time measurements in the compensated set of second measurement results.
Fig. 2 is a schematic diagram of the operation of a measurement module in a time measurement device according to an embodiment of the present invention. According to an embodiment of the invention, the measurement module CL comprises a flip-flop CF, implemented using a chain of multi-stage delay modules plus flip-flops. As shown in fig. 2, an input terminal of each of the plurality of flip-flops CF is connected to an output terminal of the corresponding second delay submodule YSB through a tap CT, and each of the second delay submodules theoretically has the same delay. For FPGA implementation, each second delay submodule corresponds to a carry chain delay, such as a delay on a carry chain of a carry look ahead adder like a Multiplexer (MUXCY), each second delay submodule YSB outputs to a data input end of a corresponding flip-flop CF, each flip-flop latches the level of each input tap CT by using a clock signal of a clock counter 15 of the same source, for a delay chain including N second delay submodules YSB, N bits of latched data are generated in total, the latched data enter an N bit encoder 14 to generate a corresponding code, the encoding method generally uses a thermometer to encode the level of the corresponding second delay submodule YSB by judging the conversion of 0-1 level, the level of the corresponding second delay submodule YSB is calculated by adding a coarse-grained count value of the corresponding clock to the level of the corresponding second delay submodule, the overall measurement time interval is obtained.
According to an embodiment of the present invention, since the time of each second delay submodule cannot be strictly consistent in the actual circuit implementation process, even if no metastable state occurs in the measurement process, the measurement results of each measurement channel cannot be completely consistent. Thus, similar time measurements may be defined as time measurements included in a set of second measurements that differ from each other by less than a preset threshold; wherein the predetermined threshold is associated with at least a second delay of the second delay submodule. According to an embodiment of the invention, the preset threshold may be an integer multiple, e.g. 1 or 2 times, of the second delay submodule.
According to an embodiment of the present invention, the first delay module YSA and/or the second delay module YSB may be formed by serially connecting a plurality of inverters, and the number of inverters in the first delay module YSA and/or the second delay module on each measurement channel may be set according to the delay requirement of the measurement channel. The first delay module and/or the second delay submodule may also adopt a delay unit of any FPGA, for example, a logic unit of a carry-ahead chain, and the implementation manner of the first delay module and the second delay submodule is not particularly limited in this embodiment.
According to an embodiment of the invention, the compensation block BC may be a subtractor for subtracting the first delay of the first delay block YSA from the measured amount of time to obtain a second measurement result. According to an embodiment of the present invention, the compensation module BC compensates the measurement result of each path according to the first delay time of the first delay module YSA, that is, the first measurement result of each path is subtracted by the first delay time of the path to obtain the second measurement result t of the path1=T1-ΔT1,t2=T2-ΔT2,……,tN=TN-ΔTN. The occurrence of the metastable state has a certain probability, and the metastable state can cause random errors of the measurement result and larger deviation of the measurement result. Therefore, when at least a preset number of similar time measurement results exist in the compensated second measurement result, the arithmetic operation unit 13 calculates a final measurement result based on the similar time measurement results.
According to an embodiment of the present invention, the clock period may be set to be greater than 2 times the metastable time window, so that the measurement results of most measurement channels are not affected by the metastable state, thereby further improving the measurement accuracy.
According to an embodiment of the invention, the first delay module YSA may delay the input signal by Δ T respectively1,ΔT2,……,ΔTNDelayed signals are obtained, the delays are all larger than 0 and smaller than one clock cycle (the period of the clock signal in fig. 2), and most signals are ensured not to fall into a time window corresponding to the metastable state of the sampling clock through different time intervals. Then, the first measurement results of the N measurement modules CL performing time measurement on the first delayed signals are T1,T2,……,TN
According to an embodiment of the present invention, the first delay of each road measurement channel may be set to be in an arithmetic progression distribution, for example, the first delay time interval T is 1/N of a system period, so that the metastable state may be uniformly distributed to achieve an overall optimal probability distribution. Here, the system period is a period of the sampling clock signal. The actual setting may be Δ T1=T,ΔT2=2T,……,ΔTN=N*T。
Fig. 3 is a flow chart of a time measurement method according to an embodiment of the invention. As shown in fig. 3, the time measuring method of the present invention includes the steps of:
s1, a signal splitter is adopted to receive the signal to be detected and divide the signal to be detected into a plurality of sub signals to be detected;
s2, measuring each sub-signal to be measured in the sub-signals to be measured by adopting each measuring channel in a plurality of measuring channels;
s3, carrying out first time delay on the input sub-signal to be detected by adopting the time delay module in each measuring channel in the plurality of measuring channels to obtain a signal after the first time delay;
s4, measuring the first delayed signal by using the measuring module in each measuring channel of the plurality of measuring channels to obtain a first measuring result;
s5, compensating the first measurement result according to the first delay by adopting a compensation module in each of the plurality of measurement channels to obtain a compensated second measurement result;
and S6, adopting an arithmetic operation unit to calculate a final measurement result according to the approximate time measurement results when no less than a preset number of the approximate time measurement results exist in a group of second measurement results.
According to an embodiment of the present invention, in the time measuring method, calculating the final measurement result according to the proximate time measurement result includes: calculating the average value of all similar time measurement results to obtain a final measurement result; or deleting the highest value and the lowest value in the similar time measurement result sum, and calculating the average value of the rest similar time measurement results to obtain the final measurement result.
According to an embodiment of the present invention, in the time measurement method, the number of the plurality of measurement channels is N, and the preset number of the similar time measurement results is a minimum integer not less than (N + 1)/2.
According to an embodiment of the invention, in the time measurement method, the measurement module CL includes a plurality of second delay submodules YSB; and the input end of each flip-flop in the plurality of flip-flops CF is respectively connected with the output end of each second delay submodule of the corresponding plurality of second delay submodules YSB through the tap CT.
According to an embodiment of the present invention, in the time measurement method, the proximate time measurement results include time measurement results that are different from each other by less than a preset threshold value in the group of second measurement results; wherein the predetermined threshold is associated with at least a second delay of the plurality of second delay sub-modules.
According to an embodiment of the present invention, in the time measurement method, the compensation module BC includes a subtractor configured to subtract the first delay from the first measurement result to obtain a second measurement result.
According to an embodiment of the invention, in the time measurement method, the clock period of the time measurement means is set to a metastable time window larger than 2 times.
According to an embodiment of the present invention, in the time measurement method, a first delay time of delaying the input signal by the first delay module in each of the plurality of measurement channels is set to an arithmetic progression distribution.
According to an embodiment of the invention, in the time measurement method, the time interval T of the first delay time is 1/N system cycles.
The invention eliminates the influence of the metastable state in the time measuring device on the measuring result, simultaneously improves the precision of the measuring result through multi-path parallel measurement, and according to the measuring principle, when the channel which generates the metastable state is L through N-path parallel measurement, the corresponding measuring precision is the measuring precision of single path
Figure BDA0002257692610000061
The apparatus and methods described herein are not limited to a particular hardware or software configuration and may find applicability in many computing or processing environments. The apparatus and method may be implemented in hardware or software, or a combination of hardware and software. The apparatus and methods may be implemented in one or more computer programs, where a computer program may be understood to include one or more processor-executable instructions. The computer program may be executed on one or more programmable processors and may be stored on one or more storage media readable by the processors (including volatile and non-volatile memory and/or storage elements), one or more input devices, and/or one or more output devices. Thus, a processor may access one or more input devices to obtain input data and may access one or more output devices to communicate output data. The input and/or output devices may include one or more of: random Access Memory (RAM), Redundant Array of Independent Disks (RAID), floppy disk drive, CD, DVD, magnetic disk, internal hard drive, external hard drive, memory stick, or other storage device capable of being accessed by the processor provided herein, wherein the above examples are not exhaustive and are for illustration only and not limiting.
The features and benefits of the present invention are illustrated by reference to the examples. Accordingly, the invention is expressly not limited to these exemplary embodiments illustrating some possible non-limiting combination of features which may be present alone or in other combinations of features.
The above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (14)

1. A time measuring device for a programmable gate array is characterized by comprising a signal splitter, a plurality of measuring channels and an arithmetic operation unit;
the signal splitter is used for receiving a signal to be tested and dividing the signal to be tested into a plurality of sub-signals to be tested;
each of the plurality of measurement channels is configured to measure one of the plurality of sub-signals to be measured; each measurement channel of the plurality of measurement channels comprises:
the delay module is used for carrying out first delay on the input sub-signal to be detected to obtain a signal after the first delay;
the measuring module is used for measuring the first delayed signal to obtain a first measuring result;
the compensation module is used for compensating the first measurement result according to the first delay to obtain a compensated second measurement result;
and the arithmetic operation unit is used for calculating a final measurement result according to the approximate time measurement results when no less than a preset number of the approximate time measurement results exist in a group of second measurement results.
2. The time measurement device of claim 1, wherein calculating a final measurement based on the proximate time measurements comprises:
calculating the average value of all similar time measurement results to obtain a final measurement result; or
And deleting the highest value and the lowest value in the similar time measurement results, and calculating the average value of the rest similar time measurement results to obtain the final measurement result.
3. The time measurement device of claim 1, wherein the number of the plurality of measurement channels is N, and the preset number of similar time measurement results is a minimum integer no less than (N + 1)/2.
4. The time measurement device of claim 1, wherein the measurement module comprises:
a plurality of second delay sub-modules; and the input end of each flip-flop in the plurality of flip-flops is connected with the output end of each second delay submodule of the plurality of second delay submodules through a tap respectively.
5. The time measurement device of claim 4, wherein the proximate time measurements comprise time measurements in the set of second measurements that differ from each other by less than a preset threshold;
wherein the preset threshold is at least related to a second delay of the plurality of second delay submodules.
6. A time measurement device according to any one of claims 1 to 5, wherein the compensation module comprises a subtractor for subtracting the first delay from the first measurement to obtain the second measurement.
7. A time measurement device according to any of claims 1 to 5, wherein the clock period of the time measurement device is set to a metastable time window greater than 2 times.
8. The time measurement device according to any one of claims 1 to 5, wherein a first delay time for which the first delay module in each of the plurality of measurement channels delays the input signal is set to an arithmetic progression distribution.
9. The time measurement device of claim 8, wherein the time interval T of the first delay time is 1/N system cycles.
10. A time measurement method for a programmable gate array, comprising the steps of:
receiving a signal to be detected by adopting a signal splitter, and dividing the signal to be detected into a plurality of sub-signals to be detected;
measuring each sub-signal to be measured in the plurality of sub-signals to be measured by adopting each measuring channel in a plurality of measuring channels;
performing first time delay on the input sub-signal to be detected by adopting a time delay module in each measuring channel of the plurality of measuring channels to obtain a first time-delayed signal;
measuring the first delayed signal by using a measurement module in each of the plurality of measurement channels to obtain a first measurement result;
compensating the first measurement result by adopting a compensation module in each of the plurality of measurement channels according to the first delay to obtain a compensated second measurement result;
and when the group of second measurement results has no less than a preset number of similar time measurement results, calculating a final measurement result according to the similar time measurement results by adopting an arithmetic operation unit.
11. The method of claim 10, wherein calculating a final measurement based on the proximate time measurements comprises:
calculating the average value of all similar time measurement results to obtain a final measurement result; or
And deleting the highest value and the lowest value in the similar time measurement results, and calculating the average value of the rest similar time measurement results to obtain the final measurement result.
12. The time measurement method according to claim 10 or 11, wherein the number of the plurality of measurement channels is N, and the preset number of similar time measurement results is a minimum integer not less than (N + 1)/2.
13. The time measurement method according to claim 10 or 11, wherein a first delay time for which the first delay module in each of the plurality of measurement channels delays the input signal is set to an arithmetic progression distribution.
14. The method according to claim 13, wherein the time interval T of the first delay time is 1/N system cycles, and N is the number of the plurality of measurement channels.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104216279A (en) * 2014-09-23 2014-12-17 西安宏泰时频技术有限公司 Time interval measuring device based on FPGA (Field Programmable Gate Array)
WO2018113625A1 (en) * 2016-12-19 2018-06-28 武汉中派科技有限责任公司 Time-to-digital converter and time measurement method

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5020038A (en) * 1990-01-03 1991-05-28 Motorola, Inc. Antimetastable state circuit
KR100220672B1 (en) * 1994-10-31 1999-09-15 전주범 Time interval measurer having parallel architecture
AU690003B2 (en) * 1995-01-19 1998-04-09 Kama-Tech (Hk) Limited Laser range finder
US6226231B1 (en) * 1999-07-14 2001-05-01 Guide Technology, Inc. Time interval analyzer having multiple measurement circuits
CN100412729C (en) * 2005-05-13 2008-08-20 清华大学 Method and device for measuring time interval through delay line in cascaded two stages
US7979228B2 (en) * 2007-07-20 2011-07-12 The Regents Of The University Of Michigan High resolution time measurement in a FPGA
CN102736511B (en) * 2011-04-06 2014-08-20 中国科学院高能物理研究所 Time measurement system and time measurement method
CN103092060B (en) * 2013-02-08 2015-04-08 西安电子科技大学 Time interval measuring system and time interval measuring method which are based on field programmable gate array (FPGA)
PL227657B1 (en) * 2013-08-30 2018-01-31 Univ Jagiellonski Method for measuring parameters of analogue signal and the device for measuring parameters of analogue signal
WO2016127357A1 (en) * 2015-02-12 2016-08-18 中国科学技术大学 Fpga-based time-to-digital converter
GB2540730B (en) * 2015-05-11 2017-09-13 Thermo Fisher Scient (Bremen) Gmbh Time interval measurement
CN106019923B (en) * 2016-05-18 2018-11-13 中国科学技术大学 A kind of time-digital converter based on FPGA
CN109143832B (en) * 2018-07-26 2020-01-17 天津大学 High-precision multichannel time-to-digital converter
CN109143833B (en) * 2018-08-31 2019-10-29 西安电子科技大学 A kind of fractional part measuring circuit applied to high resolution time digital quantizer
CN109407500B (en) * 2018-11-22 2021-03-23 深圳天眼激光科技有限公司 Time interval measuring method based on FPGA
CN110244281B (en) * 2019-07-19 2021-07-23 北京一径科技有限公司 Laser radar system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104216279A (en) * 2014-09-23 2014-12-17 西安宏泰时频技术有限公司 Time interval measuring device based on FPGA (Field Programmable Gate Array)
WO2018113625A1 (en) * 2016-12-19 2018-06-28 武汉中派科技有限责任公司 Time-to-digital converter and time measurement method

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