CN112713864A - Output stage circuit for bus transfer data - Google Patents
Output stage circuit for bus transfer data Download PDFInfo
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- CN112713864A CN112713864A CN201911021772.2A CN201911021772A CN112713864A CN 112713864 A CN112713864 A CN 112713864A CN 201911021772 A CN201911021772 A CN 201911021772A CN 112713864 A CN112713864 A CN 112713864A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/52—Circuit arrangements for protecting such amplifiers
- H03F1/523—Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
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Abstract
本发明提出一种用于总线传送数据的输出级电路。输出级电路包含：高侧开关、高侧二极管结构、高侧箝位电路、低侧开关以及低侧二极管结构。总线的阻抗电路耦接于高侧开关与低侧开关之间，以根据高侧开关与低侧开关所分别产生的高侧输出信号与低侧输出信号，产生差动输出信号。高侧二极管结构的高侧N型区包覆高侧P型区，且低侧二极管结构的低侧N型区包覆低侧P型区。高侧箝位电路与高侧N型区串接，用以箝位高侧N型区的电压不低于高侧预设电压，使高侧二极管结构与P型半导体基板所形成的寄生PNP双极结型晶体管不导通。
The present invention proposes an output stage circuit for bus transmission of data. The output stage circuit includes: a high-side switch, a high-side diode structure, a high-side clamp circuit, a low-side switch and a low-side diode structure. The impedance circuit of the bus is coupled between the high-side switch and the low-side switch to generate a differential output signal according to the high-side output signal and the low-side output signal respectively generated by the high-side switch and the low-side switch. The high-side N-type region of the high-side diode structure covers the high-side P-type region, and the low-side N-type region of the low-side diode structure covers the low-side P-type region. The high-side clamping circuit is connected in series with the high-side N-type region to clamp the voltage of the high-side N-type region not lower than the high-side preset voltage, so that the high-side diode structure and the parasitic PNP formed by the P-type semiconductor substrate double The junction transistor does not conduct.
Description
Technical Field
The present invention relates to an output stage circuit for bus data transmission, and more particularly to an output stage circuit capable of withstanding positive and negative voltages.
Background
Fig. 1A shows a schematic diagram of a typical Controller Area Network (CAN) 1. The CAN 1 comprises a plurality of data transmission control circuits 11 and a bus (bus) 12. The relay data control circuit 11 includes a controller 111 and a relay circuit 113. The controller 111 controls the transceiver circuit 113 to transmit or receive data through the bus 12. The bus 12 has a high side signal line, a low side signal line, and an impedance circuit coupled therebetween. As shown in fig. 1A, the impedance circuit includes, for example, two resistors RL, and both ends of each resistor RL are electrically connected to the high-side signal line and the low-side signal line, respectively. The high-side signal line has a plurality of high-side output terminals CANH respectively coupled to the corresponding transmission data control circuits 11. The low-side signal line has a plurality of low-side output terminals CANL, which are respectively coupled to the corresponding pass data control circuits 11. In one aspect, the tx data control circuit 11 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 11 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
Fig. 1B shows a schematic diagram of the transmission data control circuit 11. In the relay data control circuit 11, the relay circuit 113 includes a driving circuit 1131, a receiver 1132 and an output stage circuit 1133. For the bus 12, different transmission data control circuits 11 transmit or receive data through the bus 12 at different time periods. When one of the transceiving data control circuits 11 transmits or receives data, the other transceiving data control circuits 11 connected to the bus 12 do not transmit or receive data through the bus 12, but the output stage circuit 1133 needs to withstand the voltages of the high-side signal line and the low-side signal line. For safety reasons, the output stage circuit 1133 must be able to withstand high positive and negative voltages, such as positive and negative 48V.
As shown in fig. 1B, the controller 111 controls the driving circuit 1131 in the transceiver circuit 113 to operate the high-side switch QH1 and the low-side switch QL1 in the output stage circuit 1133, so as to transmit data through the corresponding high-side output terminal CANH and low-side output terminal CANL. On the other hand, the transmission data control circuit 11 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL through the receiver 1132, and receives data. The high-side switch QH1 is electrically connected to the internal voltage VDD; and the low side switch QL1 is electrically connected to the reference voltage VSS.
With continued reference to fig. 1B, during the period when the data transmission control circuit 11 does not transmit data through the bus 12, the high-side output terminal CANH and the low-side output terminal CANL may have a maximum positive or negative voltage of 48V. Therefore, the high-side switch QH1 and the low-side switch QL1 must be connected in series with diodes DH1 and DL1 having withstand voltages exceeding plus and minus 48V, respectively. Furthermore, if the high-side switch QH1, the low-side switch QL1, the diodes DH1 and DL1 are formed by standard CMOS process steps, when the high-side switch QH1 or the low-side switch QL1 is operated, a relatively high current flows through the diodes DH1 or DL1, which may cause a parasitic Bipolar Junction Transistor (BJT) to be turned on, resulting in an error in the operation of the high-side switch QH1 and the low-side switch QL1, and thus an error in data transfer. Therefore, the prior art output stage circuit 1133 needs to be formed by non-standard CMOS process steps, such as Silicon On Insulator (SOI) process steps, to avoid forming parasitic BJTs.
FIG. 1C shows a schematic cross-sectional view of diode DH1/DL 1. As shown in fig. 1C, the diode DH1/DL1 is formed not in a standard CMOS process step, but in a Silicon On Insulator (SOI) process step. The diode DH1/DL1 is formed on a semiconductor substrate and has an insulating layer, a P-type region and an N-type region. Although the soi process step avoids the formation of parasitic bipolar junction transistors, it is very expensive relative to standard CMOS process steps.
Accordingly, the present invention is directed to an output stage circuit for bus transferring data, which can prevent a parasitic transistor from being turned on and reduce manufacturing costs.
Disclosure of Invention
From one aspect, the present invention provides an output stage circuit for bus data transmission formed in a P-type semiconductor substrate, the output stage circuit for generating a differential output signal at a high-side output terminal and a low-side output terminal of the bus, comprising: a high-side switch for operating according to a high-side operating signal to generate a high-side output signal, wherein the high-side switch is electrically connected to an internal voltage; a high-side diode structure connected in series with the high-side switch for transmitting the high-side output signal and blocking reverse bias, comprising: a high side P-type region electrically connected to the high side switch for receiving the high side output signal; and a high side N-type region coupled to the high side output terminal for transmitting the high side output signal, wherein the high side N-type region covers the side surface and the bottom surface of the high side P-type region to form a high side PN junction under an upper surface of the P-type semiconductor substrate, and the high side N-type region and the P-type semiconductor substrate form a high side substrate PN junction; a high side clamp circuit, which is connected in series with the high side N-type region and is used for clamping the voltage of the high side N-type region not lower than a high side preset voltage so as to make a parasitic PNP bipolar junction transistor formed by the high side diode structure and the P-type semiconductor substrate not conducted; a low side switch for operating in response to a low side operating signal to generate a low side output signal, wherein the low side switch is electrically connected to a reference voltage; and a low side diode structure connected in series with the low side switch for transmitting the low side output signal and blocking reverse bias, comprising: a low side N-type region electrically connected to the low side switch for receiving the low side output signal; and a low side P-type region coupled to the low side output for transmitting the low side output signal, the low side N-type region encapsulating sides and bottom of the low side P-type region to form a low side PN junction under the upper surface of the P-type semiconductor substrate, the low side N-type region and the P-type semiconductor substrate forming a low side substrate PN junction; wherein an impedance circuit of the bus is coupled between the high-side output terminal and the low-side output terminal to generate the differential output signal according to the high-side output signal and the low-side output signal; wherein the high-side N-type region is directly contacted with the P-type semiconductor substrate, and no insulating layer is connected between the high-side N-type region and the P-type semiconductor substrate; the low-side N-type region is in direct contact with the P-type semiconductor substrate, and no insulating layer is connected between the low-side N-type region and the P-type semiconductor substrate.
In a preferred embodiment, the high-side diode structure comprises a high-side PNP bipolar junction field effect transistor (BJT) having a base electrically connected to a collector thereof, and the high-side P-type region comprises an emitter of the high-side PNPBJT and the high-side N-type region comprises a base of the high-side PNPBJT.
In the aforementioned embodiment, the high-side PNPBJT is preferably a concentric ring zone (concentric ring zone) structure in which the emitter, the base and the collector are arranged from inside to outside, and the high-side PNPBJT further has an isolation region having N-type conductivity, which covers and electrically connects the collector, and the isolation region is in direct contact with the P-type semiconductor substrate to form the high-side PN junction.
In a preferred embodiment, the low side diode structure comprises a low side PNPBJT having its base electrically connected to its collector, and the P-type region comprises the emitter of the low side PNPBJT and the N-type region comprises the base of the low side PNPBJT.
In the aforementioned embodiments, the low side PNPBJT is preferably a concentric ring band structure with the emitter, base and collector arranged from inside to outside, and the low side PNPBJT further has an isolation region of N-type conductivity, which encapsulates and electrically connects the collector and is in direct contact with the P-type semiconductor substrate to form the low side PN junction.
In a preferred embodiment, the high-side clamp circuit includes a Field Effect Transistor (FET) having a source coupled to the high-side N-type region and a gate biased to a predetermined control voltage to limit the voltage of the high-side N-type region from being lower than the high-side predetermined voltage, and a drain electrically connected to the high-side output terminal.
In the aforementioned embodiment, the high-side clamp circuit preferably further comprises: a Zener diode coupled between the gate and the source of the P-type MOSFET to keep the P-type MOSFET conductive; a resistor connected in series with the Zener diode for limiting a current flowing through the Zener diode; and a capacitor coupled between the gate of the P-type MOSFET and ground potential for reducing coupling effect of the gate-drain capacitance of the P-type MOSFET.
In a preferred embodiment, the high side clamp circuit includes a clamp PNPBJT having an emitter coupled to the high side N-type region and a base biased to a predetermined control voltage to limit the voltage in the high side N-type region from being lower than the high side predetermined voltage, and a collector electrically connected to the high side output.
In another aspect, the present invention provides an output stage circuit for bus data transmission formed in an N-type semiconductor substrate, the output stage circuit for generating a differential output signal at a high side output terminal and a low side output terminal of the bus, comprising: a high-side switch for operating according to a high-side operating signal to generate a high-side output signal, wherein the high-side switch is electrically connected to an internal voltage; a high-side diode structure connected in series with the high-side switch for transmitting the high-side output signal and blocking reverse bias, comprising: a high side P-type region electrically connected to the high side switch for receiving the high side output signal; and a high side N-type region coupled to the high side output terminal for transmitting the high side output signal, wherein the high side P-type region covers the side and bottom surfaces of the high side N-type region to form a high side PN junction, and the high side P-type region and the N-type semiconductor substrate form a high side substrate PN junction; a low side switch for operating in response to a low side operating signal to generate a low side output signal, wherein the low side switch is electrically connected to a reference voltage; a low side diode structure connected in series with the low side switch for transmitting the low side output signal and blocking reverse bias, comprising: a low side N-type region electrically connected to the low side switch for receiving the low side output signal; and a low-side P-type region coupled to the low-side output terminal for transmitting the low-side output signal, the low-side P-type region encapsulating side and bottom surfaces of the low-side N-type region to form a low-side substrate PN junction under the upper surface of the N-type semiconductor substrate, the low-side P-type region and the N-type semiconductor substrate forming a low-side substrate PN junction; and a low side clamp circuit connected in series with the low side P-type region for clamping the voltage of the low side P-type region not higher than a low side preset voltage to make a parasitic NPN bipolar junction transistor formed by the low side diode structure and the N-type semiconductor substrate not conductive; wherein an impedance circuit of the bus is coupled between the high-side output terminal and the low-side output terminal to generate the differential output signal according to the high-side output signal and the low-side output signal; wherein the high-side P-type region is directly contacted with the N-type semiconductor substrate, and no insulating layer is connected between the high-side P-type region and the N-type semiconductor substrate; the low-side P-type region is in direct contact with the N-type semiconductor substrate, and no insulating layer is connected between the low-side P-type region and the N-type semiconductor substrate.
In a preferred embodiment, the high-side diode structure includes a high-side NPN bipolar junction field effect transistor (BJT) having a base electrically connected to a collector thereof, and the high-side P-type region includes the base of the high-side NPNBJT and the high-side N-type region includes the emitter of the high-side NPNBJT.
In a preferred embodiment, the high-side NPNBJT is a concentric ring zone (concentric zone) structure in which the emitter, base and collector are arranged from inside to outside, and the high-side NPNBJT further has an isolation region of P-type conductivity, which encloses and electrically connects the collector, and which is in direct contact with the N-type semiconductor substrate to form the high-side PN junction.
In a preferred embodiment, the low side diode structure includes a low side NPNBJT having a base electrically connected to a collector, and the low side P-type region includes the base of the low side NPNBJT and the low side N-type region includes the emitter of the low side NPNBJT.
In the aforementioned embodiments, the low-side NPNBJT is preferably a concentric ring zone (concentric zone) structure in which the emitter, base and collector are arranged from inside to outside, and the low-side NPNBJT further has an isolation region having P-type conductivity, which encapsulates and electrically connects the collector, and the isolation region is in direct contact with the N-type semiconductor substrate to form the high-side PN junction.
In a preferred embodiment, the low side clamp includes a Field Effect Transistor (FET) having a source coupled to the low side pmos and a gate biased to a predetermined control voltage to limit the low side pmos to no higher than the low side predetermined voltage, and a drain electrically connected to the low side output.
In the aforementioned embodiment, the low side clamp preferably further comprises: a Zener diode coupled between the gate and the source of the N-type MOSFET to keep the N-type MOSFET conductive; a resistor connected in series with a first voltage source for limiting a bias current flowing through the Zener diode; and a capacitor coupled between the gate of the N-type MOSFET and a second voltage source for reducing coupling effect of the gate-drain capacitance of the N-type MOSFET; wherein the voltage provided by the second voltage source is higher than the voltage provided by the first voltage source.
In a preferred embodiment, the low side clamp includes a clamp NPNBJT having an emitter coupled to the low side P-type region and a base biased to a predetermined control voltage to limit the voltage of the low side P-type region from being higher than the low side predetermined voltage, and a collector electrically connected to the low side output.
The purpose, technical content, features and effects of the present invention will be more readily understood through the following detailed description of specific embodiments.
Drawings
Fig. 1A shows a schematic diagram of a typical Controller Area Network (CAN) 1.
Fig. 1B shows a schematic diagram of the transmission data control circuit 11.
FIG. 1C shows a schematic cross-sectional view of diode structure DH1/DL 1.
Fig. 2A-2C show a first embodiment of the invention.
Fig. 3A-3G show a second embodiment of the invention.
Fig. 4 shows a third embodiment of the invention.
Fig. 5 shows a fourth embodiment of the invention.
Fig. 6A-6C illustrate a fifth embodiment of the present invention.
Fig. 7A-7G show a sixth embodiment of the invention.
Fig. 8 shows a seventh embodiment of the invention.
Fig. 9 shows an eighth embodiment of the present invention.
Description of the symbols in the drawings
1 controller area network
11,21,31,41,51,61,71,81,91 are connected with a data control circuit
12 bus
111,211,311,411,511,611,711,811,911 controller
113,213,313,413,513,613,713,813,913 transceiver circuit
1131,2131,3131,4131,5131,6131,7131,8131,9131 drive circuit
1132,2132,3132,4132,5132,6132,7132,8132,9132 receiver
1133,2133,3133,4133,5133,6133,7133,8133,9133 output stage circuit
BTS1, BTS2, BTS3 bottom plane
CANH high side output end
CANL Low-side output
CLH2, CLH3, CLH4, CLH5 high side clamp circuits
CLL6, CLL7, CLL8.CLL9 Low side Clamp
CP capacitance
High-side diode structures of DH1, DH2, DH3, DH4, DH5, DH6, DH7, DH8 and DH9
DH2N1, DH2N2, DH2N3 high-side N type subregion
High side P type region of DH2P1
DH6P1, DH6P2, DH6P3 high-side P type subregion
High-side N-type region of DH6N2
DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9 low side diode structure
DL2N1, DL2N2, DL2N3 low side N type subregion
DL2P1 low side P type region
DL6N1 low side N-type region
DL6P1, DL6P2, DL6P3 low side P type subregion
DP diode
Preset control voltage of GH, GL
GND ground potential
MHNC, MLPC channel
MHPD, MLND drain
MHPS, MLNS source
NBL N-type buried layer
NISO, PISO exclusion zone
High side operation signals of OPH1, OPH2, OPH3, OPH4, OPH5, OPH6, OPH7 and OPH8
OPL1, OPL2, OPL3, OPL4, OPL5, OPL6, OPL7, OPL8 low side operating signals
QH1, QH2, QH3, QH4, QH5, QH6, QH7, QH8, QH9 high-side switches
QL1, QL2, QL3, QL4, QL5, QL6, QL7, QL8, QL9 low side switches
PBL P-type buried layer
POLY grid
RL, RP resistance
SDS1, SDS2, SDS3 flank
THNB, THPB base
THNC, THPC collector
THEN, THPE emitter
UPS1, UPS2, UPS3, UPS4, UPS5, UPS6 and UPS7 upper surface
VDD internal Voltage
VP, VP1, VP2 voltage source
VSS reference voltage
ZD zener diode
Detailed Description
The foregoing and other technical and scientific aspects, features and advantages of the present invention will be apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings. The drawings are schematic and are intended to show the coupling relationship between circuits and the relationship between circuits or device layers, and the shapes, thicknesses and widths of the circuits and the device layers are not drawn to scale.
Please refer to fig. 2A-2C, which illustrate a first embodiment of the present invention. Fig. 2A shows a circuit schematic of an output stage 21 for bus transferring data according to the present invention. As shown in fig. 2A, the output stage circuit 21 includes a controller 211 and a transceiver circuit 213. The controller 211 controls the transceiver circuit 213 to transmit (transmit) or receive (receive) data over a bus (not shown, as described above for bus 12). The bus has a high side signal line, a low side signal line, and an impedance circuit coupled therebetween. For example, as shown in fig. 1A, the impedance circuit includes two resistors RL, and two ends of each resistor RL are electrically connected to the high-side signal line and the low-side signal line, respectively. In the present embodiment, the high-side signal line has a plurality of high-side output terminals CANH respectively coupled to the corresponding transmission data control circuits 21. The low-side signal line has a plurality of low-side output terminals CANL, which are respectively coupled to the corresponding pass data control circuits 21. In one aspect, the tx data control circuit 21 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 21 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
With reference to fig. 2A, in the transceiver circuit 21, the transceiver circuit 213 includes a driving circuit 2131, a receiver 2132 and an output stage circuit 2133. Different transmission data control circuits 21 transmit or receive data through the bus at different time periods. When one of the transceiving data control circuits 21 transmits or receives data, the other transceiving data control circuit 21 connected to the bus does not transmit or receive data through the bus, but the output stage circuit 2133 needs to withstand the voltages of the high-side signal line and the low-side signal line. For safety reasons, the output stage circuit 2133 must be able to withstand relatively high positive and negative voltages, for example, positive and negative 48V.
As shown in fig. 2A, the controller 211 controls the driving circuit 2131 of the transceiver circuit 213 to operate the high-side switch QH2 and the low-side switch QL2 of the output stage circuit 2133, so as to transmit data through the corresponding high-side output terminal CANH and the low-side output terminal CANL. On the other hand, the transmission data control circuit 21 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL through the receiver 2132 to receive data.
With reference to fig. 2A, the output stage circuit 2133 for bus data transmission is formed in the P-type semiconductor substrate, and the output stage circuit 2133 is used for generating differential output signals at the high side output terminal CANH and the low side output terminal CANL of the bus. The output stage circuit 2133 includes a high-side switch QH2, a high-side diode structure DH2, a high-side clamp CLH2, a low-side switch QL2, and a low-side diode structure DL 2. The high-side switch QH2 is, for example but not limited to, a PNP Bipolar Junction Transistor (BJT) as shown in the figure, and is configured to operate according to a high-side operation signal OPH1 received by a base thereof to generate a high-side output signal (in the present embodiment, indicated by a collector voltage), wherein the high-side switch QH2 is electrically connected to an internal voltage VDD (in the present embodiment, indicated by an emitter electrically connected to the internal voltage VDD). The internal voltage VDD is, for example, but not limited to, 5V.
The high-side diode structure DH2 is connected in series with the high-side switch QH2 for transmitting the high-side output signal and blocking the reverse bias. As shown in fig. 2B, the high-side diode structure DH2 has a high-side P-type region DH2P1 and a high-side N-type region. Wherein the high-side N-type region comprises high-side N-type sub-regions DH2N1, DH2N2 and DH2N 3. The high-side N-type sub-region DH2N3 is, for example but not limited to, an N-type buried layer (N-type buried layer) formed on a P-type semiconductor substrate, which is well known in the art and will not be described herein. The high-side P-type region DH2P1 is electrically connected to the high-side switch QH2 to receive a high-side output signal. The high-side N-type region is coupled to the high-side output terminal CANH for transmitting a high-side output signal to the high-side output terminal CANH, and under the upper surface UPS1 of the P-type semiconductor substrate, the high-side N-type region (composed of the high-side N-type sub-regions DH2N1, DH2N2 and DH2N3) wraps the side SDS1 and the bottom BTS1 of the high-side P-type region DH2P1 to form a high-side PN junction (as indicated by a thick black dashed line in fig. 2B). And the high-side N-type region and the P-type semiconductor substrate form a high-side substrate PN junction (as illustrated by the thick black solid line in fig. 2B). The P-type semiconductor substrate is electrically connected to the ground potential GND, the high-side N-type region is in direct contact with the P-type semiconductor substrate, and no insulating layer is connected between the high-side N-type region and the P-type semiconductor substrate. For example, the high-side diode structure DH2 is formed by standard CMOS process steps, which do not include SOI process steps.
The voltage of the high-side N-type region must be maintained not lower than the high-side predetermined voltage to prevent the parasitic PNPBJT (as indicated by the dashed line PNPBJT in fig. 2B) from turning on under various conditions. For example: when a large current flows through the high-side diode structure DH2, the parasitic PNPBJT is turned on, or when the voltage at the high-side output terminal CANH is a negative voltage, the parasitic PNPBJT is turned on. In detail, when the voltage at the high-side output terminal CANH is a negative voltage, the voltage at the base of the parasitic PNPBJT (N-type sub-region DH2N3) is lower than the voltage at the collector with 0V or the ground potential GND (i.e., the P-type semiconductor substrate, which is electrically connected to 0V or the ground potential GND in this embodiment and other embodiments), so that the parasitic PNPBJT is turned on. According to the present invention, the high side clamp circuit CLH2 is serially connected to the high side N-type region for clamping the voltage of the high side N-type region not lower than the high side predetermined voltage, so that the parasitic PNPBJT formed by the high side diode structure DH2 and the P-type semiconductor substrate is not conducted.
For example, as shown in fig. 2A, the high-side clamp circuit CLH2 includes a P-type Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) having a source coupled to the high-side N-type region and a gate biased to a predetermined control voltage GH for limiting the voltage of the high-side N-type region from being not lower than a predetermined high-side voltage, and a drain electrically connected to the high-side output terminal CANH. The predetermined control voltage GH is, for example, but not limited to, 0V or the ground potential GND. For example, when the gate-source voltage Vgs of the P-type MOSFET is higher than 1V, the P-type MOSFET is not turned on, and therefore, when the preset control voltage GH is 0V, and the high-side N-type region voltage is not lower than the high-side preset voltage, for example, 1V, the P-type MOSFET is kept turned on; when the voltage of the high-side N-type region is lower than the high-side preset voltage by 1V, the P-type MOSFET is not conducted so as to prevent the voltage of the high-side N-type region from being lower than the high-side preset voltage by 1V. Thus, the parasitic PNPBJT conduction is further avoided.
It should be noted that the standard CMOS process step refers to a process step for forming a semiconductor device on a silicon substrate, which includes oxidation (oxidation), photolithography (lithography), etching (etch), ion implantation (ion implantation), diffusion (diffusion), and other process steps, and excludes special process steps, such as SOI process steps, which are well known to those skilled in the art and are not described herein.
It should be noted that the high-side diode structure DH2 is used for blocking the reverse bias voltage for the high-side diode structure DH 2. An ideal diode has zero resistance between the two electrodes (anode and cathode) when conducting in the forward direction and infinite resistance when conducting in the reverse direction, i.e. current is allowed to flow through the diode from only one direction. In a diode formed by connecting a P-type region and an N-type region to form a PN junction, the P-type region is an anode and the N-type region is a cathode. A negative voltage, i.e., a reverse bias voltage, is applied to the anode (P-type region) side with respect to the cathode (N-type region), and the applied voltage is a reverse bias voltage. This is well known to those skilled in the art and will not be described in detail herein.
The low-side switch QL2 is, for example but not limited to, a PNP Bipolar Junction Transistor (BJT) as shown in fig. 2A, and is configured to operate according to a low-side operation signal OPL1 to generate a low-side output signal (in the present embodiment, illustrated by an emitter voltage), wherein the low-side switch QL2 is electrically connected to a reference voltage VSS (in the present embodiment, illustrated by a collector electrically connected to the reference voltage VSS). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND.
As shown in fig. 2A, the low-side diode structure DL2 is connected in series with the low-side switch QL2 for transmitting the low-side output signal and blocking the reverse bias. As shown in fig. 2C, the low side diode structure DL2 has a low side N-type region and a low side P-type region DL2P 1. The low-side N-type region is composed of low-side N-type sub-regions DL2N1, DL2N2 and DL2N 3. The low-side N-type sub-region DL2N3 is, for example but not limited to, an N-type buried layer (N-type buried layer) formed on a P-type semiconductor substrate, which is well known in the art and will not be described herein. The low side N-type region is electrically connected with the low side switch QL2 to receive the low side output signal. Low side P-type region DL2P1 is coupled to low side output terminal CANL for transmitting a low side output signal to low side output terminal CANL, and covers side SDS2 and bottom BTS2 of low side P-type region DL2P1 under upper surface UPS2 of the P-type semiconductor substrate to form a low side PN junction (as illustrated by the bold dashed black line in fig. 2C). And the low-side N-type region and the P-type semiconductor substrate form a low-side substrate PN junction (as illustrated by the solid bold line in fig. 2C). The resistor RL of the bus impedance circuit is coupled between the high-side output terminal CANH and the low-side output terminal CANL to generate a differential output signal according to the high-side output signal and the low-side output signal. The low-side N-type region is directly contacted with the P-type semiconductor substrate, and the non-insulating layer is connected between the low-side N-type region and the P-type semiconductor substrate. For example, the low side diode structure DL2 is formed by standard CMOS process steps, which do not include SOI process steps.
It should be noted that the low side diode structure DL2 is used to block the reverse bias voltage in the low side diode structure DL 2.
Fig. 3A-3G show a second embodiment of the present invention. Fig. 3A shows a circuit schematic of an output stage 31 for bus transferring data according to the present invention. As shown in fig. 3A, the output stage circuit 31 includes a controller 311 and a transceiver circuit 313. The controller 311 controls the transceiver circuit 313 to transmit (transmit) or receive (receive) data via a bus (not shown, as described above for bus 12). The bus has a high side signal line, a low side signal line, and an impedance circuit coupled therebetween. For example, as shown in fig. 1A, the impedance circuit includes two resistors RL, and two ends of each resistor RL are electrically connected to the high-side signal line and the low-side signal line, respectively. The high-side signal line has a plurality of high-side output terminals CANH respectively coupled to the corresponding transmission data control circuits 31. The low-side signal line has a plurality of low-side output terminals CANL, which are respectively coupled to the corresponding pass data control circuits 31. In one aspect, the tx data control circuit 31 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 31 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
Referring to fig. 3A, in the relay data control circuit 21, the relay circuit 313 includes a driving circuit 3131, a receiver 3132, and an output stage circuit 3133. Different forwarding data control circuits 31 transmit or receive data through the bus at different time periods. When one of the transceiving data control circuits 31 transmits or receives data, the other transceiving data control circuit 31 connected to the bus does not transmit or receive data through the bus, but the output stage circuit 3133 needs to withstand the voltages of the high-side signal line and the low-side signal line. For safety reasons, the output stage 3133 must be able to withstand high positive and negative voltages, for example, a voltage of plus or minus 48V.
As shown in fig. 3A, the controller 311 controls the driving circuit 3131 in the transceiver circuit 313 to operate the high-side switch QH3 and the low-side switch QL3 in the output stage circuit 3133, so as to transmit data through the corresponding high-side output terminal CANH and low-side output terminal CANL. On the other hand, the tx data control circuit 31 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL through the receiver 3132 to receive the data.
Referring to fig. 3A, the output stage 3133 for bus data transmission is formed in the P-type semiconductor substrate, and the output stage 3133 is configured to generate a differential output signal at the high side output terminal CANH and the low side output terminal CANL of the bus. The output stage circuit 3133 includes a high-side switch QH3, a high-side diode structure DH3, a high-side clamp CLH3, a low-side switch QL3, and a low-side diode structure DL 3. The high-side switch QH3, such as but not limited to a P-type Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) as shown, is configured to operate according to a high-side operation signal OPH2 received by a gate thereof to generate a high-side output signal (in the present embodiment, indicated by a drain voltage), wherein the high-side switch QH3 is electrically connected to the internal voltage VDD (in the present embodiment, indicated by a source electrically connected to the internal voltage VDD). The internal voltage VDD is, for example, but not limited to, 5V.
The high-side diode structure DH3 is connected in series with the high-side switch QH3 for transmitting the high-side output signal and blocking the reverse bias. As shown in fig. 3A, the high-side diode structure DH3 includes, for example but not limited to, a high-side PNP bipolar junction field effect transistor (BJT), whose base is electrically connected to its collector, and the P-type region includes the emitter of the high-side PNPBJT and the N-type region includes the base of the high-side PNPBJT. As shown in fig. 3A, in the high-side diode structure DH3, the dotted line PNPBJT indicates the parasitic PNPBJT of the high-side PNPBJT, and the collector thereof is a P-type semiconductor substrate and is electrically connected to the ground potential GND.
Fig. 3B and fig. 3C respectively show a top view and a cross-sectional view of the high side diode structure DH3 according to the embodiment. As shown in fig. 3B and 3C, the high-side diode structure DH3 includes a high-side PNP bipolar junction field effect transistor (BJT), as indicated by the bold black dashed transistor symbol in fig. 3C. In a preferred embodiment, as shown in fig. 3B, the high-side PNPBJT is a concentric ring zone (concentric zone) structure, in which the P-type emitter THPE, the N-type base THNB and the P-type collector THPC are arranged from inside to outside, and the high-side PNPBJT further has an isolation region NISO and an N-type buried layer NBL. The isolation region NISO and the N-type buried layer NBL have N-type conductivity, are located outside the collector THPC, and cover and electrically connect the collector THPC. The isolation region NISO and the buried N-type layer NBL are in direct contact with the P-type semiconductor substrate to form a high-side PN junction (as illustrated by the thick black solid line in fig. 3C). The isolation region NISO and the N-type buried layer NBL are in direct contact with the P-type semiconductor substrate, and no insulating layer is connected between the isolation region NISO and the N-type buried layer NBL and the P-type semiconductor substrate.
As illustrated in fig. 3C, the base THNB of the high-side PNPBJT is electrically connected to the collector THPC and to the isolation region NISO. And the high-side P-type region of the high-side diode structure DH3 includes the emitter THPE of the high-side PNPBJT. The high-side N-type region of the high-side diode structure DH3 includes a base THNB of the high-side PNPBJT, an isolation region NISO and an N-type buried layer NBL. The high-side P-type region includes an emitter THPE electrically connected to high-side switch QH3 to receive the high-side output signal. The high side N-type region is coupled to the high side output terminal CANH for transmitting a high side output signal to the high side output terminal CANH, and covers the side and bottom surfaces of the high side P-type region under the UPS3 on the upper surface of the P-type semiconductor substrate to form a high side PN junction. And the high-side N-type region and the P-type semiconductor substrate form a high-side substrate PN junction. The high-side N-type region is directly contacted with the P-type semiconductor substrate, and no insulating layer is connected between the high-side N-type region and the P-type semiconductor substrate. For example, the high-side diode structure DH3 is formed by standard CMOS process steps, which do not include SOI process steps.
The voltage of the high-side N-type region must be maintained not lower than the high-side predetermined voltage to prevent the parasitic PNPBJT (as indicated by the dashed line PNPBJT in fig. 3C) from turning on under various conditions. For example: when a large current flows through the high-side diode structure DH3, the parasitic PNPBJT is turned on, or when the voltage at the high-side output terminal CANH is a negative voltage, the parasitic PNPBJT is turned on. In detail, when the voltage at the high-side output terminal CANH is a negative voltage, the voltage at the base (N-type buried layer NBL) of the parasitic PNPBJT is lower than the voltage at the collector (i.e., P-type semiconductor substrate) having 0V or the ground potential GND, which causes the parasitic PNPBJT to turn on. According to the present invention, the high side clamp circuit CLH3 is serially connected to the high side N-type region for clamping the voltage of the high side N-type region not lower than the high side predetermined voltage, so that the parasitic PNPBJT formed by the high side diode structure DH3 and the P-type semiconductor substrate is not conducted.
For example, as shown in fig. 3A, the high-side clamp circuit CLH3 includes a P-type Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) having a source coupled to the high-side N-type region and a gate biased to a predetermined control voltage GH for limiting the voltage of the high-side N-type region from being not lower than a predetermined high-side voltage, and a drain electrically connected to the high-side output terminal CANH. The predetermined control voltage GH is, for example, but not limited to, 0V or the ground potential GND. For example, when the gate-source voltage Vgs of the P-type MOSFET is higher than 1V, the P-type MOSFET is not turned on, and therefore, when the preset control voltage GH is 0V, and the high-side N-type region voltage is not lower than the high-side preset voltage, for example, 1V, the P-type MOSFET is kept turned on; when the voltage of the high-side N-type region is lower than the high-side preset voltage by 1V, the P-type MOSFET is not conducted so as to prevent the voltage of the high-side N-type region from being lower than the high-side preset voltage by 1V. Thus, the parasitic PNPBJT conduction is further avoided.
It should be noted that the high-side diode structure DH3 is used for blocking the reverse bias voltage for the high-side diode structure DH 3.
The low-side switch QL3, such as but not limited to a Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) as shown in fig. 3A, is configured to operate according to a low-side operating signal OPL2 received by a gate thereof to generate a low-side output signal (in the present embodiment, illustrated by a source voltage), wherein the low-side switch QL3 is electrically connected to a reference voltage VSS (in the present embodiment, illustrated by a drain electrically connected to the reference voltage VSS). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND.
As shown in fig. 3A, the low side diode structure DL3 is connected in series with the low side switch QL3 for transmitting the low side output signal and blocking the reverse bias. Fig. 3D and fig. 3E respectively show a top view and a cross-sectional view of the low side diode structure DL3 in the present embodiment. As shown in fig. 3D and 3E, the low side diode structure DL3 includes a low side PNP bipolar junction field effect transistor (BJT), as illustrated by the thick black dashed transistor symbol in fig. 3E. In a preferred embodiment, as illustrated in fig. 3D, the low side PNPBJT is a concentric ring-and-ring (concentric ring) structure, in which the P-type emitter TLPE, the N-type base TLNB and the P-type collector TLPC are arranged from inside to outside, and the low side PNPBJT further has an isolation region NISO and an N-type buried layer NBL. The isolation region NISO and the N-type buried layer NBL have N-type conductivity, and are located outside the collector TLPC and wrap and electrically connect the collector TLPC. The isolation region NISO and the N-type buried layer NBL are in direct contact with the P-type semiconductor substrate to form a low-side PN junction (as illustrated by the thick black solid line in fig. 3E). The isolation region NISO and the N-type buried layer NBL are in direct contact with the P-type semiconductor substrate, and no insulating layer is connected between the isolation region NISO and the N-type buried layer NBL and the P-type semiconductor substrate. The P-type semiconductor substrate is electrically connected to, for example, but not limited to, the ground potential GND.
As illustrated in fig. 3E, the base TLNB of the low side PNPBJT is electrically connected to the collector TLPC and to the isolation region NISO. And the low side P-type region of the low side diode structure DL3 comprises the emitter TLPE of the low side PNPBJT. The low side N-type region of the low side diode structure DL3 includes a base TLNB of the low side PNPBJT, an isolation region NISO and an N-type buried layer NBL. The low side P-type region includes an emitter TLPE electrically connected to the low side switch QL3 to receive the low side output signal. The low side N-type region is coupled to the low side output terminal CANL to transmit a high side output signal to the low side output terminal CANL, and covers the side and bottom surfaces of the low side P-type region under the upper surface of the P-type semiconductor substrate to form a low side PN junction. And the low-side N-type region and the P-type semiconductor substrate form a low-side substrate PN junction. The low-side N-type region is directly contacted with the P-type semiconductor substrate, and the non-insulating layer is connected between the low-side N-type region and the P-type semiconductor substrate. For example, the low side diode structure DL3 is formed by standard CMOS process steps, which do not include SOI process steps.
The low-side switch QL3, such as but not limited to a P-type Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) shown in fig. 3A, is configured to operate according to a low-side operating signal OPL2 to generate a low-side output signal (illustrated by a source voltage in the present embodiment), wherein the low-side switch QL3 is electrically connected to a reference voltage VSS (illustrated by a drain electrically connected to the reference voltage VSS in the present embodiment). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND.
It should be noted that the low side diode structure DL3 is used to block the reverse bias voltage in the low side diode structure DL 3.
Fig. 3F and fig. 3G respectively show a top view and a cross-sectional view of the high side clamp circuit CLH3 in this embodiment. As shown in fig. 3F and 3G, the high side clamp CLH3 includes a P-type MOSFET having a gate POLY. In a preferred embodiment, as shown in fig. 3F, the high-side clamp CLH3 is a concentric ring-shaped (concentric zone) structure, in which the P-type source MHPS, the N-type channel MHNC and the P-type drain MHPD are arranged from inside to outside, and the high-side clamp CLH3 further has an isolation region NISO and a buried N-type layer NBL. The isolation region NISO and the N-type buried layer NBL have N-type conductivity, are located outside the drain MHPD and wrap and are electrically connected with the P-type drain MHPD. The isolation region NISO and the buried N-type layer NBL are in direct contact with the P-type semiconductor substrate to form a high-side PN junction (as illustrated by the solid bold line in fig. 3G). The isolation region NISO and the N-type buried layer NBL are in direct contact with the P-type semiconductor substrate, and no insulating layer is connected between the isolation region NISO and the N-type buried layer NBL and the P-type semiconductor substrate. For example, high side clamp CLH3 is formed from standard CMOS process steps, which do not include SOI process steps.
Fig. 4 shows a third embodiment of the invention. Fig. 4 shows a circuit schematic of an output stage 41 for bus transferring data according to the present invention. As shown in fig. 4, the output stage circuit 41 includes a controller 411 and a transceiver circuit 413. The controller 411 controls the transceiver circuit 413 to transmit or receive data through a bus (not shown, such as the bus 12 described above). In one aspect, the tx data control circuit 41 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 41 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
With reference to fig. 4, in the transceiver circuit 41, the transceiver circuit 413 includes a driving circuit 4131, a receiver 4132 and an output stage circuit 4133. As shown, the controller 411 controls the driving circuit 4131 in the transceiver circuit 413 to operate the high-side switch QH4 and the low-side switch QL4 in the output stage circuit 4133 to transmit data through the corresponding high-side output terminal CANH and low-side output terminal CANL. On the other hand, the transmission data control circuit 41 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL through the receiver 4132 to receive data.
With reference to fig. 4, the output stage circuit 4133 for bus data transmission is formed in the P-type semiconductor substrate, and the output stage circuit 4133 is configured to generate differential output signals at the high side output terminal CANH and the low side output terminal CANL of the bus. The output stage circuit 4133 includes a high-side switch QH4, a high-side diode structure DH4, a high-side clamp CLH4, a low-side switch QL4, and a low-side diode structure DL 4. The high-side switch QH4, such as but not limited to a P-type Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) as shown, is configured to operate according to a high-side operation signal OPH3 received by a gate thereof to generate a high-side output signal (in the present embodiment, indicated by a drain voltage), wherein the high-side switch QH4 is electrically connected to the internal voltage VDD (in the present embodiment, indicated by a source electrically connected to the internal voltage VDD). The internal voltage VDD is, for example, but not limited to, 5V.
The high-side diode structure DH4 is connected in series with the high-side switch QH4 for transmitting the high-side output signal and blocking the reverse bias. As shown in fig. 4, the high-side diode structure DH4 includes, for example but not limited to, a high-side PNP bipolar junction field effect transistor (BJT), whose base is electrically connected to its collector, and the P-type region includes the emitter of the high-side PNPBJT and the N-type region includes the base of the high-side PNPBJT. As shown in fig. 4, in the high-side diode structure DH4, the dotted line PNPBJT indicates the parasitic PNPBJT of the high-side PNPBJT, and the collector thereof is a P-type semiconductor substrate and is electrically connected to the ground potential GND.
It should be noted that the high-side diode structure DH4 is used for blocking the reverse bias voltage for the high-side diode structure DH 4.
The low-side switch QL4, such as but not limited to a Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) as shown in fig. 4, is configured to operate according to a high-side operating signal OPL3 received by a gate thereof to generate a low-side output signal (in the present embodiment, illustrated by a source voltage), wherein the low-side switch QL4 is electrically connected to a reference voltage VSS (in the present embodiment, illustrated by a drain electrically connected to the reference voltage VSS). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND.
As shown in fig. 4, the low side diode structure DL4 is connected in series with the low side switch QL4 for transmitting the low side output signal and blocking the reverse bias. The low-side switch QL4, such as but not limited to a Field Effect Transistor (FET) as shown in fig. 4, is configured to operate according to a low-side operating signal OPL3 to generate a low-side output signal (illustrated by a source voltage in the present embodiment), wherein the low-side switch QL3 is electrically connected to a reference voltage VSS (illustrated by a drain electrically connected to the reference voltage VSS in the present embodiment). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND.
As shown in fig. 4, the low side diode structure DL4 is connected in series with the low side switch QL4 for transmitting the low side output signal and blocking the reverse bias. In this implementation, low side diode structure DL4 includes a low side PNP bipolar junction field effect transistor (BJT). In a preferred embodiment, the low-side PNPBJT is a concentric ring (concentric ring) structure in which a P-type emitter, an N-type base and a P-type collector are arranged from inside to outside, and the low-side PNPBJT further has an isolation region and an N-type buried layer. The isolation region and the N-type buried layer have N-type conductivity, are located outside the collector and wrap and are electrically connected with the collector. The isolation region is in direct contact with the N-type buried layer and the P-type semiconductor substrate to form a low-side PN junction. The isolation region is directly contacted with the N-type buried layer and the P-type semiconductor substrate, and no insulating layer is connected between the isolation region and the N-type buried layer and the P-type semiconductor substrate.
The base of the low side PNPBJT is electrically connected to the collector and to the isolation region. And the low side P-type region of low side diode structure DL4 includes the emitter of low side PNPBJT. The low side N-type region of the low side diode structure DL4 includes the base of the low side PNPBJT, the isolation region and the N-type buried layer. The low side P-type region includes an emitter electrically connected to the low side switch QL4 for receiving the low side output signal. The low side N-type region is coupled to the low side output terminal CANL to transmit a high side output signal to the low side output terminal CANL, and covers the side and bottom surfaces of the low side P-type region under the upper surface of the P-type semiconductor substrate to form a low side PN junction. And the low-side N-type region and the P-type semiconductor substrate form a low-side substrate PN junction. The low-side N-type region is directly contacted with the P-type semiconductor substrate, and the non-insulating layer is connected between the low-side N-type region and the P-type semiconductor substrate. For example, the low side diode structure DL4 is formed by standard CMOS process steps, which do not include SOI process steps.
The low side diode structure DL4 has the same structure as the low side diode structure DL3, and reference can be made to the low side diode structure DL3 shown in fig. 3D and 3E. It should be noted that the low side diode structure DL4 is used to block the reverse bias voltage in the low side diode structure DL 4.
The difference between this embodiment and the second embodiment is that in this embodiment, the high-side clamp CLH4 preferably further includes a zener diode ZD, a resistor RP, a capacitor CP, a voltage source VP, and a diode DP. The zener diode ZD is coupled between the gate and the source of the P-type MOSFET of the high-side clamp CLH4, for example, to maintain the source-gate voltage (Vsg) of the P-type MOSFET at 5V, so as to keep the P-type MOSFET turned on. The resistor RP is connected in series with the zener diode ZD to limit the current flowing through the zener diode ZD when the voltage at the high-side output terminal CANH is too high. For example, when the voltage at the high-side output terminal CANH is 58V, the current flowing through the zener diode ZD is the highest: (58-Vzd-Vp)/Rp, where Vzd is the breakdown voltage of the Zener diode ZD, Vp is the voltage provided by the voltage source VP, and Rp is the resistance of the resistor RP. The capacitor CP is coupled between the gate of the P-type MOSFET of the high-side clamp CLH4 and the ground potential GND for reducing the coupling effect (coupling effect) of the gate-drain capacitance of the P-type MOSFET of the high-side clamp CLH 4. The voltage source VP is connected in series with the resistor RP, and the voltage source VP is connected in series with the resistor RP and then connected in parallel with the capacitor CP. The voltage source VP is used for providing a predetermined bias voltage to the capacitor CP, for example, a predetermined voltage source voltage higher than the ground potential GND, when the transmission data control circuit 41 transmits data through the high-side output terminal CANH. Assuming that the voltage source VP does not provide the predetermined bias voltage for the capacitor CP, and the gate is electrically connected to the ground potential GND, the gate voltage will be changed from the ground potential GND to the negative voltage due to the gate-drain capacitance coupling effect of the P-type MOSFET of the high-side clamp CLH4 during the process of the voltage at the high-side output terminal CANH decreasing from the positive voltage to the negative voltage. Therefore, the voltage source VP provides a predetermined bias voltage for the capacitor CP, which prevents the capacitor CP from transforming from the ground potential GND to a negative voltage, thereby reducing the gate-drain capacitance coupling effect of the P-type MOSFET of the high-side clamp CLH 4. The diode DP is connected in parallel with the capacitor CP to provide a current recovery path (recovery path) when the gate voltage of the P-type MOSFET of the high-side clamp CLH4 is lower than the threshold voltage.
Fig. 5 shows a fourth embodiment of the invention. Fig. 5 shows a circuit schematic of an output stage circuit 51 for bus transferring data according to the present invention. As shown in fig. 5, the output stage circuit 51 includes a controller 511 and a transceiver circuit 513. Controller 511 controls transceiver circuit 513 to transmit (transmit) or receive (receive) data over a bus (not shown, as previously described for bus 12). In one aspect, the pass data control circuit 51 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 51 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
Referring to fig. 5, in the transceiver circuit 51, the transceiver circuit 513 includes a driving circuit 5131, a receiver 5132 and an output stage circuit 5133. Different transmission data control circuits 51 transmit or receive data through the bus at different time periods. As shown in fig. 5, the controller 511 controls the driving circuit 5131 in the transceiver circuit 513 to operate the high-side switch QH5 and the low-side switch QL5 in the output stage circuit 5133, so as to transmit data through the corresponding high-side output terminal CANH and low-side output terminal CANL. On the other hand, the transmission data control circuit 51 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL through the receiver 5132 to receive data.
With reference to fig. 5, the output stage circuit 5133 for bus data transmission is formed in the P-type semiconductor substrate, and the output stage circuit 5133 is configured to generate differential output signals at the high side output terminal CANH and the low side output terminal CANL of the bus. The output stage circuit 5133 includes a high-side switch QH5, a high-side diode structure DH5, a high-side clamp CLH5, a low-side switch QL5, and a low-side diode structure DL 5. The high-side switch QH5 is, for example but not limited to, a PNP Bipolar Junction Transistor (BJT) as shown in the figure, and is configured to operate according to a high-side operation signal OPH4 received by a base thereof to generate a high-side output signal (in the present embodiment, indicated by a collector voltage), wherein the high-side switch QH5 is electrically connected to an internal voltage VDD (in the present embodiment, indicated by an emitter electrically connected to the internal voltage VDD). The internal voltage VDD is, for example, but not limited to, 5V.
The high-side diode structure DH5 is connected in series with the high-side switch QH5 for transmitting the high-side output signal and blocking the reverse bias. It should be noted that the high-side diode structure DH5 is used for blocking the reverse bias voltage for the high-side diode structure DH 5.
The difference between this embodiment and the first embodiment is that, in this embodiment, as shown in fig. 5, the high-side clamp circuit CLH5 includes a PNP Bipolar Junction Transistor (BJT) as shown, an emitter of the BJT is coupled to the high-side N-type region of the high-side diode structure DH5, a base of the BJT is biased to a predetermined control voltage GH for limiting the voltage of the high-side N-type region from not lower than the high-side predetermined voltage, and a collector of the BJT is electrically connected to the high-side output terminal CANH. The predetermined control voltage GH is, for example, but not limited to, 0V or the ground potential GND.
The low-side switch QL5 is, for example but not limited to, a PNP Bipolar Junction Transistor (BJT) as shown in fig. 5, and is configured to operate according to a low-side operation signal OPL4 to generate a low-side output signal (in the present embodiment, illustrated by an emitter voltage), wherein the low-side switch QL5 is electrically connected to a reference voltage VSS (in the present embodiment, illustrated by a collector electrically connected to the reference voltage VSS). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND. The low side diode structure DL5 is connected in series with the low side switch QL5 for transmitting the low side output signal and blocking reverse bias. It should be noted that the low side diode structure DL5 is used to block the reverse bias voltage in the low side diode structure DL 5.
Please refer to fig. 6A-6C, which illustrate a fifth embodiment of the present invention. Fig. 6A shows a circuit schematic of an output stage circuit 61 for bus transferring data according to the present invention. As shown in fig. 6A, the output stage circuit 61 includes a controller 611 and a transceiver circuit 613. The controller 611 controls the transceiver circuitry 613 to transmit (transmit) or receive (receive) data over a bus (not shown, such as the bus 12 described above). The bus has a high side signal line, a low side signal line, and an impedance circuit coupled therebetween. For example, as shown in fig. 1A, the impedance circuit includes two resistors RL, and two ends of each resistor RL are electrically connected to the high-side signal line and the low-side signal line, respectively. In the present embodiment, the high-side signal line has a plurality of high-side output terminals CANH respectively coupled to the corresponding transmission data control circuits 61. The low-side signal line has a plurality of low-side output terminals CANL, which are respectively coupled to the corresponding pass data control circuits 61. In one aspect, the pass data control circuit 61 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 61 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
Referring to fig. 6A, in the receive data control circuit 61, the transceiver circuit 613 includes a driving circuit 6131, a receiver 6132 and an output stage circuit 6133. Different transmission data control circuits 61 transmit or receive data through the bus at different time periods. When one of the transceiving data control circuits 61 transmits or receives data, the other transceiving data control circuit 61 connected to the bus does not transmit or receive data through the bus, but the output stage circuit 6133 needs to bear the voltages of the high-side signal line and the low-side signal line. For safety reasons, the output stage circuit 6133 must be able to withstand high positive and negative voltages, such as positive and negative 48V.
As shown in fig. 6A, the controller 611 controls the driving circuit 6131 in the transceiver circuit 613 to operate the high-side switch QH6 and the low-side switch QL6 in the output stage circuit 6133, so as to transmit data through the corresponding high-side output terminal CANH and low-side output terminal CANL. On the other hand, the transmission data control circuit 61 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL through the receiver 6132 to receive data.
With reference to fig. 6A, the output stage circuit 6133 for bus data transmission is formed in the N-type semiconductor substrate, and the output stage circuit 6133 is used for generating differential output signals at the high side output terminal CANH and the low side output terminal CANL of the bus. The output stage circuit 6133 includes a high-side switch QH6, a high-side diode structure DH6, a low-side clamp CLL6, a low-side switch QL6, and a low-side diode structure DL 6. The high-side switch QH6 is, for example but not limited to, a PNP Bipolar Junction Transistor (BJT) as shown in the figure, and is configured to operate according to a high-side operation signal OPH5 received by a base thereof to generate a high-side output signal (in the present embodiment, indicated by a collector voltage), wherein the high-side switch QH6 is electrically connected to an internal voltage VDD (in the present embodiment, indicated by an emitter electrically connected to the internal voltage VDD). The internal voltage VDD is, for example, but not limited to, 5V.
The high-side diode structure DH6 is connected in series with the high-side switch QH6 for transmitting the high-side output signal and blocking the reverse bias. As shown in fig. 6B, the high-side diode structure DH6 has a high-side P-type region and a high-side N-type region DH6N 1. Wherein the high-side P-type region comprises high-side P-type sub-regions DH6P1, DH6P2 and DH6P 3. The high-side P-type sub-region DH6P3 is, for example but not limited to, a P-type buried layer (P-type buried layer) formed on an N-type semiconductor substrate, which is well known in the art and will not be described herein. The high-side P-type region is electrically connected to high-side switch QH6 to receive the high-side output signal. The high-side N-type region DH6N1 is coupled to the high-side output terminal CANH for transmitting a high-side output signal to the high-side output terminal CANH, and a high-side P-type region (composed of high-side P-type sub-regions DH6P1, DH6P2 and DH6P 3) covers the side SDS3 and the bottom BTS3 of the high-side N-type region DH6N1 under the top surface UPS4 of the N-type semiconductor substrate to form a high-side PN junction (as indicated by a thick black dashed line in fig. 6B). And the high-side P-type region and the N-type semiconductor substrate form a high-side substrate PN junction (as illustrated by the thick black solid line in fig. 6B). The N-type semiconductor substrate may be electrically connected to the highest potential in the circuit, for example, but not limited to, as shown in fig. 6B, the internal voltage VDD, the high-side P-type region directly contacts the N-type semiconductor substrate, and no insulating layer is connected between the high-side P-type region and the N-type semiconductor substrate. For example, the high-side diode structure DH6 is formed by standard CMOS process steps, which do not include SOI process steps.
It should be noted that the high-side diode structure DH6 is used for blocking the reverse bias voltage for the low-side diode structure DH 6.
The low-side switch QL6 is, for example but not limited to, a PNP Bipolar Junction Transistor (BJT) as shown in fig. 6A, and is configured to operate according to a low-side operation signal OPL5 to generate a low-side output signal (in the present embodiment, illustrated by an emitter voltage), wherein the low-side switch QL6 is electrically connected to a reference voltage VSS (in the present embodiment, illustrated by a collector electrically connected to the reference voltage VSS). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND.
As shown in fig. 6A, the low-side diode structure DL6 is connected in series with the low-side switch QL6 for transmitting the low-side output signal and blocking the reverse bias. As shown in fig. 6C, the low side diode structure DL6 has a low side N region DL6N1 and a low side P region. The low-side P-type region is composed of low-side P-type sub-regions DL6P1, DL6P2 and DL6P 3. The low-side P-type sub-region DL6P3 is, for example but not limited to, a P-type buried layer (P-type buried layer) formed on an N-type semiconductor substrate, which is well known in the art and will not be described herein. Low side N-type region DL6N1 is electrically connected to low side switch QL6 to receive the low side output signal. The low side P-type region is coupled to the low side output terminal CANL to transmit a low side output signal to the low side output terminal CANL, and covers the side SDS4 and the bottom BTS4 of the low side N-type region DL6N1 under the upper surface UPS5 of the N-type semiconductor substrate to form a low side PN junction (as illustrated by a thick black dashed line in fig. 6C). And the low side P-type region and the N-type semiconductor substrate form a low side substrate PN junction (as illustrated by the solid bold line in fig. 6C). The resistor RL of the bus impedance circuit is coupled between the high-side output terminal CANH and the low-side output terminal CANL to generate a differential output signal according to the high-side output signal and the low-side output signal. The low-side P-type region is in direct contact with the N-type semiconductor substrate, and the non-insulating layer is connected between the low-side N-type region and the P-type semiconductor substrate. For example, the low side diode structure DL6 is formed by standard CMOS process steps, which do not include SOI process steps. The N-type semiconductor substrate may be electrically connected to the highest potential in the circuit, for example, but not limited to, as shown in fig. 6C, and electrically connected to the internal voltage VDD.
The voltage of the low-side P-type region must be maintained no higher than the low-side predetermined voltage to avoid the parasitic NPNBJT (as illustrated by the dashed line NPNBJT in fig. 6C) from being turned on under various conditions. For example: the parasitic NPNBJT conduction caused by the low-side diode structure DL6 flowing a large current or the parasitic NPNBJT conduction caused by the voltage at the low-side output terminal CANL being a positive voltage. In detail, when the voltage at the low side output terminal CANL is a positive voltage, the voltage at the base (P-type sub-region DL6P3) of the parasitic NPNBJT, for example, 48V, may be higher than the voltage at the collector (i.e., the voltage at the N-type semiconductor substrate, which is electrically connected to the highest potential in the circuit, for example, but not limited to, the internal voltage VDD as shown in fig. 6C), so that the parasitic NPNBJT is turned on. According to the invention, the low side clamp CLL6 is connected in series with the low side P-type region for clamping the voltage of the low side P-type region not higher than the low side predetermined voltage, so that the parasitic NPNBJT formed by the low side diode structure DL6 and the N-type semiconductor substrate is not turned on.
For example, as shown in fig. 6A, the low side clamp CLL6 includes a field effect transistor (MOS FET) having a source coupled to the low side P-type region and a gate biased to a predetermined control voltage GL to limit the low side P-type region voltage to not higher than the low side predetermined voltage, and a drain electrically connected to the low side output terminal CANL. The preset control voltage GL is, for example, but not limited to, 2V or a positive potential. For example, when the gate-source voltage Vgs of the N-type MOSFET is lower than 1V, the N-type MOSFET is not turned on, and therefore, when the preset control voltage GL is 2V and the low-side P-type region voltage is not higher than the low-side preset voltage, for example, 1V, the N-type MOSFET is maintained to be turned on; and when the low side P-type voltage is higher than the low side preset voltage 1V, the N-type MOSFET is not conducted so as to prevent the low side P-type voltage from being higher than the low side preset voltage 1V. This further avoids the parasitic NPNBJT turn-on described above. It should be noted that the low side diode structure DL6 is used to block the reverse bias voltage in the function of the high side diode structure DL 6.
Fig. 7A-7G show a sixth embodiment of the invention. Fig. 7A shows a circuit schematic of an output stage 71 for bus transferring data according to the present invention. As shown in fig. 7A, the output stage circuit 71 includes a controller 711 and a transceiver circuit 713. The controller 711 controls the transceiver circuit 713 to transmit (transmit) or receive (receive) data over a bus (not shown, as described above for bus 12). The bus has a high side signal line, a low side signal line, and an impedance circuit coupled therebetween. For example, as shown in fig. 1A, the impedance circuit includes two resistors RL, and two ends of each resistor RL are electrically connected to the high-side signal line and the low-side signal line, respectively. In the present embodiment, the high-side signal line has a plurality of high-side output terminals CANH respectively coupled to the corresponding transmission data control circuits 71. The low-side signal line has a plurality of low-side output terminals CANL, which are respectively coupled to the corresponding pass data control circuits 71. In one aspect, the tx data control circuit 71 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 71 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
Referring to fig. 7A, in the transceiver circuit 21, the transceiver circuit 713 includes a driving circuit 7131, a receiver 7132 and an output stage 7133. Different transmission data control circuits 71 transmit or receive data through the bus at different time periods. When one of the transceiving data control circuits 71 transmits or receives data, the other transceiving data control circuits 71 connected to the bus do not transmit or receive data through the bus, but the output stage circuit 7133 needs to bear the voltages of the high-side signal line and the low-side signal line. For safety reasons, the output stage circuit 7133 must be able to withstand high positive and negative voltages, such as positive and negative 48V.
As shown in fig. 7A, the controller 711 controls the driving circuit 7131 in the transceiver circuit 713 to operate the high-side switch QH7 and the low-side switch QL7 in the output stage circuit 3133 to transmit data through the corresponding high-side output terminal CANH and low-side output terminal CANL. On the other hand, the tx data control circuit 71 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL through the receiver 7132 to receive data.
With reference to fig. 7A, the output stage 7133 for bus data transmission is formed in an N-type semiconductor substrate, and the output stage 7133 is used for generating differential output signals at the high side output terminal CANH and the low side output terminal CANL of the bus. The output stage circuit 7133 includes a high-side switch QH7, a high-side diode structure DH7, a low-side clamp CLL7, a low-side switch QL7, and a low-side diode structure DL 7. The high-side switch QH7, such as but not limited to a P-type Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) as shown, is configured to operate according to a high-side operation signal OPH6 received by a gate thereof to generate a high-side output signal (in the present embodiment, indicated by a drain voltage), wherein the high-side switch QH7 is electrically connected to the internal voltage VDD (in the present embodiment, indicated by a source electrically connected to the internal voltage VDD). The internal voltage VDD is, for example, but not limited to, 5V.
The high-side diode structure DH7 is connected in series with the high-side switch QH7 for transmitting the high-side output signal and blocking the reverse bias. As shown in fig. 7A, the high-side diode structure DH7 includes, for example but not limited to, a high-side NPN bipolar junction field effect transistor (BJT) having a base electrically connected to a collector thereof, and the N-type region includes an emitter of the high-side NPNBJT and the P-type region includes a base of the high-side NPNBJT. As shown in fig. 7A, in the high-side diode structure DH7, a dotted line NPNBJT indicates a parasitic NPNBJT of the high-side NPNBJT, and its collector is an N-type semiconductor substrate and is electrically connected to the internal voltage VDD.
Fig. 7B and fig. 7C respectively show a top view and a cross-sectional view of the high side diode structure DH7 according to the embodiment. As shown in fig. 7B and 7C, the high-side diode structure DH7 includes a high-side NPN bipolar junction field effect transistor (BJT), as indicated by the thick black dashed transistor symbol in fig. 7C. In a preferred embodiment, as illustrated in fig. 7B, the high-side NPNBJT is a concentric ring zone (concentric zone) structure in which the N-type emitter THNE, the P-type base THPB and the N-type collector THNC are arranged from inside to outside, and the high-side NPNBJT further has an isolation region PISO and a P-type buried layer PBL. The isolation region PISO and the P-type buried layer PBL have P-type conductivity, are located outside the collector THNC, and wrap and electrically connect the collector THNC. The isolation region PISO and the P-type buried layer PBL directly contact the N-type semiconductor substrate to form a high-side PN junction (as indicated by a thick black solid line in fig. 7C). The isolation region PISO and the P-type buried layer PBL are directly contacted with the N-type semiconductor substrate, and no insulating layer is connected between the isolation region PISO and the P-type buried layer PBL and the N-type semiconductor substrate.
As illustrated in fig. 7C, the base THPB of the high-side NPNBJT is electrically connected to the collector THNC and to the isolation region PISO. And the high-side N-type region of the high-side diode structure DH7 includes the emitter THNE of the high-side NPNBJT. The high-side P-type region of the high-side diode structure DH7 includes a base THPB of the high-side NPNBJT, an isolation region PISO, and a P-type buried layer PBL. The high-side P-type region is electrically connected to high-side switch QH7 to receive the high-side output signal. The high-side N-type region is coupled to the high-side output terminal CANH for transmitting a high-side output signal to the high-side output terminal CANH, and the high-side P-type region covers the side and bottom surfaces of the high-side N-type region under the upper surface UPS6 of the N-type semiconductor substrate to form a high-side PN junction (as indicated by the solid bold line in fig. 7C). And the high-side P-type region and the N-type semiconductor substrate form a high-side substrate PN junction. The high-side P-type region is directly contacted with the N-type semiconductor substrate, and no insulating layer is connected between the high-side P-type region and the N-type semiconductor substrate. For example, the high-side diode structure DH7 is formed by standard CMOS process steps, which do not include SOI process steps. It should be noted that the high-side diode structure DH7 is used for blocking the reverse bias voltage for the high-side diode structure DH 7.
The low-side switch QL7, such as but not limited to a Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) as shown in fig. 7A, is configured to operate according to a low-side operating signal OPL6 received by a gate thereof to generate a low-side output signal (in the present embodiment, illustrated by a drain voltage), wherein the low-side switch QL7 is electrically connected to a reference voltage VSS (in the present embodiment, illustrated by a source being electrically connected to the reference voltage VSS). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND.
As shown in fig. 7A, the low-side diode structure DL7 is connected in series with the low-side switch QL7 for transmitting the low-side output signal and blocking the reverse bias. Fig. 7D and fig. 7E respectively show a top view and a cross-sectional view of the low side diode structure DL7 in the present embodiment. As shown in fig. 7D and 7E, the low side diode structure DL7 includes a low side NPN bipolar junction field effect transistor (BJT), as illustrated by the thick black dashed transistor symbol in fig. 7E. In a preferred embodiment, as illustrated in fig. 7D, the low-side NPNBJT is a concentric ring-band (concentric ring) structure in which the N-type emitter TLNE, the P-type base TLPB, and the N-type collector TLNC are arranged from inside to outside, and the low-side NPNBJT further has an isolation region PISO and a P-type buried layer PBL. The isolation region PISO and the P-type buried layer PBL have P-type conductivity, are located outside the collector TLNC, and wrap and electrically connect the collector TLNC. The isolation region PISO and the P-type buried layer PBL directly contact the N-type semiconductor substrate to form a low-side PN junction (as illustrated by a thick black solid line in fig. 7E). The isolation region PISO and the P-type buried layer PBL are directly contacted with the N-type semiconductor substrate, and no insulating layer is connected between the isolation region PISO and the P-type buried layer PBL and the N-type semiconductor substrate.
As illustrated in fig. 7E, the base TLPB of the low side NPNBJT is electrically connected to the collector TLNC and to the isolation region PISO. And the low side N-type region of the low side diode structure DL7 comprises the emitter TLNE of the low side NPNBJT. The low side P-type region of the low side diode structure DL7 includes a base TLPB of the low side NPNBJT, an isolation region PISO, and a P-type buried layer PBL. The low side N-type region includes an emitter TLNE electrically connected to the low side switch QL7 for receiving the low side output signal. The low side P-type region is coupled to the low side output terminal CANL to transmit a low side output signal to the low side output terminal CANL, and covers the side and bottom surfaces of the low side N-type region under the upper surface UPS7 of the N-type semiconductor substrate to form a low side PN junction (as illustrated by a thick black dotted line in fig. 7E). And the low side P-type region and the N-type semiconductor substrate form a low side substrate PN junction (as illustrated by the solid bold line in fig. 7E). The low-side P-type region is directly contacted with the N-type semiconductor substrate, and the non-insulating layer is connected between the low-side P-type region and the N-type semiconductor substrate. For example, the low side diode structure DL7 is formed by standard CMOS process steps, which do not include SOI process steps. The N-type semiconductor substrate may be electrically connected to the highest potential in the circuit, for example, but not limited to, as shown in fig. 7A and 7C, the N-type semiconductor substrate is electrically connected to the internal voltage VDD.
The voltage of the low-side P-type region must be maintained no higher than the low-side predetermined voltage to avoid the parasitic NPNBJT (as illustrated by the dashed line NPNBJT in fig. 7E) from being turned on under various conditions. For example: the parasitic NPNBJT conduction caused by the low-side diode structure DL7 flowing a large current or the parasitic NPNBJT conduction caused by the voltage at the low-side output terminal CANL being a positive voltage. In detail, when the voltage of the low-side output terminal CANL is a positive voltage, the voltage of the base (P-type buried layer PBL) of the parasitic NPNBJT, for example, 48V, may be higher than the voltage of the collector (i.e., the voltage of the N-type semiconductor substrate, which is electrically connected to the highest potential in the circuit, for example, but not limited to, the internal voltage VDD as shown in fig. 6C), so that the parasitic PNPBJT is turned on. According to the invention, the low side clamp CLL7 is connected in series with the low side P-type region for clamping the voltage of the low side P-type region not higher than the low side predetermined voltage, so that the parasitic NPNBJT formed by the low side diode structure DL7 and the N-type semiconductor substrate is not turned on.
For example, as shown in fig. 7A, the low side clamp CLL7 includes a field effect transistor (MOS FET) having a source coupled to the low side P-type region and a gate biased to a predetermined control voltage GL to limit the low side P-type region voltage to not higher than the low side predetermined voltage, and a drain electrically connected to the low side output terminal CANL. The preset control voltage GL is, for example, but not limited to, 2V or other positive voltage. For example, when the gate-source voltage Vgs of the N-type MOSFET is lower than 1V, the N-type MOSFET is not turned on, and therefore, when the preset control voltage GL is 2V and the low-side P-type region voltage is not higher than the low-side preset voltage, for example, 1V, the N-type MOSFET is maintained to be turned on; and when the low side P-type region voltage is higher than the high side preset voltage by 1V, the N-type MOSFET is not conducted so as to prevent the low side P-type region voltage from being higher than the low side preset voltage by 1V. This further avoids the parasitic NPNBJT turn-on described above. It should be noted that the low side diode structure DL7 is used to block the reverse bias voltage in the low side diode structure DL 7.
Fig. 7F and 7G respectively show a top view and a cross-sectional view of the low side clamp CLL7 according to the present embodiment. As shown in fig. 7F and 7G, the low side clamp CLL7 includes an N-type MOSFET having a gate POLY. In a preferred embodiment, as illustrated in fig. 7F, the low side clamp CLL7 is a concentric ring (concentric zone) structure in which the N-type source MLNS, the P-type channel MLPC and the N-type drain MLND are arranged from inside to outside, and the low side clamp CLL7 further has an isolation region PISO and a P-type buried layer PBL. The isolation region PISO and the P-type buried layer PBL have P-type conductivity, are located outside the drain MLND, and wrap and are electrically connected with the N-type drain MLND. The isolation region PISO and the P-type buried layer PBL are in direct contact with the N-type semiconductor substrate to form a low-side PN junction (as illustrated by a thick black solid line in fig. 7G). The isolation region PISO and the P-type buried layer PBL are directly contacted with the N-type semiconductor substrate, and no insulating layer is connected between the isolation region PISO and the P-type buried layer PBL and the N-type semiconductor substrate. For example, the high-side clamp CLL7 is formed from standard CMOS process steps, which do not include SOI process steps. The N-type semiconductor substrate may be electrically connected to the highest potential in the circuit, for example, but not limited to, as shown in fig. 7G, and electrically connected to the internal voltage VDD.
Fig. 8 shows a seventh embodiment of the invention. Fig. 8 shows a circuit schematic of an output stage 81 for bus transferring data according to the present invention. As shown in fig. 8, the output stage circuit 81 includes a controller 811 and a transceiver circuit 813. The controller 811 controls the transceiver circuit 813 to transmit or receive data via a bus (not shown, such as the bus 12 described above). In one aspect, the tx data control circuit 81 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 71 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
Referring to fig. 8, in the transceiver circuit 81, the transceiver circuit 813 includes a driving circuit 8131, a receiver 8132, and an output stage circuit 8133. As shown, the controller 811 controls the driving circuit 8131 in the transceiver circuit 813 to operate the high-side switch QH8 and the low-side switch QL8 in the output stage circuit 8133 to transmit data through the corresponding high-side output terminal CANH and low-side output terminal CANL. On the other hand, the transmission data control circuit 81 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL through the receiver 8132 to receive data.
With reference to fig. 8, the output stage circuit 8133 for bus data transmission is formed in the N-type semiconductor substrate, and the output stage circuit 8133 is configured to generate differential output signals at the high side output terminal CANH and the low side output terminal CANL of the bus. The output stage circuit 8133 includes a high-side switch QH8, a high-side diode structure DH8, a low-side clamp CLL8, a low-side switch QL8, and a low-side diode structure DL 8. The high-side switch QH8, such as but not limited to a P-type Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) as shown, is configured to operate according to a high-side operation signal OPH7 received by a gate thereof to generate a high-side output signal (in the present embodiment, indicated by a drain voltage), wherein the high-side switch QH8 is electrically connected to the internal voltage VDD (in the present embodiment, indicated by a source electrically connected to the internal voltage VDD). The internal voltage VDD is, for example, but not limited to, 5V.
The high-side diode structure DH8 is connected in series with the high-side switch QH8 for transmitting the high-side output signal and blocking the reverse bias. As shown in fig. 8, the high-side diode structure DH8 includes, for example but not limited to, a high-side NPN bipolar junction field effect transistor (BJT) having a base electrically connected to a collector thereof, and the N-type region includes an emitter of the high-side NPNBJT and the P-type region includes a base of the high-side NPNBJT. As shown in fig. 8, in the high-side diode structure DH8, the dotted line NPNBJT indicates the parasitic NPNBJT of the high-side NPNBJT, and the collector thereof is an N-type semiconductor substrate and is electrically connected to the highest potential in the internal circuit, for example, but not limited to, the internal voltage VDD as shown in fig. 8.
It should be noted that the high-side diode structure DH7 is used for blocking the reverse bias voltage for the high-side diode structure DH 7.
The low-side switch QL8, such as but not limited to a Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) as shown in fig. 8, is configured to operate according to a low-side operating signal OPL7 received by a gate thereof to generate a low-side output signal (in the present embodiment, illustrated by a drain voltage), wherein the low-side switch QL8 is electrically connected to a reference voltage VSS (in the present embodiment, illustrated by a source electrically connected to the reference voltage VSS). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND.
As shown in fig. 8, the low side diode structure DL8 is connected in series with the low side switch QL8 for transmitting the low side output signal and blocking the reverse bias. In the present embodiment, the low side diode structure DL8 includes a low side NPN bipolar junction field effect transistor (BJT). In a preferred embodiment, the low-side NPNBJT is a concentric ring zone (concentric zone) structure in which the N-type emitter, the P-type base, and the N-type collector are arranged from inside to outside, and the low-side NPNBJT further has an isolation region and a P-type buried layer. The isolation region and the P-type buried layer have P-type conductivity, are located outside the collector and wrap and are electrically connected with the collector. The isolation region is in direct contact with the P-type buried layer and the N-type semiconductor substrate to form a low-side PN junction. The isolation region is directly contacted with the P-type buried layer and the N-type semiconductor substrate, and no insulating layer is connected between the isolation region and the P-type buried layer PBL as well as the N-type semiconductor substrate. The N-type semiconductor substrate may be electrically connected to the highest potential in the circuit, for example, but not limited to, the internal voltage VDD as shown by the collector voltage of the dotted parasitic NPNBJT in fig. 8.
The base of the low side NPNBJT is electrically connected to the collector and to the isolation region. And the low side N-type region of low side diode structure DL8 includes the emitter of low side NPNBJT. The low side P-type region of the low side diode structure DL8 includes the base of the low side NPNBJT, the isolation region and the P-type buried layer. The low side N-type region includes an emitter electrically connected to the low side switch QL8 for receiving the low side output signal. The low side P-type region is coupled to the low side output terminal CANL to transmit a low side output signal to the low side output terminal CANL, and covers the side and bottom surfaces of the low side N-type region under the upper surface of the N-type semiconductor substrate to form a low side PN junction. And the low-side P-type region and the N-type semiconductor substrate form a low-side substrate PN junction. The low-side P-type region is directly contacted with the N-type semiconductor substrate, and the non-insulating layer is connected between the low-side P-type region and the N-type semiconductor substrate. For example, the low side diode structure DL8 is formed by standard CMOS process steps, which do not include SOI process steps.
The difference between this embodiment and the sixth embodiment is that in this embodiment, the low side clamp CLL8 preferably further includes a zener diode ZD, a resistor RP, a capacitor CP, a voltage source VP1, and a diode DP and a voltage source VP2 connected in series. The zener diode ZD is coupled between the gate and the source of the N-type MOSFET of the low side clamp CLL8, for example, to maintain the gate-source voltage (Vsg) of the N-type MOSFET at 5V to keep the N-type MOSFET on. Resistor RP is connected in series with voltage source VP1 for limiting the current through zener diode ZD when the voltage at low side output CANL is too low. The capacitor CP is coupled between the gate of the N-type MOSFET of the low side clamp CLL8 and the voltage source VP2 for reducing a coupling effect (coupling effect) of the gate-drain capacitance of the N-type MOSFET of the low side clamp CLL8. The voltage source VP1 is connected in series with the resistor RP, and the voltage source VP1 is connected in series with the resistor RP and then connected in parallel with the capacitor CP. The voltage source VP1 is used to provide a predetermined bias voltage for the capacitor CP when the pass data control circuit 81 is transmitting data through the low side output terminal CANL, thereby reducing the gate-drain capacitance coupling effect of the N-type MOSFET of the low side clamp CLL8. The diode DP is connected in parallel with the capacitor CP and connected in series with the voltage source VP2 for providing a fast clamping path for the gate of the N-type MOSFET of the low side clamp CLL8 to reduce the effect of the gate-drain capacitance coupling effect of the N-type MOSFET, wherein the voltage source VP2 provides a higher voltage than the voltage source VP 1.
Referring to fig. 9, an eighth embodiment of the invention is shown. Fig. 9 shows a circuit schematic of an output stage 91 for bus transferring data according to the present invention. As shown in fig. 9, the output stage circuit 91 includes a controller 911 and a transceiver 913. The controller 911 controls the transceiver circuit 913 to transmit or receive data via a bus (not shown), such as the bus 12 described above. In one aspect, the tx data control circuit 91 generates differential output signals corresponding to the high side output terminal CANH and the low side output terminal CANL to transmit data. On the other hand, the transmission data control circuit 91 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL to receive data.
Referring to fig. 9, in the transceiver circuit 91, the transceiver circuit 913 includes a driving circuit 9131, a receiver 9132 and an output stage circuit 9133. Different transmission data control circuits 91 transmit or receive data through the bus at different time periods. As shown in fig. 9, the controller 911 controls the driving circuit 9131 in the transceiver circuit 913 to operate the high-side switch QH9 and the low-side switch QL9 in the output stage circuit 9133, so as to transmit data through the corresponding high-side output terminal CANH and low-side output terminal CANL. On the other hand, the transmission data control circuit 91 receives the differential input signal from the corresponding high-side output terminal CANH and low-side output terminal CANL via the receiver 9132 to receive data.
With reference to fig. 9, the output stage 9133 for bus data transmission is formed in an N-type semiconductor substrate, and the output stage 9133 is used for generating differential output signals at the high side output terminal CANH and the low side output terminal CANL of the bus. The output stage circuit 9133 includes a high-side switch QH9, a high-side diode structure DH9, a low-side clamp CLL9, a low-side switch QL9, and a low-side diode structure DL 9. The high-side switch QH9 is, for example but not limited to, a PNP Bipolar Junction Transistor (BJT) as shown in the figure, and is configured to operate according to a high-side operation signal OPH8 received by a base thereof to generate a high-side output signal (in the present embodiment, indicated by a collector voltage), wherein the high-side switch QH9 is electrically connected to an internal voltage VDD (in the present embodiment, indicated by an emitter electrically connected to the internal voltage VDD). The internal voltage VDD is, for example, but not limited to, 5V.
The high-side diode structure DH9 is connected in series with the high-side switch QH9 for transmitting the high-side output signal and blocking the reverse bias. It should be noted that the high-side diode structure DH9 is used for blocking the reverse bias voltage for the low-side diode structure DH 9.
The difference between this embodiment and the fifth embodiment is that, in this embodiment, as shown in fig. 9, the low side clamp CLL9 includes an NPN Bipolar Junction Transistor (BJT) as shown in the figure, an emitter of the BJT is coupled to the low side P-type region of the low side diode structure DL9, a base of the BJT is biased to a predetermined control voltage GL to limit the voltage of the low side P-type region not higher than the low side predetermined voltage, and a collector of the BJT is electrically connected to the low side output terminal CANL. The preset control voltage GL is, for example, but not limited to, 2V or other positive voltage.
The low-side switch QL9 is, for example but not limited to, a PNP Bipolar Junction Transistor (BJT) as shown in fig. 9, and is configured to operate according to a low-side operation signal OPL8 to generate a low-side output signal (in the present embodiment, illustrated by an emitter voltage), wherein the low-side switch QL9 is electrically connected to a reference voltage VSS (in the present embodiment, illustrated by a collector electrically connected to the reference voltage VSS). The reference voltage VSS is, for example but not limited to, 0V or the ground potential GND. The low side diode structure DL9 is connected in series with the low side switch QL9 for transmitting the low side output signal and blocking reverse bias. It should be noted that the low side diode structure DL9 is used to block the reverse bias voltage in the low side diode structure DL 9.
The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. The embodiments described are not limited to single use, but may be used in combination, for example, two or more embodiments may be combined, and some components in one embodiment may be substituted for corresponding components in another embodiment. In addition, equivalent variations and combinations can be realized by those skilled in the art within the spirit of the present invention, for example, the logic circuit in the foregoing embodiments is not limited to the illustrated inverse logic gate and NAND logic gate, and other logic gates can be substituted, as long as the same logic operation result can be achieved. The term "processing or calculating or generating an output result based on a signal" in the present invention is not limited to the signal itself, and includes, if necessary, performing voltage-to-current conversion, current-to-voltage conversion, and/or scaling on the signal, and then performing processing or calculation based on the converted signal to generate an output result. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as threshold voltage adjustment regions, may be added without affecting the primary characteristics of the device. All of which can be analogized to the teachings of the present invention. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above. Furthermore, it is not necessary for any embodiment of the invention to achieve all of the objects or advantages, and thus, any one of the claims should not be limited thereby.
Claims (16)
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| CN201911021772.2A CN112713864A (en) | 2019-10-25 | 2019-10-25 | Output stage circuit for bus transfer data |
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| CN201911021772.2A CN112713864A (en) | 2019-10-25 | 2019-10-25 | Output stage circuit for bus transfer data |
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Application publication date: 20210427 |