CN112652622A - Semiconductor memory, semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor memory, semiconductor structure and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000002955 isolation Methods 0.000 claims abstract description 125
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000005530 etching Methods 0.000 claims description 20
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000015654 memory Effects 0.000 abstract description 10
- 238000003860 storage Methods 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 230000002035 prolonged effect Effects 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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Abstract
The disclosure relates to the technical field of memories, and relates to a semiconductor structure, a manufacturing method of the semiconductor structure and a semiconductor memory. The semiconductor structure includes: the word line trench structure comprises a substrate, an isolation structure, a word line trench and a word line, wherein the isolation structure is formed in the substrate and defines a plurality of active regions in the substrate; word line grooves are formed on the substrate and the isolation structures; the word line is arranged in the word line groove and penetrates through the active region and the isolation structure; wherein, in the depth direction of the word line groove, the height of the word line on the active region is larger than the height of the word line at least partially on the isolation structure. The semiconductor structure provided by the disclosure can reduce the influence of the word line of the active isolation region on the electrical property of the storage transistor of the adjacent active region in a working state, and reduce leakage current.
Description
Technical Field
The present disclosure relates to the field of memory technologies, and in particular, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor memory.
Background
With the increasing trend of electronic products toward lighter, thinner, shorter and smaller products, the design of Dynamic Random Access Memory (DRAM) devices must also meet the trend of high integration and high density requirements toward miniaturization, and in order to increase the integration of DRAM devices to increase the operating speed of the devices and meet the consumer demand for miniaturized electronic devices, embedded gate word line DRAM devices have been developed in recent years to meet the above-mentioned needs.
However, as the size of the device decreases, the word line resistance increases gradually, which increases the access time of the device, usually by increasing the height of the word line to achieve its low resistance, while a larger gate induced drain leakage current may greatly reduce the reliability of the memory device, increase the refresh frequency of the memory device, and increase the power consumption of the memory device.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor memory, which can reduce the influence of word lines in active isolation regions on the electrical properties of memory transistors in adjacent active regions in an operating state and reduce leakage current.
According to an aspect of the present disclosure, there is provided a semiconductor structure including:
a substrate;
an isolation structure formed in the substrate and defining a plurality of active regions in the substrate;
a word line trench formed on the substrate and the isolation structure; and
the word line is arranged in the word line groove and penetrates through the active region and the isolation structure; wherein,
in the depth direction of the word line groove, the height of the word line on the active area is larger than the height of the word line at least partially on the isolation structure.
In an exemplary embodiment of the present disclosure, a depth of the word line trench on the active region is greater than a depth of the word line trench at least partially on the isolation structure.
In an exemplary embodiment of the present disclosure, a height of a region where a depth of the word line trench on the isolation structure is less than a depth of the word line trench on the active region is 28nm to 32 nm.
In an exemplary embodiment of the present disclosure, a width of the word line on the isolation structure is greater than a width of the word line on the active region in a width direction of the word line trench.
In an exemplary embodiment of the present disclosure, a width of the word line on the isolation structure in a width direction of the word line trench is 20nm to 35 nm.
In an exemplary embodiment of the present disclosure, at least one of the active regions is provided with two of the word lines crossing.
According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, the method comprising:
providing a substrate;
forming an isolation structure in the substrate, the isolation structure defining a plurality of active regions in the substrate;
forming a word line trench on the substrate and the isolation structure;
and forming a word line penetrating through the active region and the isolation structure in the word line groove, wherein the height of the word line on the active region is larger than the height of the word line at least partially on the isolation structure in the depth direction of the word line groove.
In an exemplary embodiment of the present disclosure, forming a word line trench on the substrate and the isolation structure includes:
etching the active region to form a first groove with a first preset depth;
and etching the isolation structure, forming a second groove with a second preset depth in at least partial region, communicating the first groove and the second groove to form the word line groove, wherein the first preset depth is greater than the second preset depth.
In an exemplary embodiment of the present disclosure, etching the isolation structure includes:
etching the isolation structure by adopting isotropic etching;
and etching the isolation structure to the second preset depth by adopting anisotropic etching to form the second groove.
In an exemplary embodiment of the present disclosure, forming a word line in the word line trench through the active region and the isolation structure includes:
forming a gate oxide layer on the inner wall of the word line trench;
the word line is formed on the gate insulating layer.
According to yet another aspect of the present disclosure, there is provided a semiconductor memory including the semiconductor structure of any one of the above.
According to the semiconductor structure provided by the disclosure, in the depth direction of the word line groove, the height of the word line on the active region is larger than that of at least part of the word line on the isolation structure, so that the overlapping area of the word line on the isolation structure and the word line on the active region on the adjacent word line is reduced, the influence of the word line on the isolation structure on the electrical property of the storage transistor in the adjacent active region in a working state is reduced, the leakage current is reduced, the device refreshing time is prolonged, and the reliability of a semiconductor device is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a top view of a semiconductor structure provided in one embodiment of the present disclosure;
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure provided by one embodiment of the present disclosure;
FIGS. 3-8 are process diagrams of a method of fabricating a semiconductor structure taken from a cross-section taken along plane A-A of FIG. 1;
fig. 9-14 are process diagrams of a method of fabricating a semiconductor structure taken from a cross-section at plane B-B in fig. 1.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The terms "a," "an," "the," and "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and the like are used merely as labels, and are not limiting on the number of their objects.
The present example embodiment first provides a semiconductor structure. As shown in fig. 1, 8 and 14, the semiconductor structure includes: the semiconductor device comprises a substrate 10, an isolation structure 20, a word line trench 40 and a word line 30, wherein the isolation structure 20 is formed in the substrate 10 and defines a plurality of active regions 101 in the substrate 10; the word line trench 40 is formed on the substrate 10 and the isolation structure 20; word line 30 is disposed in word line trench 40, word line 30 passing through active region 101 and isolation structure 20; wherein, in the depth direction of the word line trench 40, the height of the word line 30 located on the active region 101 is greater than the height of the word line 30 located on the isolation structure 20.
According to the semiconductor structure provided by the disclosure, in the depth direction of the word line trench 40, the height of the word line 30 on the active region 101 is greater than the height of at least part of the word line 30 on the isolation structure 20, so that the overlapping area between the word line 30 on the isolation structure 20 and the word line 30 on the active region 101 on the adjacent word line 30 is reduced, the influence of the word line 30 on the isolation structure on the electrical property of the memory transistor in the adjacent active region 101 in an operating state is reduced, the leakage current is reduced, the device refresh time is prolonged, and the reliability of the semiconductor device is increased.
The substrate 10 is a semiconductor substrate, the material of which the substrate 10 is formed includes, but is not limited to, a monocrystalline silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate, or a sapphire substrate, and when the semiconductor substrate is a monocrystalline substrate or a polycrystalline substrate, the semiconductor substrate may also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate. The isolation structure 20 is an insulating material, the material for forming the isolation structure 20 may include silicon nitride or silicon oxide, and the filling medium may be silicon nitride or silicon oxide. Word line 30 is a conductive material, and the conductive material forming the word line may include one of tungsten, titanium, nickel, aluminum, titanium oxide, titanium nitride, or a combination thereof.
Specifically, in the width direction of the word line trench 40, the width of the word line 30 located on the isolation structure 20 is greater than the width of the word line 30 located on the active region 101. The depth direction of the word line trench 40 is the height direction of the cross-sectional view shown in fig. 8, and the width direction of the word line trench 40 is the width direction of the cross-sectional view shown in fig. 8. By relatively increasing the width of the word line 30, the area of the cross section of the word line 30 can be increased, and then the resistance of the word line 30 on the isolation structure 20 can be reduced, thereby avoiding the problem that the resistance of the word line 30 is increased due to the reduction of the height of the word line 30 on the isolation structure 20, ensuring that the resistance of the word line 30 can not be relatively increased while the overlapping area of the word line 30 on the isolation structure 20 and the word line 30 on the active area on the adjacent word line 30 is reduced, and being beneficial to the opening speed of the transistor.
Wherein, in the width direction of the word line trench 40, the width of the word line 30 on the isolation structure 20 is 20nm to 35 nm. For example, the width of the word line 30 on the isolation structure 20 may be 20nm, 22nm, 25nm, 27nm, 29nm, 30nm, 32nm, 35nm, etc., which are not listed here. It can be seen that the width of the word line 30 on the isolation structure 20 provided by the present disclosure can reach 30nm, so that the width of the word line 30 is relatively increased, and the area of the cross section of the word line 30 can be greatly increased, thereby ensuring that the resistance of the word line 30 on the isolation structure 20 is within a preset range.
Specifically, the depth of the word line trench 40 located on the active region 101 is greater than the depth of the word line trench 40 located at least partially on the isolation structure 20, and as shown in fig. 14, the depth of the word line trench on the isolation structure 20 in the region close to the active region 101 is greater than the depth of the word line trench on the active region 101. By making the depth of the word line trench 40 on the active region 101 greater than the depth of the word line trench 40 at least partially located on the isolation structure 20, when the word line 30 is formed in the trench by deposition or the like, the height of the word line 30 deposited on the active region 101 can be made greater than the height of the word line 30 deposited on the isolation structure 20, so that the overlapping area between the word line 30 located on the isolation structure 20 and the word line 30 located on the active region 101 on the adjacent word line 30 can be reduced, the influence of the word line 30 on the isolation structure 20 on the electrical property of the memory transistor in the adjacent active region 101 in an operating state can be reduced, and the leakage current can be reduced.
Further, as shown in fig. 14, the side of the word line 30 that opens to the word line trench 40 is planar. By making the side of the word line 30 facing the opening of the word line trench 40 a plane, the height of the overlapping area between the word line 30 on the isolation structure 20 and the word line 30 on the active region 101 on the adjacent word line 30 can be made to be the height of the word line 30 on the isolation structure 20, so that the height of the overlapping area between the word line 30 on the isolation structure 20 and the word line 30 on the active region 101 on the adjacent word line 30 can be controlled, the overlapping area can be further reduced, and the electrical influence of the word line 30 on the isolation structure on the memory transistor in the adjacent active region 101 in the operating state can be reduced.
Wherein, the height of the area where the depth of the word line groove on the isolation structure 20 is smaller than the depth of the word line groove on the active area 101 is 28nm to 32 nm. By setting the height of the isolation structure 20 below the word line trench 40 to be 28nm to 32nm, the height of the isolation structure 20 below the word line trench 40 is increased, the depth of the word line trench 40 on the isolation structure 20 is relatively reduced, and the overlapping area between the word line 30 on the isolation structure 20 and the word line 30 on the active region 101 on the adjacent word line 30 is reduced.
As shown in fig. 1, at least one active region 101 is provided with two word lines 30 passing through, and the isolation structure 20 may be a Shallow Trench Isolation (STI).
There is also provided in this example embodiment a method of manufacturing a semiconductor structure, as shown in fig. 2, including:
step S100, providing a substrate;
step S200, forming an isolation structure in a substrate, wherein the isolation structure defines a plurality of active regions in the substrate;
step S300, forming a word line groove on the substrate and the isolation structure;
step S400, forming a word line passing through the active region and the isolation structure in the word line trench, and making the height of the word line on the active region greater than the height of at least a part of the word line on the isolation structure in the depth direction of the word line trench.
According to the manufacturing method of the semiconductor memory, the height of the word line on the active area is larger than that of at least part of the word line on the isolation structure in the depth direction of the word line groove, so that the overlapping area of the word line on the isolation structure and the word line on the active area on the adjacent word line can be reduced, the influence of the word line on the isolation structure on the electrical property of the storage transistor in the adjacent active area in the working state is reduced, the leakage current is reduced, the device refreshing time is prolonged, and the reliability of a semiconductor device is improved.
Next, each step of the method for manufacturing the semiconductor structure in the present exemplary embodiment will be further described.
In step S100, a substrate is provided.
Specifically, as shown in fig. 3, a semiconductor substrate 10 is provided, the material of the substrate includes, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate, and when the semiconductor substrate is a single crystal substrate or a polycrystalline substrate, the semiconductor substrate may also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.
In step S200, an isolation structure is formed in a substrate, the isolation structure defining a plurality of active regions in the substrate.
Specifically, as shown in fig. 3 and 9, a Shallow Trench Isolation Trench is formed on a semiconductor substrate by STI (Shallow Trench Isolation) Isolation, wherein the depth of the Shallow Trench Isolation Trench may be 28nm to 32nm, and then the Isolation structure 20 is formed in the etched Shallow Trench Isolation Trench by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) or other deposition techniques. The plurality of active regions 101 isolated by the isolation structure 20 may be, but not limited to, arranged in an array as shown in fig. 1. The material of the isolation structure 20 may include an insulating material such as silicon nitride or silicon oxide. As an example, a MOS device (not shown) is formed in the active region 101, and the MOS device includes a gate, a source, and a drain, and the source and the drain are respectively located at two opposite sides of the gate.
In step S300, a word line trench is formed on the substrate and the isolation structure.
Specifically, the method includes steps S310 and S320:
in step S310, the active region is etched to form a first trench having a first predetermined depth.
Specifically, as shown in fig. 4 and 10, a photoresist layer is formed on the upper surfaces of the substrate 10 and the isolation structure 20, a pattern 70 for forming word lines is then displayed on the photoresist layer by exposure, the active region 101 is then etched through the patterned photoresist layer, and an etching solution corresponding to the material of the active region 101 is selected to avoid etching the isolation structure 20. Alternatively, the active region 101 is etched using an anisotropic dry etching process, and a first trench is formed on the active region 101.
In step S320, the isolation structure is etched, a second trench having a second predetermined depth is formed in at least a portion of the region, the first trench is communicated with the second trench to form a word line trench, and the first predetermined depth is greater than the second predetermined depth.
Specifically, as shown in fig. 5 and 11, the isolation structure 20 is etched through the patterned photoresist layer, and the isolation structure 20 is first etched using isotropic etching to form an opening with a large width on the isolation structure 20. The isolation structure 20 may be etched down to about 10nm using isotropic etching to form an opening with a width of 20nm to 35nm in the isolation structure 20.
Next, as shown in fig. 6, 12 and 14, the isolation structure 20 is etched continuously downward from the opening by using anisotropic etching, the isolation structure 20 may be etched downward by about 90nm by using anisotropic etching to form a second trench with a second predetermined depth in at least a partial region, and as shown in fig. 14, the depth of the word line trench on the isolation structure 20 in the region close to the active region 101 is greater than the depth of the word line trench on the active region 101. After forming the second trench in the row of isolation structures 20, the second trench is communicated with the first trench to form the word line trench 40, and the first predetermined depth is greater than the second predetermined depth, that is, the depth of the first trench is greater than 100 nm.
It should be clear to those skilled in the art that the width of the isolation structure 20 should be greater than 32nm to ensure that after the second trench is formed on the isolation structure, there is also isolation structure material between the inner wall of the second trench and the active region 101 to form insulation of the second trench from the active region 101.
In step S400, word lines passing through the active region and the isolation structure are formed in the word line trenches, and the height of the word lines above the active region is made greater than the height of the word lines at least partially above the isolation structure in the depth direction of the word line trenches.
Specifically, the method includes steps S410 and S420:
in step S410, a gate oxide layer is formed on the inner wall of the word line trench.
Specifically, as shown in fig. 7 and 13, a gate oxide layer 50 may be formed on the inner wall of the word line trench 40 by using chemical vapor deposition, physical vapor deposition or other deposition techniques, wherein the gate oxide layer 50 has a U-shape at a portion located at the bottom of the word line trench 40, and the thickness of the gate oxide layer 50 may be 5nm to 6 nm. Alternatively, a thermal oxidation process is used to oxidize a portion of the inner surface of the word line trench 40 to form a gate oxide layer 50 on the inner surface of the word line trench 40. The gate oxide layer 50 is made of an extremely bright material such as silicon dioxide.
In step S420, a word line is formed in the word line trench.
Specifically, as shown in fig. 8 and 14, the metal word line 30 may be formed on the gate oxide layer 50 on the inner surface of the word line trench 40 by a chemical vapor deposition method, a physical vapor deposition method, or other means. The conductive material forming the word line 30 includes one or a combination of tungsten, titanium, nickel, aluminum, titanium oxide, and titanium nitride, and those skilled in the art can select other conductive materials, which is not limited by the present disclosure. The second trench is communicated with the first trench to form a word line trench 40, and the first preset depth is greater than the second preset depth, so that the height of the word line 30 positioned on the active region 101 is greater than the height of at least part of the word line 30 positioned on the isolation structure 20, the overlapping area between the word line 30 positioned on the isolation structure 20 and the word line 30 positioned on the active region 101 on the adjacent word line 30 can be reduced, the influence of the word line 30 on the isolation structure on the electrical property of the storage transistor in the adjacent active region 101 in the working state is reduced, the leakage current is reduced, the device refresh time is prolonged, and the reliability of the semiconductor device is increased.
In addition, the method for manufacturing the semiconductor structure further comprises the following steps: a top protective layer is formed.
Specifically, as shown in fig. 8 and 14, after the word line 30 is formed, the top protection layer 60 is then formed by using chemical vapor deposition, physical vapor deposition or other deposition techniques, and the top protection layer 60 completely covers the active region 101 of the substrate 10, the isolation structure 20 and the word line 30. The top protective layer 60 is an insulating oxide, such as silicon oxide or silicon carbide, but is not limited thereto.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
The semiconductor structure with the embedded Gate line provided in the present disclosure can be applied to, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), a Junction Field Effect Transistor (JFET), or the like. By reducing the overlapping area of the word line on the isolation structure and the word line on the active area on the adjacent word line, the influence of the word line on the isolation structure on the electrical property of the storage transistor in the adjacent active area in the working state is reduced, the leakage current is reduced, the refreshing time of the device is prolonged, and the reliability of the semiconductor device is improved.
The present disclosure also provides a semiconductor memory including the semiconductor structure. The semiconductor memory may be a computing memory (e.g., DRAM, SRAM, DDR3SDRAM, DDR2SDRAM, DDR SDRAM, etc.), a consumer memory (e.g., DDR3SDRAM, DDR2SDRAM, DDR SDRAM, SDRSDRAM, etc.), a graphics memory (e.g., DDR3SDRAM, GDDR3SDMRA, GDDR4SDRAM, GDDR5SDRAM, etc.), a mobile memory, and the like. The advantageous effects of the present invention can be described with reference to the above semiconductor structure, and are not described herein again.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (11)
1. A semiconductor structure, comprising:
a substrate;
an isolation structure formed in the substrate and defining a plurality of active regions in the substrate;
a word line trench formed on the substrate and the isolation structure; and
the word line is arranged in the word line groove and penetrates through the active region and the isolation structure; wherein,
in the depth direction of the word line groove, the height of the word line on the active area is larger than the height of the word line at least partially on the isolation structure.
2. The semiconductor structure of claim 1, wherein a depth of the wordline trench located over the active region is greater than a depth of the wordline trench located at least partially over the isolation structure.
3. The semiconductor structure of claim 2, wherein a height of a region where a depth of the word line trench on the isolation structure is less than a depth of the word line trench on the active region is 28nm to 32 nm.
4. The semiconductor structure of claim 1, wherein a width of the word line on the isolation structure is greater than a width of the word line on the active region in a width direction of the word line trench.
5. The semiconductor structure of claim 4, wherein the width of the word line on the isolation structure in the width direction of the word line trench is 20nm to 35 nm.
6. The semiconductor structure of claim 1, wherein at least one of the active regions is crossed by two of the word lines.
7. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming an isolation structure in the substrate, the isolation structure defining a plurality of active regions in the substrate;
forming a word line trench on the substrate and the isolation structure;
and forming a word line penetrating through the active region and the isolation structure in the word line groove, wherein the height of the word line on the active region is larger than the height of the word line at least partially on the isolation structure in the depth direction of the word line groove.
8. The method of manufacturing of claim 7, wherein forming a word line trench over the substrate and the isolation structure comprises:
etching the active region to form a first groove with a first preset depth;
and etching the isolation structure, forming a second groove with a second preset depth in at least partial region, communicating the first groove and the second groove to form the word line groove, wherein the first preset depth is greater than the second preset depth.
9. The method of manufacturing of claim 8, wherein etching the isolation structure comprises:
etching the isolation structure by adopting isotropic etching;
and etching the isolation structure to the second preset depth by adopting anisotropic etching to form the second groove.
10. The method of manufacturing of claim 7, wherein forming a word line in the word line trench through the active region and the isolation structure comprises:
forming a gate oxide layer on the inner wall of the word line trench;
forming the word line within the word line trench.
11. A semiconductor memory comprising the semiconductor structure of any one of claims 1 to 6.
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