CN112635474A - Three-dimensional NAND memory and preparation method thereof - Google Patents
Three-dimensional NAND memory and preparation method thereof Download PDFInfo
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- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention discloses a three-dimensional NAND memory and a preparation method thereof, wherein the preparation method comprises the following steps: preparing a first semiconductor structure as a three-dimensional vertical storage array; the three-dimensional vertical memory array comprises a plurality of three-dimensional vertical memory cells and a first insulating layer; bonding a first material layer on the first insulating layer; performing first thinning treatment and first surface treatment on the first material layer to form a first substrate layer; manufacturing a plurality of low-temperature MOS transistors on the first substrate layer at a low temperature, forming a second insulating layer on the plurality of low-temperature MOS transistors, and forming a second semiconductor structure serving as a reading and control layer; and opening a through hole in the first insulating layer and the second semiconductor structure, and depositing metal in the through hole to form an interconnection layer so as to interconnect the first semiconductor structure and the second semiconductor structure. The invention can realize 3D storage with higher precision and higher density; the internal bandwidth is greatly improved, and the storage efficiency and performance are improved; the reliability problem caused by the process stress of the finished product of the read-out circuit is reduced, and the yield of the 3D flash memory is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional NAND memory based on transistor-level monolithic 3D integration and a preparation method thereof.
Background
The 3D NAND is the main technical direction of a nonvolatile Flash Memory (Flash Memory), and compared with the traditional 2D NAND, the integration capacity and density are greatly improved; currently, the industry is continuously increasing the number of 3D integration layers of memory cells, for example, from 32 layers to 64 layers to 128 layers, which is the technological motive force for the continuous development of 3D NAND.
In addition, the 3D integrated unit is generally integrated on a monocrystalline silicon chip containing a reading and control circuit, so that the whole area of the chip can be effectively reduced, and the integration level is improved. As the number of integration layers is higher, it brings a series of technical challenges: the manufacturing process is complicated, the reliability is reduced, and the reading performance of the single-channel laminated unit is degraded.
Currently, a new technology X-stacking exists in the industry, in which the readout and control circuit in the 3D NAND and the memory cell array are separately manufactured, and then high-density integration is formed by a mutual bonding method, so that the mutual influence between the readout and control unit manufacturing process and the 3D vertical memory array can be reduced, and the manufacturing cycle can be reduced. However, the X-stacking method has extremely high requirements on chip bonding technology, requires alignment accuracy below 500nm, requires an additional redundant design, and meanwhile, in the bonding process, an extremely thin substrate is very easy to generate stress, and generates large defects on a read and control circuit chip prepared in advance, which causes circuit defects and requires a complex improvement process.
Disclosure of Invention
The purpose of the invention is realized by the following technical scheme.
In order to overcome the technical problems that in the existing 3D NAND bonding process, an extremely thin substrate is easy to generate stress, a read and control circuit chip prepared in advance is easy to generate a large defect, circuit defects are caused, and a complex improvement process is needed, the invention provides a three-dimensional NAND memory and a preparation method thereof.
The preparation method of the three-dimensional NAND memory comprises the following steps:
preparing a first semiconductor structure as a three-dimensional vertical storage array; wherein the three-dimensional vertical memory array includes a plurality of three-dimensional vertical memory cells, and a first insulating layer formed on the plurality of three-dimensional vertical memory cells;
bonding a first material layer on the first insulating layer; performing first thinning treatment and first surface treatment on the first material layer to form a first substrate layer;
manufacturing a plurality of low-temperature MOS transistors on the first substrate at a low temperature, and forming a second insulating layer on the plurality of low-temperature MOS transistors to form a second semiconductor structure serving as a reading and control layer;
and opening through holes in the first insulating layer and the second semiconductor structure, and depositing metal in the through holes to form an interconnection layer so as to interconnect the first semiconductor structure and the second semiconductor structure.
Preferably, the low-temperature MOS transistor is an HKMG type CMOS transistor; the first material layer is any one of a monocrystalline silicon wafer, a monocrystalline germanium wafer or an SOI substrate.
Preferably, the first material layer is bonded on the first insulating layer by using any one of a silicon-silicon direct bonding process, a metal surface bonding process, a polymer adhesive layer bonding process or a eutectic bonding process.
Preferably, the step of bonding the first material layer on the first insulating layer by using the silicon-silicon direct bonding process includes:
sequentially carrying out planarization treatment and cleaning treatment on the surface of the first insulating layer; a layer of single-layer water molecules is reserved on the surface of the first insulating layer;
carrying out oxidation treatment on the surface of the first material layer to form an oxidized surface;
inverting the first material layer through the oxidation surface to keep the surface of the first insulating layer with the water molecules; carrying out low-temperature bonding treatment on the oxidized surface and the surface of the first insulating layer in a face-to-face mode;
and carrying out annealing treatment on the formed structure so as to realize bonding interconnection of the first material layer and the first insulating layer.
Preferably, after forming the oxidized surface and before inverting the first material layer on the surface of the first insulating layer; and carrying out plasma activation treatment on the oxidized surface and the surface of the first insulating layer.
Preferably, in the low-temperature bonding treatment of the oxidized surface and the surface of the first insulating layer, a mechanical pressing treatment is performed on the surface of the first material layer.
Preferably, the first and second insulating layers are SiO2、Si3N4Or SiN, wherein the thickness of the first insulating layer and the second insulating layer is 300 nm-3 μm.
Preferably, the temperature for manufacturing the low-temperature MOS transistor at low temperature is T; wherein 0< T <500 ℃.
Preferably, the step of manufacturing the low temperature MOS transistor at a low temperature includes:
fabricating an active region on the first substrate layer at a low temperature;
manufacturing a sacrificial gate on the active region at a low temperature; forming source and drain extension regions in the active regions at two sides of the sacrificial gate, and forming a side wall on the side wall of the sacrificial gate;
performing source-drain doping in the active regions on two sides of the sacrificial gate to form a source/drain region;
depositing an oxidation dielectric layer on the formed structure, and carrying out second planarization treatment on the oxidation dielectric layer until the top of the sacrificial gate is exposed;
and carrying out replacement gate processing and forming metal contacts of a plurality of low-temperature MOS transistors.
Preferably, the source and drain doping is impurity heavily doped or fully silicided metal.
Meanwhile, the invention also provides a three-dimensional NAND memory, which comprises:
a first semiconductor structure as a three-dimensional vertical memory array; wherein the three-dimensional vertical memory array includes a plurality of three-dimensional vertical memory cells, and a first insulating layer formed on the plurality of three-dimensional vertical memory cells;
the second semiconductor structure is used as a reading and control layer and comprises a plurality of low-temperature MOS transistors and second insulating layers formed on the low-temperature MOS transistors;
an interconnect layer vertically positioned in the first insulating layer, second semiconductor structure to interconnect the first semiconductor structure, second semiconductor structure;
the low-temperature MOS transistors are formed on the first insulating layer, and substrates of the low-temperature MOS transistors are bonded and connected with one side of the first insulating layer far away from the first semiconductor structure.
Preferably, the low-temperature MOS transistor is an HKMG type CMOS transistor.
Preferably, the first and second insulating layers are SiO2、Si3N4Or SiN; the thickness of the first insulating layer and the second insulating layer is 300nm to 3 mu m.
Compared with the prior art, the preparation method provided by the invention has the advantages that the logic and storage circuits are respectively formed through the upper layer and the lower layer, the 3D storage with higher precision and higher density can be realized by utilizing the on-chip transfer of the monocrystalline silicon material and the low-temperature process (generally lower than 500 ℃), the alignment precision can reach below 50nm and is determined by the photoetching process instead of the alignment process; the internal bandwidth is greatly improved, and the storage efficiency and performance are improved; the reliability problem in the process of stacking the read control circuit and the storage unit caused by the process stress of the finished read circuit is reduced, and the yield of the 3D flash memory is improved.
The three-dimensional NAND memory provided by the invention also has the advantages of small occupied area, high quality and simple structure.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flow chart of a method for fabricating a three-dimensional NAND memory according to the present invention; fig. 2 to 6 are structural diagrams corresponding to each step of the method for manufacturing a three-dimensional NAND memory according to the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In order to overcome the technical problems that in the existing 3D NAND bonding process, an extremely thin substrate is easy to generate stress, a read and control circuit chip prepared in advance is easy to generate a large defect, circuit defects are caused, and a complex improvement process is needed, the invention provides a three-dimensional NAND memory and a preparation method thereof.
The preparation method of the three-dimensional NAND memory disclosed by the invention comprises the following steps as shown in FIG. 1:
s1, preparing a first semiconductor structure as a three-dimensional vertical storage array; the three-dimensional vertical memory array comprises a plurality of three-dimensional vertical memory cells and a first insulating layer formed on the plurality of three-dimensional vertical memory cells;
step S1 specifically includes the following steps:
s11, as shown in fig. 2, providing a substrate 1;
s12, as shown in fig. 3, fabricating a plurality of three-dimensional vertical memory arrays 2, e.g., 3D NAND strings, on a substrate 1, wherein the step of forming the plurality of NAND strings may further comprise the steps of:
forming isolation regions and doped regions on the substrate 1 (not shown, conventional techniques);
forming a plurality of conductor/insulator stacks 4 on a substrate 1;
forming a semiconductor channel 3 extending in a vertical direction and through the plurality of conductor/insulator stacks 4;
forming an epitaxial layer (not shown, conventional techniques) in contact with the semiconductor channel;
a first insulating layer 5 is formed covering the 3D NAND string.
It should be noted that the above-described structure can be formed in various ways. How to form the above-described structure is not essential to the present invention, and thus, in the present specification, it is only briefly described so that those skilled in the art can easily implement the present invention. It is fully contemplated by one of ordinary skill in the art that the above-described structures may be otherwise made.
S2, as shown in fig. 4, bonding the first material layer 6 on the first insulating layer 5; performing first thinning treatment and first surface treatment on the first material layer 6 to form a first substrate layer 6;
in this step, any one of a silicon-silicon direct bonding process, a metal surface bonding process, a polymer bonding layer bonding process or a eutectic bonding process may be adopted to bond the first material layer on the first insulating layer; the first material layer can be any one of a monocrystalline silicon wafer, a monocrystalline germanium wafer or an SOI substrate; of course, the first material layer may be any semiconductor material that meets the operational requirements.
Specifically, if the first material layer is a monocrystalline silicon wafer or an SOI substrate; a silicon-silicon direct bonding process may be used to bond the first material layer on the first insulating layer, and the specific operation steps include:
s21, sequentially performing first planarization treatment and cleaning treatment on the surface of the first insulating layer; a layer of single-layer water molecules is reserved on the surface of the first insulating layer;
in the step, after the first insulating layer is deposited and formed, in order to ensure the subsequent bonding quality, first planarization treatment needs to be carried out on the first insulating layer, so that the overall height and the local height of the upper surface of the first insulating layer are flat; it is conceivable that a part of particles may remain on the surface of the first insulating layer after the first planarization process, and at this time, the first insulating layer needs to be subjected to a cleaning process to remove all the remaining particles and leave a single layer of water molecules on the upper surface of the first insulating layer.
Wherein the first planarization treatment may be performed on the upper surface of the first insulating layer by CMP (chemical mechanical polishing).
And S22, performing oxidation treatment on the surface of the first material layer to form an oxidized surface.
In this step, before silicon-silicon direct bonding, the upper surface of the first material layer needs to be oxidized to form an oxidized surface on the upper surface of the first material layer; wherein, the thickness range of the formed oxidation surface is as follows: 1nm to 500 nm.
S23, inverting the first material layer through the oxidation surface to keep the surface of the first insulating layer with water molecules; carrying out low-temperature bonding treatment on the oxidized surface and the surface of the first insulating layer in a face-to-face mode;
in the step, the first material layer is inverted on the surface of the first insulating layer with water molecules reserved through an oxidation surface, namely the oxidation surface of the first material layer is contacted with the water molecules on the upper surface of the first insulating layer; during the bonding process, the water molecules form hydrogen bonds with the oxygen atoms in the oxidation surface.
And S24, annealing the formed structure to realize bonding interconnection of the first material layer and the first insulating layer.
In the step, annealing treatment is carried out on the formed structure, and the formed hydrogen bond is converted into an Si-O bond; compared with a hydrogen bond, the Si-O bond has higher bonding strength, and the first insulating layer and the first material layer can be tightly bonded together, so that the device performance is improved.
Further, after a layer of single-layer water molecules is reserved on the surface of the first insulating layer, before the first material layer is inverted on the surface of the first insulating layer; i.e., after step S21, and before step S22; and carrying out plasma activation treatment on the upper surface of the first material layer and the upper surface of the first insulating layer so as to further remove impurity particles on the two surfaces and improve the bonding effect.
Further, in the low temperature bonding process of the oxidized surface on the first material layer and the upper surface of the first insulating layer, in the second stepThe surface of a material layer is subjected to mechanical pressure application treatment, so that the bonding effect is improved; wherein, the pressure intensity range of the mechanical pressing is as follows: 0 to 10kg/cm2。
Specifically, after the bonding is completed, a first thinning process and a first surface process need to be performed on the back surface of the first material layer to form a first substrate layer 6; wherein the first thinning treatment comprises back coarse grinding, back fine grinding and stress relief; specifically, the back surface is coarsely ground to reduce the layer thickness of the first material layer, and the back surface is finely ground to make the back surface of the first material layer highly flat for later preparation; the stress release and the first surface treatment can be carried out through wet etching or CMP polishing and other processes, so that the back quality of the first material layer is further improved, the surface physical damage is avoided, and the granularity is reduced;
if the first material layer is an SOI substrate, the intermediate buried oxide layer can be used as a barrier layer for first surface treatment; if the first material layer is a monocrystalline silicon wafer, the corrosion rate of the first surface treatment needs to be controlled so as to treat the layer thickness of the first material layer to be less than 500 nm; preferably to 50 to 100 nm.
S3, as shown in fig. 5, manufacturing a plurality of low temperature MOS transistors 7 on the first substrate layer 6 at a low temperature, and forming a second insulating layer 8 on the plurality of low temperature MOS transistors to form a second semiconductor structure as a readout and control layer;
in this step, the low temperature MOS transistor 7 may be a low temperature CMOS transistor. More specifically, the low temperature MOS transistor is an HKMG type CMOS transistor.
Specifically, the step of manufacturing the low-temperature MOS transistor 7 at a low temperature includes:
s31, manufacturing an active area on the first substrate layer 6 at a low temperature;
s32, manufacturing a sacrificial gate on the active region at a low temperature; forming source and drain extension regions in the active regions at two sides of the sacrificial gate, and forming a side wall on the side wall of the sacrificial gate;
depositing a grid electrode material of a sacrificial grid on an active area, etching the grid electrode material to form the sacrificial grid, and after the sacrificial grid is formed, forming a source drain extension area in the active area at two sides of the sacrificial grid through doping; and at the sacrificeDepositing a side wall material on the side wall of the livestock grid, and etching the side wall material to form a side wall; wherein, the grid material can be polysilicon; the side wall material can be SiO2Or SiN.
S33, performing source-drain doping in the active regions on the two sides of the sacrificial gate to form a source/drain region; specifically, the source and drain doping may be performed on the active regions on both sides of the sacrificial gate by using heavily doped impurities or fully silicided metal.
S34, depositing an oxidation dielectric layer on the formed structure, and carrying out second planarization treatment on the oxidation dielectric layer until the top of the sacrificial gate is exposed; in this step, an oxide dielectric layer is deposited on the formed structure; wherein, the height of the oxidation dielectric layer is enough to embed the protruding sacrificial gate; and processes such as CMP are adopted to carry out second planarization treatment on the sacrificial gate, so that the top of the sacrificial gate is exposed, and the replacement gate is convenient to carry out in the later stage.
And S35, performing replacement gate processing to form a plurality of low-temperature MOS transistors 7.
In the step, the sacrificial gate in the gate region is removed, and a gate dielectric layer and a gate are sequentially formed in the gate region.
After the preparation of the low-temperature MOS transistors 7 is completed, the second insulating layer 8 needs to be formed thereon, wherein the preparation material and the layer thickness of the second insulating layer 8 may be the same as those of the first insulating layer 5, or may be set according to specific situations.
It should be noted that, the manufacturing method provided by the present invention only adopts the operations described in steps S2 to S3 to sequentially form the second semiconductor structure (including the low temperature MOS transistor 14) on the first semiconductor structure; it is conceivable that the above operation may be repeated as appropriate to prepare the nth semiconductor structure; wherein N is greater than or equal to 1.
Preferably, the temperature at which the low-temperature MOS transistor 7 is manufactured at low temperature is T; wherein 0< T <500 ℃.
Preferably, the second insulating layer 8 is SiO2、Si3N4Or SiN, the second insulating layer 8 has a layer thickness of 300nm to 3 μm.
S4, as shown in fig. 6, a via is opened in the first insulating layer 5, the second insulating layer 8, and the second semiconductor structure, and a metal is deposited in the via to form an interconnect layer 9 to interconnect the first semiconductor structure and the second semiconductor structure.
In the step, after two layers of semiconductor structures are sequentially formed, the two layers of semiconductor structures need to be three-dimensionally interconnected; specifically, through holes are formed in the first insulating layer 5, the second insulating layer 8 and the second semiconductor structure, and the positions of the through holes are opposite to the positions of the semiconductor channels 3 of the low-temperature MOS transistors and the three-dimensional vertical storage array; after the through holes are formed, filling metal in the through holes so as to interconnect the semiconductor structures of all layers; and finishing the preparation of the three-dimensional NAND memory.
Meanwhile, the present invention also provides a three-dimensional NAND memory, as shown in fig. 6, comprising:
a first semiconductor structure as a three-dimensional vertical memory array 2, the three-dimensional vertical memory array 2 including a plurality of three-dimensional vertical memory cells, and a first insulating layer 5 formed on the plurality of three-dimensional vertical memory cells;
the second semiconductor structure is used as a reading and control layer and comprises a plurality of low-temperature MOS transistors 7 and second insulating layers formed on the low-temperature MOS transistors 7;
the interconnection layer 9 is vertically positioned in the first insulation layer 5 and the second semiconductor structure, so as to interconnect the first semiconductor structure and the second semiconductor structure;
wherein, a plurality of low temperature MOS transistors 7 are formed on the first insulating layer 5, and the substrate 6 of the plurality of low temperature MOS transistors 7 is bonded and connected with one side of the first insulating layer 5 far away from the first semiconductor structure.
By adopting the technical scheme, the plurality of low-temperature MOS transistors are bonded on the three-dimensional vertical storage array through the bonding process, so that the three-dimensional NAND memory with small occupied area and high quality is formed, and the complexity and the preparation difficulty of the three-dimensional NAND memory are reduced.
Further, the low-temperature MOS transistor 7 is a low-temperature CMOS transistor. Specifically, for example, the low-temperature MOS transistor is an HKMG type CMOS transistor 7.
By adopting the technical scheme, the CMOS transistor has low power consumption, strong anti-interference capability and easy integration, and is convenient for the preparation of a three-dimensional NAND memory; moreover, the circuit of the low-temperature CMOS has higher working speed and stronger reliability, works under low power supply voltage, has performance similar to that of a bipolar logic circuit, has higher integration and packaging density, and further reduces the occupied area of the three-dimensional NAND memory.
Further, the first insulating layer 5 and the second insulating layer 8 are made of SiO2、Si3N4Or SiN, and the thickness of the first insulating layer 5 and the second insulating layer 8 is 300nm to 3 μm.
In summary, in the preparation method of the three-dimensional NAND memory provided by the invention, the conventional NAND preparation method is adopted to prepare the plurality of NAND arrays, and the first insulating layers 5 are formed on the plurality of NAND arrays to correspondingly form the first semiconductor structures; bonding a first material layer 6 on the first insulating layer 5 to tightly combine the first insulating layer 5 and the first material layer 6, and then thinning and surface treating the first material layer 6; preparing a plurality of low-temperature MOS transistors 7 on the substrate at a low temperature, and forming second insulating layers 8 on the plurality of low-temperature MOS transistors 7 to correspondingly form second semiconductor structures; and forming an interconnection layer 9 to complete the preparation of the three-dimensional NAND memory.
Based on the above method, a stacked 3D NAND flash memory can be fabricated with a lower multi-layer 3D NAND memory cell on which is a read and control logic layer based on-chip transfer of single crystal semiconductor material.
Based on the above method, a stacked 3D NAND flash memory can be manufactured with a vertical interconnect channel size of the upper logic layer and the lower memory layer of less than 50 nm.
Based on the above method, the upper logic layer manufacturing method can be a CMOS manufacturing process, and the temperature is less than 500 ℃.
Based on the above method, the gate electrode in the upper CMOS manufacturing process can be a high-k metal gate structure instead.
Based on the above method, alternatively, the single crystal semiconductor bonding material may be single crystal silicon, single crystal germanium, or the like.
Based on the above method, alternatively, the device structure in the 3D memory cell may be a floating gate, a CTM structure, or the like.
Compared with the prior art, the preparation method provided by the invention has the advantages that the logic and storage circuits are respectively formed through the upper layer and the lower layer, the 3D storage with higher precision and higher density can be realized by utilizing the on-chip transfer of the monocrystalline silicon material and the low-temperature process (generally lower than 500 ℃), the alignment precision can reach below 50nm and is determined by the photoetching process instead of the alignment process; the internal bandwidth is greatly improved, and the storage efficiency and performance are improved; the reliability problem in the process of stacking the read control circuit and the storage unit caused by the process stress of the finished read circuit is reduced, and the yield of the 3D flash memory is improved.
The three-dimensional NAND memory provided by the invention also has the advantages of small occupied area and high quality.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (13)
1. A preparation method of a three-dimensional NAND memory is characterized by comprising the following steps:
preparing a first semiconductor structure as a three-dimensional vertical storage array; wherein the three-dimensional vertical memory array includes a plurality of three-dimensional vertical memory cells, and a first insulating layer formed on the plurality of three-dimensional vertical memory cells;
bonding a first material layer on the first insulating layer; performing first thinning treatment and first surface treatment on the first material layer to form a first substrate layer;
manufacturing a plurality of low-temperature MOS transistors on the first substrate layer at a low temperature, and forming a second insulating layer on the plurality of low-temperature MOS transistors to form a second semiconductor structure serving as a reading and control layer;
and opening through holes in the first insulating layer and the second semiconductor structure, and depositing metal in the through holes to form an interconnection layer so as to interconnect the first semiconductor structure and the second semiconductor structure.
2. The method for manufacturing a three-dimensional NAND memory according to claim 1, wherein the low-temperature MOS transistor is a HKMG type CMOS transistor; the first material layer is any one of a monocrystalline silicon wafer, a monocrystalline germanium wafer or an SOI substrate.
3. The method of claim 1, wherein the first material layer is bonded to the first insulating layer using any one of a silicon-silicon direct bonding process, a metal surface bonding process, a polymer adhesive layer bonding process, or a eutectic bonding process.
4. The method of claim 3, wherein the step of bonding the first material layer on the first insulating layer using the silicon-silicon direct bonding process comprises:
sequentially carrying out planarization treatment and cleaning treatment on the surface of the first insulating layer; a layer of single-layer water molecules is reserved on the surface of the first insulating layer;
carrying out oxidation treatment on the surface of the first material layer to form an oxidized surface;
inverting the first material layer through the oxidation surface to keep the surface of the first insulating layer with the water molecules; carrying out low-temperature bonding treatment on the oxidized surface and the surface of the first insulating layer in a face-to-face mode;
and carrying out annealing treatment on the formed structure so as to realize bonding interconnection of the first material layer and the first insulating layer.
5. The method according to claim 4, wherein after the oxidized surface is formed and before the first material layer is inverted on the surface of the first insulating layer, plasma activation processing is performed on the oxidized surface and the surface of the first insulating layer.
6. The method according to claim 4, wherein a mechanical pressing process is performed on the surface of the first material layer in the low-temperature bonding process of the oxidized surface and the surface of the first insulating layer.
7. The method according to claim 1, wherein the first and second insulating layers are made of SiO2、Si3N4Or SiN, wherein the thickness of the first insulating layer and the second insulating layer is 300 nm-3 μm.
8. The method according to claim 1, wherein the temperature at which the low-temperature MOS transistor is manufactured at a low temperature is T; wherein 0< T <500 ℃.
9. The method of claim 1, wherein the step of fabricating the low temperature MOS transistor at a low temperature comprises:
fabricating an active region on the first substrate layer at a low temperature;
manufacturing a sacrificial gate on the active region at a low temperature; forming source and drain extension regions in the active regions at two sides of the sacrificial gate, and forming a side wall on the side wall of the sacrificial gate;
performing source-drain doping in the active regions on two sides of the sacrificial gate to form a source/drain region;
depositing an oxidation dielectric layer on the formed structure, and carrying out second planarization treatment on the oxidation dielectric layer until the top of the sacrificial gate is exposed;
and carrying out replacement gate processing and forming metal contacts of a plurality of low-temperature MOS transistors.
10. The method of claim 9, wherein the source and drain doping is impurity heavy doping or fully silicided metal.
11. A three-dimensional NAND memory, comprising:
a first semiconductor structure as a three-dimensional vertical memory array; wherein the three-dimensional vertical memory array includes a plurality of three-dimensional vertical memory cells, and a first insulating layer formed on the plurality of three-dimensional vertical memory cells;
the second semiconductor structure is used as a reading and control layer and comprises a plurality of low-temperature MOS transistors and second insulating layers formed on the low-temperature MOS transistors;
an interconnect layer vertically positioned in the first insulating layer, second semiconductor structure to interconnect the first semiconductor structure, second semiconductor structure;
the low-temperature MOS transistors are formed on the first insulating layer, and substrates of the low-temperature MOS transistors are bonded and connected with one side of the first insulating layer far away from the first semiconductor structure.
12. The three-dimensional NAND memory of claim 11 wherein the low temperature MOS transistor is a HKMG type CMOS transistor.
13. The three-dimensional NAND memory of claim 11 wherein the first and second insulating layers are SiO2、Si3N4Or SiN; the thickness of the first insulating layer and the second insulating layer is 300nm to 3 mu m.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107658317A (en) * | 2017-09-15 | 2018-02-02 | 长江存储科技有限责任公司 | A kind of semiconductor device and preparation method thereof |
| CN109326557A (en) * | 2018-09-28 | 2019-02-12 | 长江存储科技有限责任公司 | Three-dimensional memory structure and manufacturing method |
| CN109817536A (en) * | 2019-02-15 | 2019-05-28 | 长江存储科技有限责任公司 | The forming method of bonding structure |
| CN110854117A (en) * | 2019-11-26 | 2020-02-28 | 中国科学院微电子研究所 | Three-dimensional static random access memory and preparation method thereof |
-
2020
- 2020-12-11 CN CN202011436746.9A patent/CN112635474A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107658317A (en) * | 2017-09-15 | 2018-02-02 | 长江存储科技有限责任公司 | A kind of semiconductor device and preparation method thereof |
| CN109326557A (en) * | 2018-09-28 | 2019-02-12 | 长江存储科技有限责任公司 | Three-dimensional memory structure and manufacturing method |
| CN109817536A (en) * | 2019-02-15 | 2019-05-28 | 长江存储科技有限责任公司 | The forming method of bonding structure |
| CN110854117A (en) * | 2019-11-26 | 2020-02-28 | 中国科学院微电子研究所 | Three-dimensional static random access memory and preparation method thereof |
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