CN112614855A

CN112614855A - Preparation method of semiconductor etched hole inner film layer and three-dimensional memory structure

Info

Publication number: CN112614855A
Application number: CN202011419075.5A
Authority: CN
Inventors: 何亚东; 张莉; 王新胜; 刘力挽; 王伟哲
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-12-07
Filing date: 2020-12-07
Publication date: 2021-04-06

Abstract

The invention provides a preparation method of a semiconductor etching hole inner film layer and a preparation method of a three-dimensional memory structure, wherein the preparation method of the etching hole inner film layer comprises the following steps: providing a semiconductor substrate with an etching hole, providing first raw material gas in the etching hole to form an initial material film layer, and introducing first purging gas to perform first purging; and providing second raw material gas, reacting with the initial material film layer to form an etching hole filling film layer, and introducing second purging gas to perform second purging. According to the method, the step of purging with the purging gas is introduced in the preparation process of the film layer in the hole, so that the monoatomic layer material layer can be obtained based on the first raw material gas, byproducts can be effectively removed in the film forming process in a simple mode, the process is simple, and the performance of a device can be improved.

Description

Preparation method of semiconductor etched hole inner film layer and three-dimensional memory structure

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a preparation method of an inner film layer of a semiconductor etching hole and a preparation method of a three-dimensional memory structure.

Background

As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and achieve lower cost per bit are becoming more and more popular. 3D memory is a technology for stacking data units, and stacking of more than 32 layers, even 72, 96, 128 or more layers of data units has been achieved. As the number of stacked layers increases, the extraction of memory structures throughout the stacked structure faces greater challenges.

At present, in a three-dimensional (3D) memory and a manufacturing process thereof, various holes to be filled, such as channel holes (channel holes) and gate line slits (gate line slits) of a device, often exist, and especially as the Aspect Ratio (AR) of the holes increases, removal of byproducts during formation of an in-hole film layer becomes very difficult, for example, the byproducts may be generated during deposition of a thin film, and the byproducts may generate side effects (side effects) in terms of device function and the like, and an effective film layer is difficult to obtain, so that an effective method for solving the above problems is urgently needed.

Therefore, it is necessary to provide a method for fabricating an in-hole film layer by etching a semiconductor and a method for fabricating a three-dimensional memory structure, so as to solve the above-mentioned problems in the prior art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing a semiconductor etching hole liner layer and a method for preparing a three-dimensional memory structure, which are used to solve the problems in the prior art that the by-product in the preparation of etching hole liner layer is difficult to be effectively removed, and thus it is difficult to prepare an effective film layer, which affects the device performance.

In order to achieve the above objects and other related objects, the present invention provides a method for preparing an in-hole film layer for semiconductor etching, the method comprising the steps of:

providing a semiconductor substrate, wherein an etching hole is formed in the semiconductor substrate;

providing a first raw material gas to form an initial material film layer on the inner wall of the etching hole based on the first raw material gas;

introducing a first purging gas from the top of the etching hole to perform first purging;

providing a second raw material gas to obtain an etching hole filling film layer based on the second raw material gas and the initial material film layer;

and introducing a second purging gas from the top of the etching hole to perform second purging.

Optionally, a specific preparation method for forming the etching hole filling film layer includes:

introducing the first feed gas for a first time period;

cutting off the first raw material gas, and introducing the first purge gas in a second time period;

cutting off the first purge gas, and introducing the second feed gas in a third time period;

cutting off the second feed gas, and introducing the second purge gas in a fourth time period;

the second purge gas is turned off.

Optionally, repeating the above steps at least once to obtain the etching hole filling film layer.

Optionally, before introducing the first raw material gas, the method further comprises performing a first raw material gas prefabrication process for a first preset time period; before the first purge gas is introduced, the method further comprises a first purge gas prefabricating process lasting for a second preset time; before the second raw material gas is introduced, the method further comprises a second raw material gas prefabricating process lasting for a third preset time; before the second purge gas is introduced, the method further comprises a second purge gas prefabricating process lasting for a fourth preset time.

Optionally, the processes of providing the first raw material gas, introducing the first purge gas, providing the second raw material gas, and introducing the second purge gas form a first cyclic process, and the preparation method includes a step of repeating the first cyclic process at least once to obtain the etching hole filling film layer.

Optionally, the forming manner of the hole-etching inner film layer includes an atomic layer deposition process, the hole-etching film layer is prepared based on a plurality of atomic layer deposition units, and the first cycle process is performed in the process of forming each atomic layer deposition unit.

Optionally, the preparation method further includes the steps of providing an nth raw material gas and introducing an nth purge gas, where N is an integer greater than or equal to 3, the N raw material gas reacts with a film layer formed after the N-1 raw material gas passes through, and the nth purge gas is introduced after the N raw material gas reacts.

Optionally, the first purge gas and the second purge gas are the same gas or a combination of gases, and both are introduced through the same pipeline.

Optionally, the first purge gas has a first flow rate and the second purge gas has a second flow rate, the second flow rate being between 3-4 times the first flow rate.

Optionally, the first purge gas is introduced in a normal distribution mode in the process of introducing the first purge gas; and introducing the second purge gas in a normal distribution mode in the process of introducing the second purge gas.

Optionally, the manner of introducing the first purge gas and the second purge gas includes: and introducing purge gas along the axial direction of the etching hole, and introducing at least one of the purge gas which is vertical to the axial direction of the etching hole and is introduced on the surface of the opening of the etching hole.

The invention also provides a preparation method of the three-dimensional memory structure, which comprises the following steps:

providing a semiconductor substrate;

forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises sacrificial layers and dielectric layers which are alternately laminated;

forming an etching hole penetrating the laminated structure to the semiconductor substrate;

and forming an inner film layer in the etching hole, wherein the inner film layer is prepared by the preparation method of the semiconductor etching hole inner film layer according to any one of the schemes, and the semiconductor substrate and the laminated structure on the semiconductor substrate form the semiconductor base.

Optionally, the etching hole includes a channel hole, the inner film layer formed in the channel hole includes a silicon oxide layer, the first raw material gas includes aminosilane, and the second raw material gas includes oxygen during the formation of the silicon oxide layer.

Optionally, the etching hole comprises a gate slit, the inner film layer formed in the gate slit comprises a metal tungsten layer, wherein, in the forming of the metal tungsten layer, the first raw material gas comprises WF₆The second raw material gas comprises B₂H₆。

According to the preparation method of the semiconductor etching hole inner film layer and the three-dimensional memory structure, the step of introducing the purging gas to purge in the preparation process of the hole inner film layer can obtain the monoatomic layer material layer based on the first raw material gas, can effectively remove byproducts in the film forming process in a simple mode, has a simple process, and is beneficial to improving the performance of a device.

Drawings

FIG. 1 is a flow chart of a process for etching an inter-via film in a semiconductor device according to the present invention.

Fig. 2 is a schematic structural diagram of a semiconductor substrate according to an embodiment of the invention.

FIG. 3 is a schematic structural diagram illustrating a formation of an initial material film according to an embodiment of the invention.

FIG. 4 is a schematic diagram illustrating a first purge performed according to a first embodiment of the present invention.

FIG. 5 is a diagram illustrating the formation of an etch hole filling film according to one embodiment of the present invention.

FIG. 6 is a schematic diagram of a second purge performed in accordance with one embodiment of the present invention.

Fig. 7 is a schematic diagram illustrating a specific example of forming a filling film layer according to one embodiment of the present invention.

FIG. 8 is a flow chart illustrating a process for fabricating a memory structure according to an embodiment of the invention.

FIG. 9 is a schematic view of a semiconductor substrate provided in the fabrication of a second memory structure according to an embodiment of the present invention.

FIG. 10 is a schematic diagram illustrating the formation of a stack structure and a trench hole in the fabrication of a second memory structure according to an embodiment of the present invention.

FIG. 11 is a schematic view of the formation of a bottom epitaxial layer in the fabrication of a second memory structure according to the present invention.

FIG. 12 is a schematic diagram illustrating the formation of a functional sidewall layer in the fabrication of a second memory structure according to the present invention.

Fig. 13 is a schematic view illustrating the formation of a channel layer and an insulation filling layer in the fabrication of a second memory structure according to an embodiment of the invention.

Fig. 14 is a top view of a gate line gap formed in the fabrication of a second memory structure according to an embodiment of the invention.

Fig. 15 is a cross-sectional view of a gate line gap formed in the fabrication of a second memory structure according to an embodiment of the invention.

FIG. 16 is a schematic view of forming a gate fill hole in the fabrication of a second memory structure according to the embodiment of the invention.

FIG. 17 is a schematic view of forming a gate body layer in the fabrication of a second memory structure according to the second embodiment of the present invention.

FIG. 18 is a schematic diagram of a sidewall spacer and a gap filling layer in the fabrication of a second memory structure according to an embodiment of the invention.

Description of the element reference numerals

1 semiconductor substrate

Etching holes 2

3 film layer of starting material

4 etching hole filling layer

100 semiconductor substrate

101 laminated structure

102 dielectric layer

103 sacrificial layer

104 channel hole

105 bottom epitaxial layer

106 functional sidewall layer

107 channel layer

108 insulating fill layer

109 air chamber

110 grid line gap

111 gate fill hole

112 gate body layer

113 sidewall spacer

114 gap filling layer

S1-S5, S1 '-S3' steps

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, "between … …" as used herein includes both endpoints.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in FIG. 1, the present invention provides a method for preparing an inner film layer of a semiconductor etching hole, comprising the following steps:

s1, providing a semiconductor substrate, wherein an etching hole is formed in the semiconductor substrate;

s2, providing a first raw material gas to form an initial material film layer on the inner wall of the etching hole based on the first raw material gas;

s3, introducing a first purge gas from the top of the etching hole to perform first purge;

s4, providing a second raw material gas to obtain an etching hole filling film layer based on the second raw material gas and the initial material film layer;

and S5, introducing a second purging gas from the top of the etching hole to perform second purging.

The method for forming an inner film layer of a semiconductor etching hole according to the present invention will be described in detail with reference to the accompanying drawings, which are shown in FIGS. 1-7. It should be noted that the above sequence does not strictly represent the preparation sequence of the preparation method of the semiconductor etching hole liner layer protected by the present invention, and those skilled in the art can make changes between steps according to routine choice in the art, and fig. 1 only shows one preparation step of the preparation method of the semiconductor etching hole liner layer in an example.

First, as described in S1 in fig. 1 and fig. 2, a semiconductor substrate 1 is provided, and an etching hole 2 is formed in the semiconductor substrate 1. The semiconductor substrate 1 may be a single-layer material layer or a stacked structure composed of multiple material layers. In addition, the etching hole 2 may be a hole formed by dry etching or a hole formed by wet etching. In an example, the etch holes 2 are holes with a high aspect ratio, e.g. the aspect ratio may be more than 10, e.g. 15, 20.

Next, as shown in S2 in fig. 1 and fig. 3, a first raw material gas is provided to form a starting material film layer 3 on the inner wall of the etching hole 2 based on the first raw material gas. Wherein the first feed gas is one of the feed materials which ultimately form the desired membrane layer. The invention designs the film forming mode, firstly, one of the raw material gases is introduced into the etching hole 2. In one example, for example, in an Atomic Layer Deposition (ALD) process, a monoatomic layer film of a source gas, i.e., the starting material film 3, is formed first. For example, for forming a layer of silicon oxide material, the first source gas is a source of silicon and can be a silane, such as, for example, di-t-butylsilane.

Next, as shown in S3 of fig. 1 and fig. 4, a first purge gas is introduced from the top of the etching hole 2 to perform a first purge. The purging process is mainly used for forming the monoatomic layer film, redundant first raw material gas deposited on the inner wall of the etching hole 2 is removed, the monoatomic layer film is favorably ensured to be formed, and the monoatomic layer initial material film 3 is obtained.

Next, as shown in S4 of fig. 1 and fig. 5, a second raw material gas is provided to etch the hole-filling film layer 4 based on the second raw material gas and the initial material film layer 3. The etching hole filling film layer 4 is a material layer to be formed, that is, the second raw material gas reacts with the initial material film layer 3 which has been formed to obtain a final filling film layer. For example, in one example, the radio frequency is turned on (RF on) to perform the reaction between the feed gases. For example, for forming a layer of silicon oxide material, the second feed gas is an oxidizing source, such as oxygen.

In one example, one can select which of the first feed gas to inject first based on the properties of the two or more feed gases, for example, the main material is selected to inject first and the auxiliary material is selected to inject second, such as WF6 for W metal, the first feed gas is B2H 6; in addition, the oxidizing and reducing materials may be introduced, or the first introduction may be performed with strong adsorption.

Finally, as shown in S5 in FIG. 1 and FIG. 6, a second purge gas is introduced from the top of the etching hole to perform a second purge. The purging in this step is mainly used for removing by-products, wherein some by-products are formed simultaneously during the reaction to form the finally required film layer, and if the by-products exist in the etching holes 2, the by-products will finally have a serious influence on the device performance and the like, so the by-products are removed by the purging in this step, and the purer etching hole filling film layer 4 is obtained.

In an example, the forming manner of the hole-etching inner film layer 4 includes an Atomic Layer Deposition (ALD) process, wherein the hole-etching film layer 4 is prepared based on a plurality of atomic layer deposition units based on the ALD process, that is, the hole-etching filling film layer 4 is formed by stacking a plurality of atomic layer deposition units, each atomic layer deposition unit forming process is a deposition cycle, and the hole-etching filling film layer 4 is finally obtained by performing a plurality of deposition cycles.

The steps of providing the first raw material gas, introducing the first purge gas, providing the second raw material gas and introducing the second purge gas are performed in the process of forming each atomic layer deposition unit, namely in each deposition period, and form a first cyclic process. For example, a first atomic layer deposition unit is formed based on the above process steps, then the steps of providing a first raw material gas, introducing a first purge gas, providing a second raw material gas, and introducing a second purge gas are performed on the first atomic layer deposition unit to form a second atomic layer deposition unit, and so on, the steps of providing a first raw material gas, introducing a first purge gas, providing a second raw material gas, and introducing a second purge gas are repeated to obtain the etching hole filling layer 4 based on the atomic layer deposition process. Namely, the forming mode of the etching hole inner film layer comprises an atomic layer deposition process, the etching hole film layer is prepared on the basis of a plurality of atomic layer deposition units, and the first cycle process is executed in the process of forming each atomic layer deposition unit.

Referring to fig. 7, as an example, a specific preparation method for forming the etching hole filling film layer is provided, which includes:

introducing the first feed gas in a first time t 1; cutting off the first feed gas, and introducing the first purge gas in a second time period t 2; cutting off the first purge gas and introducing the second feed gas for a third time period t 3; cutting off the second feed gas, and introducing the second purge gas in a fourth time period t 4; the second purge gas is turned off.

Specifically, in this example, the respective gases (the feed gas and the purge gas) are introduced separately, i.e., in time intervals that do not overlap with each other, so as to facilitate efficient performance of the respective steps. In an alternative example, the time periods are consecutive, for example, the first raw material gas supply (as shown in the figure, Precursor Dose) is immediately disconnected after the first raw material gas supply is completed for a first time period t1, and the step of introducing the first Purge gas (as shown in the figure, LFG Purge) for a second time period t2 is immediately performed, and so on.

In one example, the above steps are repeated at least once to obtain the etching hole filling film layer, that is, the cyclic steps of providing a first raw material gas, introducing a first purge gas, providing a second raw material gas, and introducing a second purge gas are performed at least once, and the above four steps can be referred to as one cycle. For example, in the atomic layer deposition process, the above-mentioned one-cycle process is performed for each atomic layer deposition unit, and then the above-mentioned steps are repeated to form the next atomic layer deposition unit.

By way of example, for silicon oxide, the first feed gas is a source of silicon and the second feed gas is oxygen. The flow rate of the first raw material gas is between 1000 and 1500sccm, which can be 1200sccm, 1250sccm, 1300 sccm; the duration of the passage time (first time period t1) is between 0.15 and 0.75s, and may be, for example, 0.2s, 0.3s, 0.5s, 0.6 s; in another example, the gas may be introduced in the form of saturated vapor using an inert gas such as argon as a carrier gas. Through the design, the formation of the initial material film layer of the monoatomic layer is further facilitated. The flow rate of the second raw material gas may be designed according to the actual product, and is preferably excessive relative to the product components; the duration of the feeding period (first period t3) may be the same as the feeding period of the first raw material gas, and may be adjusted according to the reaction sufficiency, for example, may be between 0.3 and 0.9, and may be, for example, 0.3s, 0.5s, 0.6s, or 0.8.

With continued reference to fig. 7, in an example, the introducing of the first raw material gas includes a first raw material gas preparation (e.g., Precursor preparation in the figure) for a first preset time period y1 for the first raw material gas pipeline, the introducing of the first purge gas includes a first purge gas preparation (e.g., purge gas preparation in the figure) for a second preset time period y2 for the first purge gas pipeline, and the introducing of the second raw material gas includes a second raw material gas preparation (e.g., oxygen introduction in the figure, O3 for a third preset time period y3 for the second raw material gas pipeline₂Dose) before the second purge gas is introduced, the second purge gas line is subjected to a second purge gas preparation (LFG Charge, as shown in the figure) for a fourth preset time period y 4.

As an example, the prefabrication time can be 1/4-2/3 and 1/2 of the time for introducing the later reaction raw material gas, can be 1/2, and of course, can also be equal, for example, the time length of y1 is equal to the time length of t1, and the time length of y2 is equal to the time length of t2, and of course, corresponding changes can also be made according to the setting of the machine.

As an example, the duration of the first preset duration y1 is equal to the sum of the durations of the second duration t2, the third duration t3 and the fourth duration t 4; the duration of the second preset duration y2 is equal to the duration of the first duration t 1; the duration of the third preset duration y3 is equal to the sum of the durations of the fourth duration t4, the first duration t1 and the second duration t 2; the duration of the fourth preset duration y4 is equal to the duration of the third duration t 3. The method is favorable for forming the initial material film layer and the etching hole filling film layer, and is particularly suitable for the ALD multi-cycle process, the time is compact, the time is saved, and the productivity is improved.

As an example, the preparation method further includes the steps of providing an nth raw material gas and introducing an nth purge gas, wherein N is an integer greater than or equal to 3, the nth raw material gas reacts with the membrane layer formed after the N-1 raw material gas passes through, and the nth purge gas is performed after the nth raw material gas reacts. That is, the raw material for forming a certain intermediate membrane layer may be divided into a first raw material gas, a second raw material gas, and an nth raw material gas, and each raw material gas is introduced separately, and purging is performed once after each introduction. In one example, when N is greater than or equal to 3, the second to nth raw material gases may be simultaneously introduced, and two steps of operations are performed, wherein a monoatomic layer is formed first on the basis of the first raw material gas, and then all the following raw material gases are introduced and simultaneously radio frequency opened to form the target material layer.

For example, the first purge gas and the second purge gas are the same type, and both are the same gas or gas combination, and preferably both are introduced through the same pipe. That is, the same gas may be selected for both, and for example, Ar, N2, etc., or other inert gases, and one or more of the above gases may be mixed. In addition, the two can be introduced based on the same pipeline, so that the equipment is simplified.

In one example, the first purge gas has a first flow rate and the second purge gas has a second flow rate to remove byproducts from the etch holes, including facilitating deposition of a single atomic layer of the material, both of which can be considered as large flow (large flux gas flow) to create a pressure difference in the holes based on bernoulli's principle, with a large top flow rate and a low next flow rate and a high pressure, to create a pressure difference, such that no material is required to be exhausted by the purge gas in this step.

By way of example, the second flow rate is between 3-4 times, e.g., 3.5 times, 3.8 times, the first flow rate to facilitate final material layer formation. In one example, the first flow rate is between 10000-; the second flow rate was 45000sccm to facilitate removal of reaction byproducts during thin film deposition.

As an example, the first purge gas is introduced in a normal distribution manner during the introduction of the first purge gas; and introducing the second purge gas in a normal distribution mode in the process of introducing the second purge gas. Therefore, the method is favorable for forming the purging gas based on the modes of quick opening and quick closing, and the purging effect is improved. Here, the normal distribution may mean that the flow rate is normally distributed in the time period in which the gas is introduced, and in this case, the second flow rate is between 3 and 4 times the first flow rate may mean that the peak flow rate is in a multiple relationship. Of course, the same flow rate may be maintained during purging.

As an example, the manner of passing the first purge gas and the second purge gas includes: and introducing purge gas along the axial direction of the etching hole, and introducing at least one of the purge gas which is vertical to the axial direction of the etching hole and is introduced on the surface of the opening of the etching hole. That is, the purging direction of the purge gas may be adjusted according to actual requirements, taking the first purge gas as an example, the purge gas may be introduced along the axial direction of the etching hole, that is, the purge gas is purged toward the etching hole to form a distribution of lower high pressure and upper low pressure, as shown in the introduction manner in fig. 4, where the arrow direction indicates that the high pressure is directed to the low pressure; in addition, in another example, the purge gas may be blown along the surface of the semiconductor substrate (not shown in the figure), that is, blown perpendicular to the direction of the etching holes, and the purge gas is blown above the openings of the etching holes, preferably, contacts the top opening during the purge process, and may be continuously purged, or may be blown from left to right on the surface of the semiconductor substrate, and the purge process passes through the openings of the etching holes, and the positions of the openings may have a small gas pressure, and it is advantageous to blow no by-products or the like into the holes directly while reducing the gas pressure of the openings.

Example two

As shown in fig. 8, the present invention further provides a method for manufacturing a three-dimensional memory structure, which includes the following steps:

s1', providing a semiconductor substrate;

s2', forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises sacrificial layers and dielectric layers which are alternately laminated;

s3', forming an etching hole penetrating the laminated structure to the semiconductor substrate;

s4', forming an inner film layer in the via, the inner film layer being prepared according to the method for preparing an inner film layer of a semiconductor via according to any one of the embodiments, wherein the semiconductor substrate and the stacked structure thereon form the semiconductor base.

The method for forming an inner film layer of a semiconductor etching hole according to the present invention will be described in detail with reference to the accompanying drawings, which are shown in FIGS. 8-18. It should be noted that the above sequence does not strictly represent the preparation sequence of the preparation method of the semiconductor etching hole liner layer protected by the present invention, and those skilled in the art can make changes between steps according to routine choice in the art, and fig. 1 only shows one preparation step of the preparation method of the semiconductor etching hole liner layer in an example.

First, as shown in S1' in fig. 8 and fig. 9, the semiconductor substrate 100 is provided. The semiconductor substrate 100 includes, but is not limited to, a silicon substrate. The semiconductor substrate 100 may be selected according to actual requirements of a device, and may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon-on-Insulator (SOI) substrate, a Germanium-on-Insulator (GOI) substrate, and the like, in other embodiments, the semiconductor substrate 100 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, Silicon carbide, and the like, and the semiconductor substrate 100 may also be a stacked structure, such as a Silicon/Germanium-Silicon stacked layer, and the like. As an example, the semiconductor substrate 100 may be a single crystal silicon wafer, for example. The semiconductor substrate 100 may be ion-doped, P-doped, or N-doped.

Next, as shown in S2' in fig. 8 and fig. 10, a stacked structure 101 is formed on the semiconductor substrate 100, wherein the stacked structure 101 includes a sacrificial layer 103 and a dielectric layer 102 that are alternately stacked. That is, the stacked structure 101 includes sacrificial layers 103 and dielectric layers 102 alternately stacked in a direction perpendicular to the surface of the semiconductor substrate 100. In this embodiment, the semiconductor substrate 100 and the stacked structure 101 constitute the semiconductor base in the first embodiment.

Specifically, the material of the dielectric layer 102 includes, but is not limited to, silicon oxide, and the material of the sacrificial layer 103 includes, but is not limited to, silicon nitride. Optionally, the dielectric layer and the sacrificial layer have a certain selection ratio in the same etching/etching process to ensure that the dielectric layer is hardly removed when the sacrificial layer is removed. The stacked structure 101 may be formed by a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD), or the like. The number of layers of the dielectric layer and the sacrificial layer in the stacked structure may include 32 layers, 64 layers, 96 layers, 128 layers, or the like, and the number of layers and the thickness of the dielectric layer and the sacrificial layer may be set according to actual needs, which is not limited herein.

Next, as shown in S3' of fig. 8 and fig. 10-11 and 14-16, etching holes are prepared in the stacked-layer structure 101.

Finally, forming an inner film layer in the etching hole as shown in S4' of fig. 8 and fig. 12, wherein the inner film layer is prepared based on the method for preparing an inner film layer of a semiconductor etching hole according to any one of the embodiments, and the semiconductor substrate 100 and the stacked structure 101 on the semiconductor substrate 100 form the semiconductor base according to the first embodiment.

In an example, the etching hole formed in this embodiment may be a channel hole (channel hole)104, and may also be a gate line slit (gate line slit)110, and in other examples, the sacrificial layer 103 may also be removed based on the gate line slit 110 to form a gate filling hole 111 correspondingly.

Correspondingly, in the embodiment, when the etching hole is the channel hole 104, the formed inner film layer may be an insulating filling layer 108 prepared in the channel hole 104, wherein, in an example, the channel layer 107 and the insulating filling layer 108 are prepared in the channel hole 104. In addition, when the etching hole is the gate slit 111, the formed inner film layer may be a slit filling layer 114 prepared in the gate slit 111. In addition, when the etching hole is the gate filling hole 111, the formed inner film layer may be the gate body layer 112 prepared in the gate filling hole 111.

Specifically, in an embodiment, as shown in fig. 10, the channel hole 104 is formed in the stacked structure 101 and may be formed by an etching process. The channel hole 104 constitutes the etching hole 2 in the first embodiment, and further, after the channel hole 104 is formed, a channel layer 107 is prepared in the channel hole to finally form a channel structure of a device, such as a channel structure of 3D NAND. In one example, the channel layer 107 includes a polysilicon layer.

Next, referring to fig. 12 and 13, as an example, a functional sidewall layer 106 is further formed in the channel hole 104, wherein the functional sidewall layer 106, the channel layer 107, and the insulating fill layer 108 are sequentially arranged from outside to inside. In one example, the functional sidewall layer 106 includes silicon oxide, silicon nitride, and silicon oxide layers arranged from the inner wall surface of the trench hole toward the center, forming an ONO sidewall structure. The material of the insulating filling layer 108 includes, but is not limited to, silicon oxide. In addition, an air cavity 109 is formed in the insulating filling layer 108 to facilitate stress buffering.

The insulating filling layer 108 can be prepared by using the preparation method for etching the hole filling film layer in the embodiment. For example, for forming the silicon oxide etching hole filling layer, the flow rate of the first raw material gas aminosilane can be between 1000-2000sccm, such as 1200sccm, 1500sccm, 1800sccm, and the flowing time can be between 0.15-0.75s, such as 0.3s, 0.5s, 0.6 s; the flow rate of the second raw material gas oxygen can be between 4500-5500sccm, such as 4800sccm, 5000sccm, 5200sccm, and the flowing time can be between 0.3-0.9s, such as 0.5s, 0.6s, 0.8 s.

Referring to fig. 11-13, by way of example, the method of preparation further includes the step of preparing the bottom epitaxial layer 105 in a manner that includes: the channel hole 104 is formed to extend into the semiconductor substrate 100 as well, as shown in fig. 10; growing the bottom epitaxial layer 105 on the semiconductor substrate 100 at the bottom of the channel hole 104 before forming the functional sidewall layer 106, for example, a selective epitaxial growth process (SEG) may be employed, the functional sidewall layer 106 being formed on the sidewalls of the channel hole 104 and extending to the surface of the bottom epitaxial layer 105, as shown in fig. 11-12; further comprising the step of removing the functional sidewall layer 106 at the bottom of the channel hole to expose the bottom epitaxial layer 105, thereby contacting the channel layer 107 with the bottom epitaxial layer 105 when forming the channel layer 107, as shown in fig. 13, for common source connection.

As shown in fig. 14 to 15, in an example, the etching hole may also be the formed gate slit 110, and the manufacturing of the three-dimensional memory structure further includes a step of manufacturing a gate line slit 110 in the stacked structure 101, and in an example, the gate line slit 110 further extends into the semiconductor substrate. Further, as shown in fig. 16, a step of removing the sacrificial layer 103 in the stacked structure based on the gate line slit 110 is further included to correspondingly form a gate filling hole 111 at a position where the sacrificial layer 103 is removed. Both the gate line slit 110 and the gate filling hole 111 based on the gate line slit 110 can be used as the etching hole 2 in the first embodiment, and the film layers prepared in the gate line slit 110 and the gate filling hole 111 can adopt the mode in the first embodiment.

As shown in fig. 17, a gate body layer 112 is formed in the gate filling hole 111 as an example, wherein the gate body layer includes a metal tungsten layer, but other material layers may be selected. Wherein the tungsten layer can be prepared by the method of the first embodiment, for example, in one embodiment, the first raw material gas can be WF6, the flow rate can be between 1000-; the second raw material gas is B2H6, the flow rate can be between 4500-5500sccm, can be 4800sccm, 5000sccm, 5200sccm, the flowing time is between 0.3-0.9s, can be 0.5s, 0.6s, 0.8 s. In an example, a surface transition layer (not shown) prepared on the surface of the gate body layer 112 is further formed in the gate filling hole 111, for example, in an example, the surface transition layer includes a titanium nitride layer and a titanium layer.

As shown in fig. 18, after the gate body layer 112 is formed, a step of forming a gap filling layer 114 in the gate line gap 110 is further included, and a material of the gap filling layer 114 includes, but is not limited to, a metal tungsten layer; in addition, a sidewall spacer 113 prepared on the surface of the gap filling layer 114 is further formed in the gate line gap 110, and the sidewall spacer 113 includes but is not limited to an oxide layer; similarly, the gap filling layer 114 can also be prepared by the process of the embodiment.

For example, in one embodiment, during the formation of the gap-filling layer 114, the first material gas is selected to be WF6, the flow rate may be between 1000 sccm and 2000sccm, such as 1200sccm, 1500sccm and 1800sccm, and the flowing time is between 0.15 s and 0.75s, such as 0.3s, 0.5s and 0.6 s; the second material gas is selected as B2H6, the flow rate can be between 4500-5500sccm, for example 4800sccm, 5000sccm, 5200sccm, and the flowing time can be between 0.3-0.9s, for example 0.5s, 0.6s, 0.8 s.

In summary, according to the preparation method of the semiconductor etching hole inner film layer and the three-dimensional memory structure, the step of purging by the purge gas is introduced in the preparation process of the hole inner film layer, so that the monoatomic layer material layer can be obtained based on the raw material gas, byproducts can be effectively removed in the film forming process through a simple method, the process is simple, and the device performance can be improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A preparation method of a film layer in a semiconductor etching hole is characterized by comprising the following steps:

providing a second raw material gas to obtain an etching hole filling film layer based on the second raw material gas and the initial material film layer; and introducing a second purging gas from the top of the etching hole to perform second purging.

2. The method as claimed in claim 1, wherein the step of forming the hole-filling film comprises:

introducing the first feed gas for a first time period; cutting off the first feed gas, and introducing the first purge gas in a second time period; cutting off the first purge gas, and introducing the second feed gas in a third time period; cutting off the second feed gas, and introducing the second purge gas in a fourth time period; the second purge gas is turned off.

3. The method as claimed in claim 2, wherein the step of etching the via hole liner with a semiconductor is further performed,

before the first raw material gas is introduced, the method further comprises a first raw material gas prefabricating process which lasts for a first preset time;

before the first purge gas is introduced, the method further comprises a first purge gas prefabricating process lasting for a second preset time;

before the second raw material gas is introduced, the method further comprises a second raw material gas prefabricating process lasting for a third preset time;

before the second purge gas is introduced, the method further comprises a second purge gas prefabricating process lasting for a fourth preset time.

4. The method as claimed in claim 3, wherein the sum of the duration of the second period of time, the duration of the third period of time and the duration of the fourth period of time is equal to the duration of the first predetermined period of time; the duration of the second preset duration is equal to the duration of the first duration; the sum of the fourth time length, the first time length and the second time length is equal to the time length of the third preset time length; the duration of the fourth preset duration is equal to the duration of the third duration.

5. The method as claimed in claim 1, wherein the steps of providing the first source gas, introducing the first purge gas, providing the second source gas and introducing the second purge gas form a first cycle, and the method comprises repeating the first cycle at least once to obtain the etch hole filling film; the forming mode of the etching hole inner film layer comprises an atomic layer deposition process, the etching hole film layer is prepared on the basis of a plurality of atomic layer deposition units, and the first cycle process is executed in the process of forming each atomic layer deposition unit.

6. The method as claimed in claim 1, further comprising the steps of providing an Nth raw material gas and introducing an Nth purge gas, wherein N is greater than or equal to 3, the Nth raw material gas reacts with the film layer formed after the Nth-1 raw material gas passes through, and the Nth purge gas is introduced after the Nth raw material gas reacts.

7. The method as claimed in any one of claims 1 to 6, wherein the first purge gas and the second purge gas are the same gas or a combination of gases, and both are introduced through the same pipeline.

8. The method as claimed in claim 7, wherein the first purge gas is introduced at a first flow rate, and the second purge gas is introduced at a second flow rate, wherein the second flow rate is 3-4 times the first flow rate.

9. The method as claimed in claim 7, wherein the first purge gas is introduced in a normal distribution manner during the introduction of the first purge gas; and introducing the second purge gas in a normal distribution mode in the process of introducing the second purge gas.

10. The method as claimed in claim 7, wherein the introducing the first purge gas and the second purge gas comprises: and introducing purge gas along the axial direction of the etching hole, and introducing purge gas perpendicular to the axial direction of the etching hole and on the surface of the opening of the etching hole.

11. A preparation method of a three-dimensional memory structure is characterized by comprising the following steps:

providing a semiconductor substrate;

forming an inner film layer in the etching hole, wherein the inner film layer is prepared on the basis of the preparation method of the semiconductor etching hole inner film layer as claimed in any one of claims 1 to 9, and the semiconductor substrate and the laminated structure on the semiconductor substrate form the semiconductor base.

12. The method of claim 11, wherein the etch hole comprises a channel hole, the inner film layer formed in the channel hole comprises a silicon oxide layer, wherein the first material gas comprises an aminosilane and the second material gas comprises oxygen during the formation of the silicon oxide layer.

13. The method of claim 11, wherein the etch hole comprises a gate gap, the inner film layer formed in the gate gap comprises a metal tungsten layer, and wherein the first material gas comprises WF during the formation of the metal tungsten layer₆The second raw material gas comprises B₂H₆。