CN112445302B

CN112445302B - Starting method and device of digital currency mining machine and digital currency mining machine

Info

Publication number: CN112445302B
Application number: CN202011309260.9A
Authority: CN
Inventors: 马伟彬; 黄理洪; 杨作兴; 巫跃凤; 郭海丰
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2021-08-27
Anticipated expiration: 2040-11-20
Also published as: CN112445302A

Abstract

The embodiment of the invention provides a starting method and device of a digital currency mining machine and the digital currency mining machine. The digital currency mining machine comprises N force calculation plates which are connected in series to form a series power supply structure, wherein a power supply positive terminal of a first force calculation plate in the series power supply structure is connected with a positive terminal of a power supply, a power supply negative terminal of a last force calculation plate in the series power supply structure is connected with a negative terminal of the power supply, each force calculation plate comprises a plurality of operation chips, and N is a positive integer of at least 2; the method comprises the following steps: sending a start signal to an ore refrigeration before turning on the power supply; turning on the power supply; and controlling each operation chip in the N operation boards to synchronously start the cores in a gradual mode. The embodiment of the invention improves the voltage balance between the force calculation boards and in the force calculation boards and can also ensure the accuracy of clock signals.

Description

Starting method and device of digital currency mining machine and digital currency mining machine

Technical Field

The invention belongs to the technical field of information, and particularly relates to a starting method and device of a digital currency mining machine and the digital currency mining machine.

Background

With the rapid development of supercomputers, digital currency mining machines have moved from video card mining machines to lower power and lower cost Application Specific Integrated Circuit (ASIC) mining machines.

Digital currency mining machines typically include a plurality of computing power boards. In order to improve the computational power, the computational power board is generally a circuit board which is arranged in a chip array mode. Typically, the computation board is an operation array unit composed of several operation chips (such as ASIC, CPU or GPU). The core voltage power supply of the operation chip in the computation board mostly adopts a series power supply mode, wherein the positive power supply and the negative power supply (ground) of the operation chip are connected end to form a multistage series voltage domain, and each voltage domain is provided with one or more operation chips. Meanwhile, the force calculation boards are connected in parallel to obtain power supply from a power supply.

However, as the power demand of the mining machine is gradually increased, the power of the mining machine is higher and higher, the output current of the power supply is larger and larger, the power supply output loss proportional to the square of the current is increased sharply, and the power supply efficiency is reduced.

Furthermore, the power supply needs to provide a lower voltage (e.g., 12 volts or 18 volts) for each computing board connected in parallel, and thus a direct current-direct current (DC-DC) device needs to be arranged in the power supply to implement the voltage reduction, thereby causing a cost problem.

Disclosure of Invention

The embodiment of the invention provides a starting method and device of a digital currency mining machine and the digital currency mining machine.

The technical scheme of the embodiment of the invention is as follows:

a starting method of a digital currency mining machine comprises N force calculation plates which are connected in series to form a series power supply structure, wherein a positive power supply terminal of a first force calculation plate in the series power supply structure is connected with a positive terminal of a power supply, a negative power supply terminal of a last force calculation plate in the series power supply structure is connected with a negative terminal of the power supply, each force calculation plate comprises a plurality of operation chips, and N is a positive integer of at least 2; the method comprises the following steps:

sending a start signal to an ore refrigeration before turning on the power supply;

turning on the power supply;

and controlling each operation chip in the N operation boards to synchronously start the cores in a gradual mode.

In one embodiment, between the sending of the activation signal to the ore refrigeration component and the turning on of the power supply, the method further comprises: simultaneously providing a reset signal to each of the N force plates and simultaneously maintaining the reset signal for each force plate;

between turning on the power supply and synchronously turning on the cores in a progressive manner by each computational chip in the N computational boards, the method further comprises: and simultaneously releasing the reset signal for each force calculation plate.

In one embodiment, the clock signal transmission path of each of the N force computing boards has a chain-like structure; between said simultaneously releasing said reset signal for each force plate and said controlling each computational chip in said N force plates to synchronously turn on cores in a progressive manner, the method further comprises:

providing a clock signal to a first one of the compute chips in the clock signal transfer path of each of the N compute boards;

and after the clock signal passes through a preset number of arithmetic chips of each of the N arithmetic boards, the clock signal is inverted.

In one embodiment, between the sending of the activation signal to the ore refrigeration component and the turning on of the power supply, the method further comprises:

detecting a temperature of each of the N force calculation plates;

determining a maximum value of the temperatures of each of the N force plates;

when the maximum value is lower than or equal to a predetermined threshold value, the process of turning on the power supply is started.

In one embodiment, after said controlling each compute chip in the N compute boards to synchronously turn on cores in a progressive manner, the method further comprises:

detecting a voltage of each of the N force plates;

determining a force calculation plate which is a voltage adjustment object from the N force calculation plates based on the comparison result of the voltage of each force calculation plate in the N force calculation plates and a preset voltage range;

and controlling a voltage equalizing circuit in the force computing plate as the voltage adjusting object to adjust the voltage of the force computing plate as the voltage adjusting object, or controlling a voltage equalizing circuit corresponding to the force computing plate as the voltage adjusting object in a power supply to adjust the voltage of the force computing plate as the voltage adjusting object.

A starting device of a digital currency mining machine comprises N force calculation plates which are connected in series to form a series power supply structure, wherein a power supply positive terminal of a first force calculation plate in the series power supply structure is connected with a positive terminal of a power supply, a power supply negative terminal of a last force calculation plate in the series power supply structure is connected with a negative terminal of the power supply, each force calculation plate comprises a plurality of operation chips, and N is a positive integer of at least 2; the device includes:

the sending module is used for sending a starting signal to the ore machine refrigerating part before the power supply is started;

the starting module is used for starting the power supply;

and the control module is used for controlling each operation chip in the N computation boards to synchronously start the cores in a progressive mode.

In one embodiment, the sending module is further configured to simultaneously provide a reset signal to each of the N computing boards and simultaneously maintain the reset signal of each computing board between the sending of the start signal to the mineral cooling component and the turning on of the power supply; and synchronously starting the cores in a progressive mode between the starting power supply and each operation chip in the N control computation force plates, and simultaneously releasing the reset signal for each computation force plate.

In one embodiment, the clock signal transmission path of each of the N force computing boards has a chain-like structure; the device also includes:

a clock providing module, configured to provide a clock signal to a first one of the computational chips in a clock signal transmission path of each of the N computational boards; and after the clock signal passes through a preset number of arithmetic chips of each of the N arithmetic boards, the clock signal is inverted.

In one embodiment, the apparatus further comprises:

the detection module is used for detecting the temperature of each force calculation plate in the N force calculation plates; determining a maximum value of the temperatures of each of the N force plates;

wherein the power-on module performs the power-on process when the maximum value is lower than or equal to a predetermined threshold value.

In one embodiment, the control module is further configured to detect a voltage of each of the N force computing plates; determining a force calculation plate which is a voltage adjustment object from the N force calculation plates based on the comparison result of the voltage of each force calculation plate in the N force calculation plates and a preset voltage range; and controlling a voltage equalizing circuit in the force computing plate as the voltage adjusting object to adjust the voltage of the force computing plate as the voltage adjusting object, or controlling a voltage equalizing circuit corresponding to the force computing plate as the voltage adjusting object in a power supply to adjust the voltage of the force computing plate as the voltage adjusting object.

A starting apparatus for a digital currency mining machine, comprising: a memory; a processor; wherein the memory has stored therein an application executable by the processor for causing the processor to perform the method of starting a digital currency machine as claimed in any one of the preceding claims.

A digital currency mining machine comprising: the system comprises N force calculation plates, a power supply and a power supply control module, wherein the N force calculation plates are connected in series to form a series power supply structure, the positive terminal of a power supply of the first force calculation plate in the series power supply structure is connected with the positive terminal of the power supply, the negative terminal of the power supply of the last force calculation plate in the series power supply structure is connected with the negative terminal of the power supply, each force calculation plate comprises a plurality of operation chips, and N is a positive integer of at least 2; a control panel, comprising: a memory and a processor; wherein the memory has stored therein an application executable by the processor for causing the processor to execute the method of starting a digital currency mining machine as claimed in any one of the above;

each force calculation board in the N force calculation boards is in communication connection with the control board through a respective communication interface.

A computer readable storage medium having computer readable instructions stored therein for performing the method of starting a digital currency machine as claimed in any one of the preceding claims.

According to the technical scheme, the digital currency mining machine comprises the plurality of computing plates which are connected in series to form a series power supply structure, the thought that the computing plates need to adopt a parallel structure for power supply is overcome, the power supply of the computing plates is realized through the series structure, the power supply efficiency is improved, and the complexity and the cost of power supply design are reduced. In addition, before the power supply is started, the chip temperature of the computation force plate is reduced, so that the leakage difference caused by the influence of the chip leakage current on the temperature can be reduced, the voltage between chip layers in each computation force plate is further reduced, and the subsequent electrification voltage balance establishment and signal transmission are facilitated. Moreover, by controlling each operation chip to synchronously start the core in a gradual mode, the proportion of leakage current of the chip in the total current can be gradually reduced, voltage difference between boards and voltage difference between layers in the boards are gradually reduced, and voltage balance between the operation boards and interlayer voltage balance in each operation board are improved.

Drawings

Fig. 1 is a structural diagram of a power supply system of the digital money mining machine of the present invention.

Fig. 2 is an exemplary block diagram of a force computing plate of the digital currency mining machine of the present invention.

Fig. 3 is an exemplary configuration diagram of a power supply system of a digital money mining machine with a built-in voltage equalization circuit of the power supply of the present invention.

FIG. 4 is a flow chart of a method of starting the digital currency mining machine of the present invention.

FIG. 5 is an exemplary flow chart of a method of starting the digital currency mining machine of the present invention.

Fig. 6 is an exemplary block diagram of a series power supply structure including two computing boards according to the present invention.

Fig. 7 is an exemplary configuration view of a starting apparatus of the digital money mining machine of the present invention.

FIG. 8 is an exemplary block diagram of a starting apparatus having a memory-processor architecture for the digital currency mining machine of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the accompanying drawings.

For simplicity and clarity of description, the invention will be described below by describing several representative embodiments. Numerous details of the embodiments are set forth to provide an understanding of the principles of the invention. It will be apparent, however, that the invention may be practiced without these specific details. Some embodiments are not described in detail, but rather are merely provided as frameworks, in order to avoid unnecessarily obscuring aspects of the invention. Hereinafter, "including" means "including but not limited to", "according to … …" means "at least according to … …, but not limited to … … only". In view of the language convention of chinese, the following description, when it does not specifically state the number of a component, means that the component may be one or more, or may be understood as at least one.

The applicant found that: in the existing computing power board power supply structure of the digital currency mining machine, each computing power board obtains electric energy from a power supply in parallel. In such a power supply structure, as the computational power demand of the utility is higher and higher, the output current of the power supply is higher and higher, the output loss of the power supply is increased sharply, and the power supply efficiency is reduced. Moreover, since the computing boards are connected in parallel, the power supply needs to provide a lower dc voltage for each computing board, and therefore the power supply also needs to have a dc voltage reduction function, which results in a complex power supply design and brings about a cost problem.

The applicant has analyzed that the root cause of the above technical problems is: the prior art is bound to the thinking formula that the power supply of the computing board must adopt a parallel structure to ensure that each computing chip is started smoothly, and neglects the series feasibility of the power supply of the computing board under the condition that the computing chip has obtained design optimization, thereby causing the technical problems.

In the embodiment of the invention, the thought that the power supply of the computing board must adopt a parallel structure is overcome, and the power supply mode of the computing board in a series structure is adopted, so that the power supply efficiency is improved, and the complexity and the cost of the power supply design are reduced.

As can be seen from fig. 1, the force computing board 1 and the force computing board 2 … obtain electric energy from a power supply in series, wherein N is a positive integer of at least 2. Each force calculation board comprises a respective positive power supply terminal and a respective negative power supply terminal. In the series power supply structure shown in fig. 1, the power supply negative terminal of each upper stage computing force board is connected to the power supply positive terminal of the lower stage computing force board of the upper stage computing force board. And the positive terminal of the power supply of the first force computing plate in the series power supply structure is connected with the positive terminal of the power supply, and the negative terminal of the power supply of the last force computing plate in the series power supply structure is connected with the negative terminal of the power supply.

Specifically, the force calculation board 1 is connected in series with the force calculation board 2 (the force calculation board 1 is a higher-level force calculation board of the force calculation board 2), the force calculation board 2 is connected in series with the force calculation board 3 (the force calculation board 2 is a higher-level force calculation board of the force calculation board 3), and … … are sequentially connected in series with the force calculation board N. The force calculation plate 1 is the first force calculation plate in a series structure. The positive terminal of the power supply of the force calculation plate 1 is connected with the positive terminal of the power supply; the power supply negative terminal of the force calculation plate 1 is connected with the power supply positive terminal of the force calculation plate 2; the power supply negative terminal of the force calculation plate 2 is connected with the power supply positive terminal of the force calculation plate 3, and the power supply negative terminal of the force calculation plate 3 is connected with the power supply positive terminal of the lower force calculation plate of the force calculation plate 3; … …, until the negative power supply terminal of the computing force board N-1 is connected with the positive power supply terminal of the computing force board N. The force calculation board N is the last force calculation board in the series structure. The negative terminal of the power supply of the computing force plate N is connected with the negative terminal of the power supply. For example, the negative terminal of the power supply may be grounded.

In addition, each of the

force computing boards

1 and 2 … includes a respective communication interface. The communication interface of each force calculation board is respectively connected with the communication interface of the control board. The control panel is also connected with a power supply through a power supply and communication interface.

Therefore, the embodiment of the invention provides a power calculation board series power supply scheme. The power supply (corresponding to the positive power supply terminal) and the ground (corresponding to the negative power supply terminal) of each computing power board are connected end to form a multi-stage series voltage domain. Assuming that the voltage of each computation force plate is V1, the power supply voltage provided by the power supply to the N computation force plates is V1N. In order to improve the computing power, the number of the computing power plates connected in series is increased, and the output voltage of the power supply is increased. Since the currents in the series circuit are the same, the current drop loss of the power supply remains constant all the time. Furthermore, when the output voltage of the power supply is increased, the power supply loss can be lower and the power supply efficiency can be gradually increased due to the reduction of the voltage difference between the input and the output of the power supply.

After the force computing boards are connected in series, because the computing chips of the force computing boards may have inconsistency and the voltage division may be uneven at the moment of power-on, a voltage equalization circuit is preferably arranged in each force computing board to control the voltage of the force computing board within a reasonable voltage range. The voltage equalization circuit is arranged between the power supply positive terminal and the power supply negative terminal in the force calculation board and is adapted to equalize the voltage difference between the force calculation boards.

Alternatively, the voltage equalization circuit may be arranged in the power supply. Specifically, the power supply includes: the (N-1) voltage equalization circuits correspond to the (N-1) force calculation plates except the first force calculation plate in the N force calculation plates one by one; each voltage equalization circuit comprises a positive terminal and a negative terminal, the positive terminal is connected to the positive power supply terminal of the corresponding force calculation plate, and the negative terminal is connected to the negative power supply terminal of the corresponding force calculation plate.

For example, a voltage equalization circuit disposed in a power supply or computing board may be implemented as a combined circuit including a buck conversion (buck) circuit and a boost conversion (boost) circuit. When the voltage of the force calculating plate is too high, the current is drained through a boost circuit to reduce the voltage and raise the voltage of other force calculating plates; when the voltage of the computation board is too low, the buck circuit supplements current to improve the voltage and reduce the voltage of other computation boards.

Furthermore, it is preferred to arrange an isolation circuit for isolating the communication signals in each computing board, considering that the communication signals of each computing board will be at different potentials (voltage domains) and the communication interfaces of the respective computing boards are connected to the same control board.

Alternatively, the isolation circuit may be disposed in the control board. Specifically, the control panel includes: a controller; n isolation circuits corresponding to the N force calculation boards one by one; wherein each isolation circuit comprises a first end and a second end, the first end is adapted to be connected with a communication interface in the computing board corresponding to the isolation circuit, and the second end is adapted to be connected with the controller. Preferably, the controller may be implemented as: a System On Chip (SOC) Chip; a Field Programmable Gate Array (FPGA); the SOC chip and the FPGA are combined together; a CPU; a Microprocessor (MCU); a common combination of a CPU and MCU, etc.

For example, the isolation circuitry disposed in the control board or force computing board may be implemented as a dedicated isolation chip; an opto-coupler isolation circuit; a transformer isolation circuit; an isolation capacitor; an ethernet interface including a transformer, etc.

Based on the above description, the embodiment of the invention also provides a force calculation plate of the digital currency mining machine. The force calculation board is adapted to the series power supply scheme of the force calculation board shown in fig. 1. This calculation power board includes: a substrate; the power supply positive terminal and the power supply negative terminal are respectively arranged on the substrate and are adapted to be connected with the other force calculation plate in series; a communication interface mounted on the substrate; and the plurality of operation chips are arranged on the substrate, wherein the signal transmission paths of the plurality of operation chips have a chain structure.

In one embodiment, the force computation sheet further comprises: and the isolation circuit is arranged on the substrate and comprises a first end and a second end, wherein the first end is adapted to be connected with the communication interface, and the second end is adapted to be connected with an operation chip which is used as a signal receiving starting point of the force computation board in the chain structure.

In one embodiment, a Power supply includes a Power Factor Correction (PFC) circuit; wherein the sum of the voltages of the N force calculation plates is equal to the output voltage of the PFC circuit.

Therefore, after the force calculation board series connection scheme of the embodiment of the invention is adopted, the sum of the voltages of the force calculation boards reaches the PFC voltage by increasing the series connection number of the force calculation boards, the DC-DC conversion in a power supply can be omitted, the power supply efficiency is further improved, and the cost is obviously reduced.

For example, assuming that the PFC voltage provided by the power supply is 400 volts (V), the 400V PFC voltage can be used to supply power to 33 series 12V computing boards or 22 series 18V computing boards, thereby omitting a DC-DC conversion device of the power supply.

The above exemplary description describes the number of force plates in series and the voltage value of each force plate, and those skilled in the art will appreciate that this description is merely exemplary and is not intended to limit the scope of the embodiments of the present invention.

Fig. 2 is an exemplary block diagram of a force computing plate of the digital currency mining machine of the present invention. In fig. 2, the computing force plate includes a substrate, and mounted on the substrate:

(1) the power supply positive terminal;

(2) a power supply negative terminal;

(3) a communication interface;

(4) the device comprises an operation chip 1, an operation chip 2 and an operation chip 3 … … operation chip m, wherein m is a positive integer of at least 2;

(5) an isolation circuit;

(6) and a voltage equalization circuit.

The positive power terminal and the negative power terminal are adapted to be connected in series with another computing force board. Such as:

(a) and when the force calculation plate is the first force calculation plate in the series structure, the positive terminal of the power supply is connected with the positive terminal of the power supply, and the negative terminal of the power supply is connected with the positive terminal of the power supply of the lower force calculation plate.

(b) And when the force calculation plate is the last force calculation plate in the series structure, the positive terminal of the power supply is connected with the negative terminal of the power supply of the superior force calculation plate, and the negative terminal of the power supply is connected with the negative terminal of the power supply.

(c) And when the force calculation plate is a middle force calculation plate (neither the first force calculation plate nor the last force calculation plate) in the series structure, the positive power terminal is connected with the negative power terminal of the superior force calculation plate, and the negative power terminal is connected with the positive power terminal of the inferior force calculation plate.

The core voltage power supply of the operation chip m of the

operation chips

1, 2 and 3 … … adopts a series power supply mode, wherein the positive power supply and the negative power supply (ground) of each operation chip are connected end to form a multistage series voltage domain, and each voltage domain is provided with one or more operation chips.

In FIG. 2, an operation chip m and an operation chip m-1 form a voltage domain, wherein the operation chip m and the operation chip m-1 are commonly connected to a positive power terminal; the operation chip m-2 and the operation chip m-3 form a voltage domain, the operation chip m-2 is connected with the operation chip m-1 in series, and the operation chip m-3 is connected with the operation chip m in series; the operation chip m-4 and the operation chip m-5 form a voltage domain, the operation chip m-4 is connected with the operation chip m-3 in series, and the operation chip m-5 is connected with the operation chip m-2 in series; … … the operation chip 7 and the operation chip 8 form a voltage domain; the operation chip 6 and the operation chip 5 form a voltage domain, the operation chip 6 is connected with the operation chip 7 in series, and the operation chip 5 is connected with the operation chip 8 in series; the operation chip 3 and the operation chip 4 form a voltage domain, the operation chip 3 is connected with the operation chip 6 in series, and the operation chip 4 is connected with the operation chip 5 in series; the operation chip 2 and the operation chip 1 form a voltage domain, the operation chip 2 is connected with the operation chip 3 in series, the operation chip 1 is connected with the operation chip 4 in series, and the operation chip 2 and the operation chip 1 are connected with a power supply negative terminal together. It can be seen that the voltage domains are connected in series (as shown by the solid lines).

Moreover, the communication interface can receive communication signals from outside the computing power board (such as the control board) and can also send communication signals to outside the computing power board (such as the control board). The signal transmission paths of the

arithmetic chips

1, 2, and 3 … … have a chain-like structure (shown by a broken line).

When the communication interface receives the communication signal from the control panel, the signal transmission path is as follows: the operation chip 1 (signal receiving start point in the operation chip) → the operation chip 2 → the operation chip 3 → the operation chip 4 → the operation chip 5 → the operation chip 6 → the operation chip 7 → the operation chip 8 → … … the operation chip m-5 → the operation chip m-4 → the operation chip m-3 → the operation chip m-2 → the operation chip m-1 → the operation chip m.

When sending communication signals to the control panel through the communication interface, the signal transmission path is: the arithmetic chip m → the arithmetic chip m-1 → the arithmetic chip m-2 → the arithmetic chip m-3 → the arithmetic chip m-4 → the arithmetic chip m-5 … …, the arithmetic chip 8 → the arithmetic chip 7 → the arithmetic chip 6 → the arithmetic chip 5 → the arithmetic chip 4 → the arithmetic chip 3 → the arithmetic chip 2 → the arithmetic chip 1 (signal transmission destination in the arithmetic chip).

It is preferred to arrange an isolation circuit in each force computing board, considering that the communication signals of each force computing board will be at different potentials (voltage domains) and connected to the same control board. The isolation circuit includes a first end and a second end, the first end is connected to the communication interface, and the second end is connected to an operation chip (such as an operation chip 1 shown in fig. 2) in the chain structure, which is used as a signal receiving starting point of the force computation board.

After a plurality of force computing boards shown in fig. 2 are connected in series, since the force computing board chips may have inconsistency and may have uneven voltage division at the moment of power-on, a voltage equalization circuit is arranged in each force computing board to control the voltage of the force computing board within a reasonable voltage range. In fig. 2, a voltage equalization circuit is arranged between the positive power supply terminal and the negative power supply terminal, adapted to equalize the voltage difference between the force plates. The voltage equalization circuit comprises a buck circuit and a boost circuit. When the voltage of the force calculation plate is too high, the current is drained through a boost circuit to reduce the voltage; when the voltage of the force plate is too low, the buck circuit supplements current to increase the voltage. Preferably, the substrate may be implemented as an aluminum substrate.

Based on the above description, the embodiment of the invention also provides a starting method of the digital currency mining machine. The start-up method is applicable to a digital currency mining machine that includes N force plates connected in series in a series power configuration. Wherein: the positive terminal of a power supply of a first force calculation plate in the series power supply structure is connected with the positive terminal of the power supply, and the negative terminal of the power supply of a last force calculation plate in the series power supply structure is connected with the negative terminal of the power supply; each computation board comprises a plurality of computation chips, wherein N is a positive integer of at least 2. Preferably, each force computation board has the same circuit structure.

As can be seen from fig. 3, the power supply comprises: (N-1) voltage equalizing circuits; each voltage equalization circuit corresponds to (N-1) force calculation plates except the first force calculation plate in the N force calculation plates which are connected in series one by one; each voltage equalization circuit comprises a positive terminal and a negative terminal, the positive terminal is connected to the positive power supply terminal of the corresponding force calculation plate, and the negative terminal is connected to the negative power supply terminal of the corresponding force calculation plate.

As shown in fig. 4, the method includes:

step 401: sending a start signal to the mine refrigeration member prior to turning on the power supply.

Here, upon determining that the ore machine has a start-up requirement and that the power source of the ore machine has not been turned on, a start-up signal is sent to the ore refrigeration to start the ore refrigeration so that the ore refrigeration begins to cool down each computing plate in the series power configuration prior to the power source being turned on. Optionally, the mine cooling member is further controlled to output a maximum cooling power.

The ore refrigeration piece can be used to cool the ore. For example, the mine refrigeration component may be embodied as an air-cooled component (e.g., a fan) or a water-cooled component (e.g., a water-cooled panel), among others. While typical examples of mineral refrigeration units have been described above, those skilled in the art will appreciate that this description is by way of example only, and is not intended to limit the scope of embodiments of the present invention.

By reducing the chip temperature of each computation board, the leakage difference caused by the influence of the temperature on the chip leakage current in each computation board can be reduced, and further the voltage between chip layers in each computation board is reduced, thereby being beneficial to the subsequent establishment of the electrified voltage balance and the signal transmission.

For example, when the mining machine determines that the mining machine has a start-up requirement upon receipt of a restart command, a start-up signal may be sent to the mining machine refrigeration to lower the chip temperature of each computing plate before the mining machine is shut down to restart. Optionally, the power-on time may be delayed to ensure that the chip temperature of each computing board is adequately dissipated.

For another example, when the mining machine determines that the mining machine has a start demand upon receipt of a start command, a start signal may be sent to the mining machine refrigeration to lower the chip temperature of each computing plate before the mining machine is started. Optionally, the power-on time may be delayed to ensure that the chip temperature of each computing board is adequately dissipated.

Step 402: and turning on the power supply.

Here, the specific operation of turning on the power supply includes: and sending a starting instruction to the power supply so as to start the power supply of the mining machine. After the power supply is started, the power connection between the power supply and the series power supply structure is established, and each force calculation board in the N force calculation boards is electrified.

In one embodiment, the temperature of each force computing plate may be periodically detected using a temperature sensor disposed on each of the N force computing plates; determining the maximum value of the temperatures of the N force calculation plates; starting to execute a process of turning on the power supply when the maximum value is lower than or equal to a predetermined threshold value; when the maximum value is higher than the predetermined threshold value, the process of turning on the power supply is temporarily not performed, and the next detection value of each temperature sensor is waited for to be judged again.

Step 403: and controlling each operation chip in the N operation boards to synchronously start a core (core) in a gradual mode.

Considering that there are generally a plurality of cores (for example, hundreds) inside the operation chip, when each core is turned on, a small amount of operating current is added, so as to pull down the voltage of the current layer, therefore, after the power supply is powered on for the series power supply structure, all the operation chips in all the N operation boards are powered on at the same time, and at this time, each operation chip can be controlled to turn on the cores synchronously and gradually. When the cores are synchronously and gradually started, the proportion of the leakage current of each operation chip in the total current of the operation board where the operation chip is located is gradually reduced, so that the voltage difference between layers in the operation board is gradually reduced, the voltage balance of the operation board and the voltage balance between the operation boards gradually tend to be stable, and finally the voltage balance is established.

For example, each operation chip synchronously starting the cores in a progressive manner includes: each arithmetic chip in the N arithmetic boards simultaneously starts a preset number of cores, wherein the preset number accounts for the total number of cores of the arithmetic chips, and the preset number is selected to be small enough, for example, one core is started at a time.

For example, assume that there are N computation boards, each computation board has M computation chip sets (i.e., layers), each computation chip set has K computation chips, each computation chip has 100 cores, which are core 1 to core 100, respectively. Then, at the first timing, the respective cores 1 in each of the N computation chips (i.e., all of the N × M × K computation chips) are controlled to be turned on (the cores 2 to 100 are temporarily not turned on). And controlling the core 2 in each operation chip in the N operation boards to be started (the cores 3 to 100 are not started temporarily) at a second time sequence. Similar processing is carried out until the core 100 in each operation chip in the N operation boards is controlled to be started at the 100 th timing.

Therefore, the proportion of the leakage current of the chip in the total current can be gradually reduced by controlling each operation chip to synchronously start the core in a gradual mode, so that the voltage difference between layers is gradually reduced, and the voltage balance between the operation boards in the operation board is finally established.

In one embodiment, between sending an activation signal to the mine refrigeration member in step 401 and turning on the power supply in step 402, the method further comprises: simultaneously providing a reset signal to each of the N force plates and simultaneously maintaining the reset signal for each force plate. For example, the control board may send a Reset signal to the Reset pin of each computing board and hold the Reset signal of each computing board; between turning on the power supply in step 402 and controlling each compute chip in the N compute boards to turn on the cores synchronously in a gradual manner in step 403, the method further includes: and simultaneously releasing the reset signal for each force calculation plate. For example, the control board releases a Reset signal to the Reset pin of each force board.

In one embodiment, after controlling each of the N computational chips to synchronously turn on the cores in a progressive manner in step 403, the method further includes: detecting the voltage of each force calculation plate in the N force calculation plates; determining a force calculation plate which is a voltage adjustment object from the N force calculation plates based on the comparison result of the voltage of each of the N force calculation plates and a preset voltage range; the voltage equalization circuit in the force computing plate as the voltage adjustment object is controlled to adjust the voltage of the force computing plate as the voltage adjustment object, or the voltage equalization circuit corresponding to the force computing plate as the voltage adjustment object in the power supply is controlled to adjust the voltage of the force computing plate as the voltage adjustment object. Here, when the voltage of a certain force calculation plate exceeds an upper limit value of a predetermined voltage range or is lower than a lower limit value of the predetermined voltage range, the force calculation plate may be determined as a voltage adjustment target. Specifically, the method comprises the following steps: when the voltage of a certain force computing board is found to be too high, the current is drained through a boost circuit to reduce the voltage of the force computing board and raise the voltages of other force computing boards; when the voltage of a certain computation plate is too low, the buck circuit supplements current to improve the voltage of the computation plate and reduce the voltages of other computation plates.

The applicant has also found that: the pull-up driving capability and the pull-down driving capability of the operation chip are different, and a certain time delay is needed when the clock signal passes through the operation chip, so that the duty ratio of the upper pulse width or the lower pulse width of the clock signal is gradually increased after the clock signal passes through a plurality of chips, and the clock signal of the operation chip which goes backwards is worse aiming at the chain structure in the operation board.

In one embodiment, the clock signal transfer path of each of the N force computing boards has a chain-like structure; between releasing the reset signal and controlling each compute chip in the N compute boards to synchronously turn on the cores in a progressive manner, the method further comprises: providing a clock signal to a first one of the compute chips in a clock signal transfer path of each of the N compute boards; and after the clock signal passes through a preset number of arithmetic chips in each of the N arithmetic boards, the clock signal is inverted. The predetermined number may be an accurate value obtained through theoretical calculation, or an empirical value set manually.

More specifically, the meaning of flipping the clock signal is: the high and low levels of the clock signal are toggled. The method specifically comprises the following steps: the high level of the clock signal is changed to the low level, and the low level of the clock signal is changed to the high level. Compared with the clock signal before the inversion, the upper pulse width ratio and the lower pulse width ratio of the inverted clock signal are replaced with each other. For example, the upper pulse width ratio of the clock signal before the inversion is M%, and the lower pulse width ratio is N%; and the proportion of the upper pulse width of the inverted clock signal is N%, the proportion of the lower pulse width of the inverted clock signal is M%, wherein M + N is 100, and M and N are positive numbers.

For example, assume that the predetermined number is 10; every time the clock signal passes through one operation chip, the pulse width ratio (the proportion of the upper pulse width length to the total pulse width length) of the clock signal is increased by 1%; the upper pulse width ratio of the clock signal supplied to the first operation chip is 50% (correspondingly, the lower pulse width ratio is 50%). Then, after the clock signal passes through the first computing chip, the upper pulse width ratio of the clock signal is increased to 51% (correspondingly, the lower pulse width ratio is decreased to 49%), after the clock signal passes through the second computing chip, the upper pulse width ratio of the clock signal is increased to 52% (correspondingly, the lower pulse width ratio is decreased to 48%), and so on, after the clock signal passes through the tenth computing chip, the upper pulse width ratio of the clock signal is increased to 60% (correspondingly, the lower pulse width ratio is decreased to 40%). Before being input to the eleventh operation chip, the high level of the clock signal is changed to the low level and the low level is changed to the high level, thereby realizing inversion of the clock signal. The upper pulse width fraction of the inverted clock signal is 40% (correspondingly, the lower pulse width fraction is 60%). The inverted clock signal obviously reduces the upper pulse width ratio, and the upper pulse width ratio can be gradually recovered after the clock signal passes through a subsequent operation chip. Therefore, the embodiment of the invention can regularly adjust the clock signal of each computation board, and avoids the defect that the clock signal of the computation chip is worse later.

As can be seen, in the embodiment of the present invention, the clock initialization is performed from the first arithmetic chip to which the clock signal is connected, and the clock signal is inverted every predetermined number of arithmetic chips. This is because: after every certain number of operation chips, the upper pulse width or the lower pulse width of the clock signal is gradually increased, and the clock signal is inverted once at this time, so that the ratio of the upper pulse width and the lower pulse width of the clock signal can be replaced once, and on the basis, the problem of the clock signal cannot be caused by the continuous change of the pulse width of the following clock signal.

Based on the above description, the following describes exemplary embodiments of the present invention.

FIG. 5 is an exemplary flow chart of a method of starting the digital currency mining machine of the present invention. The method is applicable to a digital currency mining machine comprising N force plates connected in series in a series power supply configuration. The power supply positive terminal of the first force computing plate in the series power supply structure is connected with the positive terminal of a power supply, the power supply negative terminal of the last force computing plate in the series power supply structure is connected with the negative terminal of the power supply, each force computing plate comprises a plurality of operation chips, and N is a positive integer of at least 2.

For example, fig. 6 is an exemplary block diagram of a series power supply structure including two computing boards according to the present invention.

As can be seen from fig. 6, the force computing board 1 and the force computing board 2 have the same circuit structure, and the force computing board 1 and the force computing board 2 are connected in series with each other. Wherein, the power negative terminal of the computing power board 1 is connected with the power positive terminal of the computing power board 2. The positive terminal of the power supply of the computing force plate 1 can be connected with the positive terminal of the power supply or connected with the negative terminal of the power supply of the primary computing force plate. The power supply negative terminal of the computing force plate 2 can be connected with the negative terminal of the power supply or the power supply positive terminal of the next-stage computing force plate.

In the force calculation board 1: the operation chip m and the operation chip m-1 form a voltage domain, wherein the operation chip m and the operation chip m-1 are connected with the power supply positive terminal of the force calculation plate 1 together; the operation chip m-2 and the operation chip m-3 form a voltage domain, the operation chip m-2 is connected with the operation chip m-1 in series, and the operation chip m-3 is connected with the operation chip m in series; the operation chip m-4 and the operation chip m-5 form a voltage domain, the operation chip m-4 is connected with the operation chip m-3 in series, and the operation chip m-5 is connected with the operation chip m-2 in series; … … the operation chip 7 and the operation chip 8 form a voltage domain; the operation chip 6 and the operation chip 5 form a voltage domain, the operation chip 6 is connected with the operation chip 7 in series, and the operation chip 5 is connected with the operation chip 8 in series; the operation chip 3 and the operation chip 4 form a voltage domain, the operation chip 3 is connected with the operation chip 6 in series, and the operation chip 4 is connected with the operation chip 5 in series; the operation chip 2 and the operation chip 1 form a voltage domain, the operation chip 2 is connected with the operation chip 3 in series, the operation chip 1 is connected with the operation chip 4 in series, and the operation chip 2 and the operation chip 1 are connected with the power supply negative terminal of the operation board 1 together. It can be seen that the voltage domains within the force plate 1 are connected in series (as shown by the solid lines). Moreover, the communication interface in the computing power board 1 can receive communication signals from the outside of the computing power board 1 (for example, a control board) and can also send communication signals to the outside of the computing power board 1 (for example, the control board). The signal transmission paths of the

computation chips

1, 2, and 3 … … in the computation board 1 have a chain-like structure (shown by a broken line). When the communication interface in the force computing board 1 receives a communication signal from the control board, the signal transmission path in the force computing board 1 is as follows: the operation chip 1 (signal receiving start point in the operation chip) → the operation chip 2 → the operation chip 3 → the operation chip 4 → the operation chip 5 → the operation chip 6 → the operation chip 7 → the operation chip 8 → … … the operation chip m-5 → the operation chip m-4 → the operation chip m-3 → the operation chip m-2 → the operation chip m-1 → the operation chip m. When the force calculation board 1 sends a communication signal to the control board through the communication interface, the signal transmission path is as follows: the arithmetic chip m → the arithmetic chip m-1 → the arithmetic chip m-2 → the arithmetic chip m-3 → the arithmetic chip m-4 → the arithmetic chip m-5 … …, the arithmetic chip 8 → the arithmetic chip 7 → the arithmetic chip 6 → the arithmetic chip 5 → the arithmetic chip 4 → the arithmetic chip 3 → the arithmetic chip 2 → the arithmetic chip 1 (signal transmission destination in the arithmetic chip).

In the force calculation board 2: the operation chip m and the operation chip m-1 form a voltage domain, wherein the operation chip m and the operation chip m-1 are connected with the power supply positive terminal of the force calculation board 2 together; the operation chip m-2 and the operation chip m-3 form a voltage domain, the operation chip m-2 is connected with the operation chip m-1 in series, and the operation chip m-3 is connected with the operation chip m in series; the operation chip m-4 and the operation chip m-5 form a voltage domain, the operation chip m-4 is connected with the operation chip m-3 in series, and the operation chip m-5 is connected with the operation chip m-2 in series; … … the operation chip 7 and the operation chip 8 form a voltage domain; the operation chip 6 and the operation chip 5 form a voltage domain, the operation chip 6 is connected with the operation chip 7 in series, and the operation chip 5 is connected with the operation chip 8 in series; the operation chip 3 and the operation chip 4 form a voltage domain, the operation chip 3 is connected with the operation chip 6 in series, and the operation chip 4 is connected with the operation chip 5 in series; the operation chip 2 and the operation chip 1 form a voltage domain, the operation chip 2 is connected with the operation chip 3 in series, the operation chip 1 is connected with the operation chip 4 in series, and the operation chip 2 and the operation chip 1 are connected with the power supply negative terminal of the operation board 2 together. It can be seen that the voltage domains within the force plate 2 are connected in series (as shown by the solid lines). Moreover, the communication interface in the computing power board 2 can receive communication signals from the outside of the computing power board 2 (for example, the control board) and can also send communication signals to the outside of the computing power board 2 (for example, the control board). The signal transmission paths of the computation chip 1, the computation chip 2, and the computation chip 3 … … in the computation board 2 have a chain-like structure (shown by a dotted line). When the communication interface in the force computing board 2 receives the communication signal from the control board, the signal transmission path in the force computing board 2 is: the operation chip 1 (signal receiving start point in the operation chip) → the operation chip 2 → the operation chip 3 → the operation chip 4 → the operation chip 5 → the operation chip 6 → the operation chip 7 → the operation chip 8 → … … the operation chip m-5 → the operation chip m-4 → the operation chip m-3 → the operation chip m-2 → the operation chip m-1 → the operation chip m. When the force calculation board 2 sends a communication signal to the control board through the communication interface, the signal transmission path is as follows: the arithmetic chip m → the arithmetic chip m-1 → the arithmetic chip m-2 → the arithmetic chip m-3 → the arithmetic chip m-4 → the arithmetic chip m-5 … …, the arithmetic chip 8 → the arithmetic chip 7 → the arithmetic chip 6 → the arithmetic chip 5 → the arithmetic chip 4 → the arithmetic chip 3 → the arithmetic chip 2 → the arithmetic chip 1 (signal transmission destination in the arithmetic chip).

As shown in fig. 5, the method for starting the series power supply structure shown in fig. 6 includes:

step 501: sending a start signal to the mine refrigeration member prior to turning on the power supply.

Here, when it is determined that the ore machine has a start-up requirement and the power source of the ore machine has not been turned on, a start-up signal is sent to the ore cooling member to start the ore cooling member and control the ore cooling member to output a maximum cooling power such that the ore cooling member cools force plate 1 and force plate 2 separately before the power source of the ore machine is turned on.

Step 502: simultaneously sends reset signals to the force computing board 1 and the force computing board 2, and simultaneously maintains the reset signals.

Here, the Reset signals are respectively sent to the Reset pins of the

force computing boards

1 and 2, and are simultaneously held.

Step 503: and starting a power supply of the mining machine.

Here, a power-on command is sent to the power supply, thereby turning on the power supply. After the power supply is started, the power connection between the power supply and the series power supply structure is established, and the force calculating board 1 and the force calculating board 2 are respectively electrified.

Step 504: while releasing the reset signal.

Here, the Reset signals of the respective Reset pins of the force computing board 1 and the force computing board 2 are simultaneously released.

Step 505: the computing power board 1 and the computing power board 2 are supplied with clock signals, respectively.

The clock signal transmission path of the computation force board 1 shown in fig. 6 has a chain-like structure.

For example, a crystal oscillator (e.g., a 24M crystal oscillator) is disposed in the force computing board 1 and adjacent to the force computing chip 1. The transmission path of the clock signal generated by the crystal oscillator in the force computing board 1 is as follows: the operation chip 1 → the operation chip 2 → the operation chip 3 → the operation chip 4 → the operation chip 5 → the operation chip 6 … …, the operation chip m-5 → the operation chip m-4 → the operation chip m-3 → the operation chip m-2 → the operation chip m-1 → the operation chip m. Here, the crystal oscillator supplies a clock signal to the first arithmetic chip (arithmetic chip 1) in the clock signal transfer path. The clock signal is transmitted between the arithmetic chips of the force plate 1 along the clock signal transmission path, and the clock signal is inverted after a predetermined number of the arithmetic chips. For example, assuming that the predetermined number is 3, the clock signal sequentially passes through the arithmetic chip 1 → the arithmetic chip 2 → the arithmetic chip 3, and then the clock signal output from the arithmetic chip 3 to the arithmetic chip 4 is inverted. Then, the inverted clock signal passes through the arithmetic chip 4 → the arithmetic chip 5 → the arithmetic chip 6 in this order, and the clock signal output from the arithmetic chip 6 to the arithmetic chip 7 is inverted again. In the clock signal transmission path within the force board 1, the inversion of the clock signal is realized on the basis of a similar manner.

The above exemplary description is made by taking the case where the crystal oscillator is disposed adjacent to the operation chip 1, and in fact, the crystal oscillator may be disposed at a position adjacent to the operation chip M. At this time, the transmission path of the clock signal generated by the crystal oscillator in the force computing board 1 is: the operation chip m → the operation chip m-1 → the operation chip m-2 → the operation chip m-3 → the operation chip m-4 → the operation chip m-5 … … the operation chip 8 → the operation chip 7 → the operation chip 6 → the operation chip 5 → the operation chip 4 → the operation chip 3 → the operation chip 2 → the operation chip 1. Similarly, the crystal oscillator supplies a clock signal to the first arithmetic chip (arithmetic chip m) in the clock signal transfer path. The clock signal is transmitted between the arithmetic chips of the force plate 1 along the clock signal transmission path, and the clock signal is inverted after a predetermined number of the arithmetic chips. For example, assuming that the predetermined number is 3, the clock signal sequentially passes through the operation chip m → the operation chip m-1 → the operation chip m-2, and then the clock signal output from the operation chip m-2 to the operation chip m-3 is inverted. Then, the inverted clock signal passes through the operation chip m-3 → the operation chip m-4 → the operation chip m-5 in sequence, and the clock signal output to the operation chip m-6 by the operation chip m-5 is inverted again. In the clock signal transmission path within the force board 1, the inversion of the clock signal is realized on the basis of a similar manner.

Also, the number of crystal oscillators in the force plate 1 may be plural. Accordingly, there are multiple clock signals within the force board 1. Each clock signal has a respective transmission path within the force computation board 1; each transmission path has a respective chain-like structure. Each clock signal is transmitted among the operation chips along the respective clock signal transmission path, and the clock signals are respectively inverted after passing through a predetermined number of operation chips.

Similarly, the clock signal transmission path of the computation board 2 shown in fig. 6 has a chain-like structure.

For example, a crystal oscillator (e.g., a 24M crystal oscillator) is disposed in the force computing board 2 adjacent to the computing chip 1. The transmission path of the clock signal generated by the crystal oscillator in the force computing board 1 is as follows: the operation chip 1 → the operation chip 2 → the operation chip 3 → the operation chip 4 → the operation chip 5 → the operation chip 6 … …, the operation chip m-5 → the operation chip m-4 → the operation chip m-3 → the operation chip m-2 → the operation chip m-1 → the operation chip m. Here, the crystal oscillator supplies a clock signal to the first arithmetic chip (arithmetic chip 1) in the clock signal transfer path. The clock signal is transmitted between the arithmetic chips of the force plate 1 along the clock signal transmission path, and the clock signal is inverted after a predetermined number of the arithmetic chips. For example, assuming that the predetermined number is 4, the clock signal sequentially passes through the operation chip 1 → the operation chip 2 → the operation chip 3 → the operation chip 4, and then the clock signal output from the operation chip 4 to the operation chip 5 is inverted. Then, the inverted clock signal passes through the arithmetic chip 5 → the arithmetic chip 6 → the arithmetic chip 7 → the arithmetic chip 8 in this order, and the clock signal output from the arithmetic chip 8 to the arithmetic chip 9 is inverted again. In the clock signal transfer path within the force plate 2, the inversion of the clock signal is realized on the basis of a similar manner.

The above exemplary description is made by taking the case where the crystal oscillator is disposed adjacent to the operation chip 1, and in fact, the crystal oscillator may be disposed at a position adjacent to the operation chip M. At this time, the transmission path of the clock signal generated by the crystal oscillator in the force computing board 2 is: the operation chip m → the operation chip m-1 → the operation chip m-2 → the operation chip m-3 → the operation chip m-4 → the operation chip m-5 … … the operation chip 8 → the operation chip 7 → the operation chip 6 → the operation chip 5 → the operation chip 4 → the operation chip 3 → the operation chip 2 → the operation chip 1. Similarly, the crystal oscillator supplies a clock signal to the first arithmetic chip (arithmetic chip m) in the clock signal transfer path. The clock signal is transmitted between the arithmetic chips of the force plate 1 along the clock signal transmission path, and the clock signal is inverted after a predetermined number of the arithmetic chips. For example, assuming that the predetermined number is 4, the clock signal outputted from the operation chip m-3 to the operation chip m-4 is inverted after the clock signal sequentially passes through the operation chip m → the operation chip m-1 → the operation chip m-2 → the operation chip m-3. Then, the inverted clock signal passes through the operation chip m-4 → the operation chip m-5 → the operation chip m-6 → the operation chip m-7 in sequence, and the clock signal output to the operation chip m-8 by the operation chip m-7 is inverted again. In the clock signal transfer path within the force plate 2, the inversion of the clock signal is realized on the basis of a similar manner.

Also, the number of crystal oscillators in the force plate 2 may be plural. Accordingly, there are multiple clock signals within the force plate 2. Each clock signal has a respective transmission path within the force computation board 2; each transmission path has a respective chain-like structure. Each clock signal is transmitted among the operation chips along the respective clock signal transmission path, and the clock signals are respectively inverted after passing through a predetermined number of operation chips.

The start-up procedure of the present invention is described above in a series power supply structure including two computing boards, and those skilled in the art will appreciate that this description is merely exemplary and is not intended to limit the scope of the embodiments of the present invention. For example, the number of force plates in the series power supply structure can be a positive integer greater than 2.

While the embodiments of the present invention have been described with reference to the predetermined number of force calculating plates 1 being 3 and the predetermined number of force calculating plates 2 being 4, those skilled in the art will appreciate that such descriptions are merely exemplary and are not intended to limit the scope of the embodiments of the present invention. For example, the predetermined number in the force computing plate 1 and the predetermined number in the force computing plate 2 may be the same value.

Step 506: the operation chip gradually starts the core.

Here, each compute chip in the control force board 1 and the force board 2 synchronously and progressively turns on the core. For example, each compute chip is assumed to have 100 cores, core 1 to core 100. Then, at the first timing, all the arithmetic chips in the force computing board 1 and all the arithmetic chips in the force computing board 2 are controlled to turn on the respective cores 1 (at this time, the cores 2 to 100 are not turned on temporarily). At the second timing, all the arithmetic chips in the arithmetic board 1 and all the arithmetic chips in the arithmetic board 2 are controlled to turn on the respective cores 2 (at this time, the cores 3 to 100 are not turned on temporarily). Similar processing is carried out until all the arithmetic chips in the control arithmetic board 1 and all the arithmetic chips in the arithmetic board 2 respectively turn on the respective cores 100 at the 100 th timing, and all the cores are turned on so far.

Based on the above description, the embodiment of the invention also provides a starting device of the digital currency mining machine.

Fig. 7 is an exemplary configuration view of a starting apparatus of the digital money mining machine of the present invention. The digital currency mining machine comprises N computing force plates which are connected in series to form a series power supply structure, wherein a power supply positive terminal of a first computing force plate in the series power supply structure is connected with a positive terminal of a power supply, a power supply negative terminal of a last computing force plate in the series power supply structure is connected with a negative terminal of the power supply, each computing force plate comprises a plurality of computing chips, and N is a positive integer of at least 2. As shown in fig. 7, the apparatus includes:

a sending module 701, configured to send a start signal to an ore machine refrigeration unit before a power supply is turned on;

a power-on module 702 for powering on a power supply;

and the control module 703 is configured to control each computational chip in the N computational boards to synchronously turn on the cores in a gradual manner.

In one embodiment, the sending module 701 is further configured to simultaneously provide a reset signal to each computing force plate of the N computing force plates and simultaneously maintain the reset signal of each computing force plate between sending a start signal to the ore cooling component and turning on the power supply; and between the power supply is started and each operation chip in the N operation boards is controlled to synchronously start the cores in a progressive mode, and the reset signal is released for each operation board simultaneously. The sending module 701 may be implemented as an integral module to collectively implement the functions of sending the start signal, providing the reset signal, holding the reset signal, and releasing the reset signal. Furthermore, the sending module 701 may also be implemented as a logic module comprising a plurality of sub-modules, wherein each sub-module corresponds to the functions of sending the start signal, providing the reset signal, holding the reset signal, and releasing the reset signal, respectively.

In one embodiment, the clock signal transfer path of each of the N force computing boards has a chain-like structure; the device also includes: a clock providing module 704, configured to provide a clock signal to a first one of the computational chips in the clock signal transmission path of each of the N computational boards; and when the clock signal passes through a preset number of arithmetic chips, the clock signal is inverted.

In one embodiment, the apparatus further comprises: a detection module 705, configured to detect a temperature of each force calculation plate of the N force calculation plates; determining a maximum value of the temperatures of each of the N force plates; wherein the power-on module 702 performs the process of turning on the power when the maximum value is lower than or equal to a predetermined threshold value.

In one embodiment, the control module 703 is further configured to detect a voltage of each of the N force plates; determining a force calculation plate which is a voltage adjustment object from the N force calculation plates based on the comparison result of the voltage of each of the N force calculation plates and a preset voltage range; the voltage equalization circuit in the force computing plate as the voltage adjustment object is controlled to adjust the voltage of the force computing plate as the voltage adjustment object, or the voltage equalization circuit corresponding to the force computing plate as the voltage adjustment object in the power supply is controlled to adjust the voltage of the force computing plate as the voltage adjustment object.

As shown in fig. 8, the starting apparatus of the digital money mining machine includes:

a processor 801; a memory 802; in which the memory 802 has stored therein an application program executable by the processor 801 for causing the processor 801 to execute the method of starting a digital money mining machine as claimed in any one of the above.

The memory 802 may be embodied as various storage media such as an Electrically Erasable Programmable Read Only Memory (EEPROM), a Flash memory (Flash memory), and a Programmable Read Only Memory (PROM). The processor 801 may be implemented to include one or more central processors or one or more field programmable gate arrays that integrate one or more central processor cores. In particular, the central processor or central processor core may be implemented as a CPU, MCU or Digital Signal Processor (DSP).

The embodiment of the invention also provides a digital currency mining machine, which comprises: the device comprises N force calculation boards, wherein the N force calculation boards are connected in series to form a series power supply structure. The power supply positive terminal of the first force computing plate in the series power supply structure is connected with the positive terminal of a power supply, the power supply negative terminal of the last force computing plate in the series power supply structure is connected with the negative terminal of the power supply, each force computing plate comprises a plurality of computing chips, and N is a positive integer of at least 2; a control panel, comprising: a memory and a processor; wherein the memory has stored therein an application executable by the processor for causing the processor to execute the method of starting a digital currency mining machine as claimed in any one of the above; each force calculation board in the N force calculation boards is in communication connection with the control board through a respective communication interface.

It should be noted that not all steps and modules in the above flows and structures are necessary, and some steps or modules may be omitted according to actual needs. The execution order of the steps is not fixed and can be adjusted as required. The division of each module is only for convenience of describing adopted functional division, and in actual implementation, one module may be divided into multiple modules, and the functions of multiple modules may also be implemented by the same module, and these modules may be located in the same device or in different devices.

The hardware modules in the various embodiments may be implemented mechanically or electronically. For example, a hardware module may include a specially designed permanent circuit or logic device (e.g., a special purpose processor such as an FPGA or ASIC) for performing specific operations. A hardware module may also include programmable logic devices or circuits (e.g., including a general-purpose processor or other programmable processor) that are temporarily configured by software to perform certain operations. The implementation of the hardware module in a mechanical manner, or in a dedicated permanent circuit, or in a temporarily configured circuit (e.g., configured by software), may be determined based on cost and time considerations.

The present invention also provides a machine-readable storage medium storing instructions for causing a machine to perform a method as described herein. Specifically, a system or an apparatus equipped with a storage medium on which a software program code that realizes the functions of any of the embodiments described above is stored may be provided, and a computer (or a CPU or MPU) of the system or the apparatus is caused to read out and execute the program code stored in the storage medium. Further, part or all of the actual operations may be performed by an operating system or the like operating on the computer by instructions based on the program code. The functions of any of the above-described embodiments may also be implemented by writing the program code read out from the storage medium to a memory provided in an expansion board inserted into the computer or to a memory provided in an expansion unit connected to the computer, and then causing a CPU or the like mounted on the expansion board or the expansion unit to perform part or all of the actual operations based on the instructions of the program code.

Examples of the storage medium for supplying the program code include floppy disks, hard disks, magneto-optical disks, optical disks (e.g., CD-ROMs, CD-R, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs, DVD + RWs), magnetic tapes, nonvolatile memory cards, and ROMs. Alternatively, the program code may be downloaded from a server computer or the cloud by a communication network.

"exemplary" means "serving as an example, instance, or illustration" herein, and any illustration, embodiment, or steps described as "exemplary" herein should not be construed as a preferred or advantageous alternative. For the sake of simplicity, the drawings are only schematic representations of the parts relevant to the invention, and do not represent the actual structure of the product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "a" does not mean that the number of the relevant portions of the present invention is limited to "only one", and "a" does not mean that the number of the relevant portions of the present invention "more than one" is excluded. In this document, "upper", "lower", "front", "rear", "left", "right", "inner", "outer", and the like are used only to indicate relative positional relationships between relevant portions, and do not limit absolute positions of the relevant portions.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The starting method of the digital currency mining machine is characterized by comprising N computing force plates which are connected in series to form a series power supply structure, the N computing force plates are connected end to form a multi-stage series voltage domain, a power supply positive terminal of a first computing force plate in the series power supply structure is connected with a positive terminal of a power supply, a power supply negative terminal of a last computing force plate in the series power supply structure is connected with a negative terminal of the power supply, each computing force plate comprises a plurality of computing chips, and N is a positive integer of at least 2; the method comprises the following steps:

turning on the power supply;

2. A method of starting a digital currency machine as claimed in claim 1,

between the sending of the activation signal to the ore refrigeration component and the turning on of the power supply, the method further comprises: simultaneously providing a reset signal to each of the N force plates and simultaneously maintaining the reset signal for each force plate;

3. A method of starting a digital currency machine as claimed in claim 2, wherein the clock signal transmission path of each of said N force plates has a chain-like configuration; between said simultaneously releasing said reset signal for each force plate and said controlling each computational chip in said N force plates to synchronously turn on cores in a progressive manner, the method further comprises:

4. A method of starting a digital currency machine as claimed in claim 1, wherein between said sending a start signal to the machine refrigeration and said turning on the power supply, the method further comprises:

detecting a temperature of each of the N force calculation plates;

determining a maximum value of the temperatures of each of the N force plates;

5. A starting method for a digital currency ore machine according to any one of claims 1 to 4, wherein after each computational chip in the controlling N computational boards synchronously turns on a core in a progressive manner, the method further comprises:

detecting a voltage of each of the N force plates;

6. The starting device for the digital currency mining machine is characterized by comprising N computing force plates which are connected in series to form a series power supply structure, wherein the N computing force plates are connected end to form a multi-stage series voltage domain, a power supply positive terminal of a first computing force plate in the series power supply structure is connected with a positive terminal of a power supply, a power supply negative terminal of a last computing force plate in the series power supply structure is connected with a negative terminal of the power supply, each computing force plate comprises a plurality of computing chips, and N is a positive integer of at least 2; the device includes:

the starting module is used for starting the power supply;

7. A starting apparatus for a digital currency machine as claimed in claim 6,

the sending module is further configured to simultaneously provide a reset signal to each of the N force computing plates and simultaneously maintain the reset signal of each force computing plate between the sending of the start signal to the mine refrigeration component and the turning on of the power supply; and synchronously starting the cores in a progressive mode between the starting power supply and each operation chip in the N control computation force plates, and simultaneously releasing the reset signal for each computation force plate.

8. A starting apparatus for a digital currency machine as claimed in claim 7, wherein the clock signal transmission path of each of said N force plates has a chain-like configuration; the device also includes:

9. A starting apparatus for a digital currency machine as claimed in claim 6, further comprising:

10. A starting apparatus of a digital money machine according to any one of claims 6-9, wherein,

the control module is further used for detecting the voltage of each force calculation plate in the N force calculation plates; determining a force calculation plate which is a voltage adjustment object from the N force calculation plates based on the comparison result of the voltage of each force calculation plate in the N force calculation plates and a preset voltage range; and controlling a voltage equalizing circuit in the force computing plate as the voltage adjusting object to adjust the voltage of the force computing plate as the voltage adjusting object, or controlling a voltage equalizing circuit corresponding to the force computing plate as the voltage adjusting object in a power supply to adjust the voltage of the force computing plate as the voltage adjusting object.

11. A starting apparatus for a digital currency mining machine, comprising:

a memory;

a processor;

wherein the memory has stored therein an application executable by the processor for causing the processor to perform the method of starting a digital currency machine as claimed in any one of claims 1 to 5.

12. A digital currency mining machine, comprising:

the power supply system comprises N power calculation plates, a power supply and a power supply, wherein the N power calculation plates are connected in series to form a series power supply structure, the N power calculation plates are connected end to form a multi-stage series voltage domain, a power supply positive terminal of a first power calculation plate in the series power supply structure is connected with a positive terminal of a power supply, a power supply negative terminal of a last power calculation plate in the series power supply structure is connected with a negative terminal of the power supply, each power calculation plate comprises a plurality of operation chips, and N is a positive integer of at least 2;

a control panel, comprising: a memory and a processor; wherein the memory has stored therein an application executable by the processor for causing the processor to perform the method of starting a digital currency machine as claimed in any one of claims 1 to 5;

13. A computer readable storage medium having computer readable instructions stored therein for performing the method of starting a digital currency machine as claimed in any one of claims 1 to 5.