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CN112309460B - Dual-port SRAM with separated read and write - Google Patents

Dual-port SRAM with separated read and write Download PDF

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Publication number
CN112309460B
CN112309460B CN202011309949.1A CN202011309949A CN112309460B CN 112309460 B CN112309460 B CN 112309460B CN 202011309949 A CN202011309949 A CN 202011309949A CN 112309460 B CN112309460 B CN 112309460B
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tube
pull
read
selection
threshold voltage
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CN112309460A (en
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The invention discloses a dual-port SRAM with separate reading and writing, the memory cell includes: a main body circuit, a write port circuit and a read port circuit; the write port circuit comprises a first selection tube and a second selection tube; the read port circuit comprises a read selection tube and a read pull-down tube; the gate structure of each MOS transistor of the memory unit adopts a metal gate; the work function layers of the metal grids of the first NMOS pull-down tube, the first selection tube, the read selection tube and the read pull-down tube are arranged separately to adjust the gamma ratio and the beta ratio, and after the work function layers of the metal grids are arranged, the first NMOS pull-down tube and the second NMOS pull-down tube have a first threshold voltage, and the first selection tube and the second selection tube have a second threshold voltage; the read select transistor has a third threshold voltage and the read pull-down transistor has a fourth threshold voltage such that the second threshold voltage is less than the first threshold voltage and the fourth threshold voltage is less than the third threshold voltage. The invention can improve the NM performance of the circuit, does not need to adjust the parameters of an active region and adopts an auxiliary circuit, and can be well applied to the FinFET SRAM.

Description

Dual-port SRAM with separated read and write
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a dual-port SRAM with separate read and write operations.
Background
As shown in fig. 1, a circuit diagram of a memory cell of a conventional 6T type SRAM is shown, 6T indicates that there are 6 transistors in the memory cell, and as can be seen from fig. 1, the memory cell of the conventional 6T type SRAM includes a main body circuit composed of P type pull-up transistors 103 and 104 and N type pull-down transistors 105 and 106, and a port circuit composed of selection transistors 101 and 102, and both reading and writing are performed through the port circuit. In fig. 1, the selection transistor 101 is also denoted by PG1, the selection transistor 102 is also denoted by PG2, the P-type pull-up transistor 103 is also denoted by PU1, the P-type pull-up transistor 104 is also denoted by PU2, the N-type pull-down transistor 105 is also denoted by PD1, and the N-type pull-down transistor 106 is also denoted by PD 2. The P-type pull-up tube 103 and the N-type pull-down tube 105 form a CMOS inverter, the P-type pull-up tube 104 and the N-type pull-down tube 106 also form a CMOS inverter, and the two CMOS inverters are connected end to form a latch, wherein the latch comprises two first storage nodes Q and the second storage nodes Qb which are mutually opposite and interlocked. The sources of the P-type pull-up transistors 103 and 104 are both connected to the power supply voltage Vdd, the sources of the N-type pull-down transistors 105 and 106 are both grounded Vss, the gates of the selection transistors 101 and 102 are both connected to the word lines, the selection transistor 101 connects and disconnects the first storage node Q to and from the bit line BL under the control of the word lines, and the selection transistor 102 connects and disconnects the second storage node Qb to and from the bit line BLB, the bit lines BL and BLB being opposite to each other.
The memory cell read/write of the existing 6T SRAM shown in fig. 1 employs the same port, which makes the Noise Margin (NM) of the circuit worse as the static Noise Margin (Static Noise Margin, SNM).
In order to improve SNM, a read-write split SRAM circuit commonly used in the industry at present is generally used as a memory cell of an 8T2P type SRAM shown in fig. 2, where 8T indicates that there are 8 transistors in the memory cell, and 2P indicates that there are two ports (ports), namely, a write port (write port) and a read port (read port). As can be seen from fig. 2, the memory cell of the conventional 8T 2P-type SRAM includes a main circuit composed of P-type pull-up tubes 3 and 4 and N-type pull-down tubes 5 and 6, a write port circuit composed of selection tubes 1 and 2, and a read port circuit composed of a read selection tube 7 and a read pull-down tube 8. In fig. 2, a selection tube 1 is also denoted by PG1, a selection tube 2 is also denoted by PG2, a P-type pull-up tube 3 is also denoted by PU1, a P-type pull-up tube 4 is also denoted by PU2, an N-type pull-down tube 5 is also denoted by PD1, and an N-type pull-down tube 6 is also denoted by PD 2. The read select pipe 7 is also denoted by RPG and the read pull-down pipe 8 is also denoted by RPD.
It can be seen that the body circuit and the write port circuit are an existing conventional 6T-SRAM memory cell. The P-type pull-up tube 3 and the N-type pull-down tube 5 form a CMOS inverter, the P-type pull-up tube 4 and the N-type pull-down tube 6 also form a CMOS inverter, and the two CMOS inverters are connected end to form a latch, wherein the latch comprises two first storage nodes Q and the second storage nodes Qb which are mutually opposite and mutually interlocked. The sources of the P-type pull-up transistors 3 and 4 are both connected to a power supply voltage Vdd, the sources of the N-type pull-down transistors 5 and 6 are both grounded Vss, the gates of the selection transistors 1 and 2 are both connected to a write word line WWL, and under the control of the write word line WWL, the selection transistor 1 connects and disconnects the first storage node Q to and from the first write bit line WBL, and the selection transistor 2 connects and disconnects the second storage node Qb to and from the second write bit line WBLB.
The write port circuitry enables individual write operations. The read port circuit of fig. 2 is also capable of performing a separate read operation, with the gate of the read pull-down tube 8 connected to the second storage node Qb and the source connected to Vss. The drain electrode of the read pull-down tube 8 is connected with the source electrode of the read selection tube 7, and the drain electrode of the selection tube 7 is connected with the read bit line RBL.
In the circuit shown in fig. 2, when a read operation is performed, the read word line RWL is connected to a high level such as Vdd, and the read select transistor 7 is turned on; the read bit line RBL is also connected with a high level, so that when the information stored on the second storage node Qb is different, the conduction state of the read pull-down tube 8 is different, and when the read pull-down tube 8 is conducted, the potential of the read bit line RBL is reduced; when the read pull-down pipe 8 is turned off, the potential of the read bit line RBL is kept at a high level.
While in the write operation and standby, the read word line RWL is connected to a low level such as the ground Vss, and at this time, the read select transistor 7 is turned off, and the high level on the read bit line RBL does not adversely affect the first storage node Q and the second storage node Qb. Finally, the SNW of the circuit can be improved.
In the existing dual-port SRAM with mixed read and write, a read-write mixed port circuit is added to the memory cell of the dual-port SRAM with mixed read and write based on the 6T memory cell shown in fig. 1, so that the two read-write mixed port circuits can be separately controlled, and parallel operation on two different rows can be realized in the SRAM array.
The noise margin of the memory cell of the SRAM mainly includes: noise margin (Hold Noise Margin, HNM), read noise margin (Read Noise Margin, RNM), write noise margin (Write Noise Margin, WNM) are maintained.
HNM is NM in the hold process without read-write, RNM is NM in the read process, WNM is NM in the write process. HNM, RNM and WRM are mainly related to the following three ratios:
α＝I PU /I PD ,I PU indicating the current of the pull-up tube of the main circuit, I PD The current of the pull-up tube of the main circuit is shown, and for the memory cell of the 8T2P type SRAM shown in FIG. 2, I PU The source-drain conduction current of the P-type pull-up tube 3 or the P-type pull-up tube 4 is represented by I PD Represents the source-drain conduction current of the P-type pull-up tube 3 or the P-type pull-up tube 4, and the N-type pull-down tube 5 or the N-type pull-down tubeThe source and drain of the pull tube 6 conduct current.
β＝I PD /I PG ,I PD Indicating the current of the pull-down tube during reading, I PG Indicating the current of the select transistor during read, I for the memory cell of the 8T2P type SRAM shown in FIG. 2 PG Indicating the source-drain conduction current of the read select transistor 7, I PD The source-drain on current of the read pull-down tube 8 is shown.
γ＝I PG /I PU ,I PU Indicating the current drawn up in the writing process, I PG Indicating the current of the select transistor during writing, I for the memory cell of the 8T2P type SRAM shown in FIG. 2 PG Indicating the source-drain on-current of the selection tube 1 or 2, I PU The source-drain on-current of the P-type pull-up tube 3 or the P-type pull-up tube 4 is shown.
When each MOS transistor of the memory cell is a planar device, the MOS transistors are formed in the active region, and the source-drain conduction current of the NMOS is I PD Or I PG Is the source-drain conduction current of PMOS, I PU The adjustment of the above ratio is easily achieved by the size adjustment of the active region and by the doping adjustment of the threshold voltage of the active region, resulting in a good NM.
When the transistor of the SRAM adopts a fin transistor (FinFET), the source-drain conduction current of the NMOS is I PD Or I PG Is generally the same as the source-drain on current of PMOS, and the adjustment of β and γ is completely different from that of planar devices. In the existing method, an auxiliary circuit is generally needed to realize the adjustment of beta and gamma, but the circuit area is increased.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a memory cell structure of an SRAM, which can realize the adjustment of beta and gamma ratio, does not need to adjust the parameters of an active region and does not need to adopt an auxiliary circuit, can be well applied to the FinFET SRAM, improves the NM performance of the circuit and can save the area.
In order to solve the above technical problems, the dual-port SRAM with separate read and write provided by the present invention, the memory cell includes: a body circuit, a write port circuit and a read port circuit.
The body circuit includes a pair of first and second storage nodes that are mutually inverted and mutually latched.
The main circuit is formed by connecting a first CMOS inverter and a second CMOS inverter, wherein the output end of the first CMOS inverter and the input end of the second CMOS inverter are connected together and serve as the second storage node, and the output end of the second CMOS inverter and the input end of the first CMOS inverter are connected together and serve as the first storage node.
The write port circuit includes a first select tube and a second select tube.
The read port circuit comprises a read select tube and a read pull-down tube.
The first CMOS inverter is composed of a first PMOS pull-up tube and a first NMOS pull-down tube.
The second CMOS inverter is composed of a second PMOS pull-up tube and a second NMOS pull-down tube.
The first selection tube, the second selection tube, the reading selection tube and the reading pull-down tube are NMOS tubes.
The first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube, the second NMOS pull-down tube, the first selection tube, the second selection tube, the reading selection tube and the reading pull-down tube all adopt metal grids in grid structures.
And the metal gate of the first PMOS pull-up tube is the same as the metal gate of the second PMOS pull-up tube.
The work function layers of the first NMOS pull-down tube, the first selection tube, the read selection tube and the metal gate of the read pull-down tube are arranged separately to adjust the gamma ratio and the beta ratio, wherein the gamma ratio is the ratio of the source leakage current of the first selection tube to the source leakage current of the first PMOS pull-up tube; the beta ratio is the ratio of the source-drain current of the read pull-down tube to the source-drain current of the read select tube.
The work function layers of the metal gates of the first NMOS pull-down tube, the first selection tube, the read selection tube and the read pull-down tube are set as follows:
the metal gate of the first NMOS pull-down tube is provided with a first work function layer, and the metal gate of the second NMOS pull-down tube is the same as the metal gate of the first NMOS pull-down tube.
The metal gate of the first selection tube is provided with a second work function layer, and the metal gate of the second selection tube is the same as the metal gate of the first selection tube.
The metal gate of the read select tube has a third work function layer.
The metal gate of the read pull-down tube has a fourth work function layer.
The first work function layer makes the threshold voltage of the first NMOS pull-down tube be a first threshold voltage.
The second work function layer makes the threshold voltage of the first selection tube be a second threshold voltage.
The third work function layer makes the threshold voltage of the read select transistor be a third threshold voltage.
The fourth work function layer makes the threshold voltage of the read pull-down tube be a fourth threshold voltage.
The second threshold voltage is less than the first threshold voltage to increase the gamma ratio and thereby improve the write noise margin.
The fourth threshold voltage is less than the third threshold voltage to increase the beta ratio and thereby improve the read noise margin.
A further improvement is that the third threshold voltage is equal to the first threshold voltage.
A further improvement is that the second threshold voltage is less than or equal to the fourth threshold voltage.
A further improvement is that the gate of the first select tube and the gate of the second select tube are both connected to a write word line.
A first source drain region of the first selection tube is connected with a first write bit line, and a second source drain region of the first selection tube is connected with the first storage node.
The first source drain region of the second selection tube is connected with a second write bit line, and the second source drain region of the first selection tube is connected with the second storage node.
The grid electrode of the reading selection tube is connected with a reading word line; the first source drain region of the reading selection tube is connected with a reading bit line, and the second source drain region of the reading selection tube is connected with the first source drain region of the reading pull-down tube.
And a second source drain region of the read pull-down tube is grounded, and a grid electrode of the read pull-down tube is connected with one of the first storage node and the second storage node.
The gate structures of the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube, the second NMOS pull-down tube, the first selection tube, the second selection tube, the read selection tube and the read pull-down tube are provided with gate dielectric layers with high dielectric constant layers.
In a further improvement, the high dielectric constant layer is formed on a semiconductor substrate, and the metal gate is formed on the high dielectric constant layer.
A further improvement is that the gate dielectric layer also has an interfacial layer between the high dielectric constant layer and the semiconductor substrate.
A further improvement is that the metal gate includes a corresponding work function layer and a metal conductive material layer.
A further improvement is that the material of the metallic conductive material layer comprises aluminum.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
A further improvement is that the material of the interface layer comprises silicon oxide.
A further improvement is that the material of the high dielectric constant layer comprises hafnium oxide.
The first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube, the second NMOS pull-down tube, the first selection tube, the second selection tube, the read selection tube and the read pull-down tube are FinFETs.
Further improvements are that the FinFET includes a fin body, and the corresponding gate structure covers the side and top surfaces of the fin body.
The further improvement is that on the layout structure, the fins are parallel to each other.
The further improvement is that, on the layout structure of the storage unit:
the metal conductive material layers of the first PMOS pull-up tube and the first NMOS pull-down tube are connected together.
The metal conductive material layers of the second PMOS pull-up tube and the second NMOS pull-down tube are connected together.
The metal conductive material layer of the read pull-down tube is connected with the metal conductive material layer of one of the first PMOS pull-up tube and the second PMOS pull-up tube.
In a further improvement, the first PMOS pull-up tube is formed on one fin body, and the second PMOS pull-up tube is formed on one fin body.
The first NMOS pull-down tube is formed on 2 fin bodies, and the second NMOS pull-down tube is formed on 2 fin bodies.
The first selection tube is formed on 2 fin bodies, and the first selection tube is formed on 2 fin bodies.
The read pull-down tube is formed on 3 fin bodies, and the read selection tube is formed on 3 fin bodies.
The further improvement is that, on the layout structure of the storage unit:
the first NMOS pull-down tube and the first selection tube are positioned on the same 2 fin bodies.
The second NMOS pull-down tube and the second selection tube are positioned on the same 2 fin bodies.
The read pull-down tube and the read select tube are located on the same 3 fin bodies.
In the invention, according to the function difference of each NMOS of the read-write separated dual-port SRAM in the read-write process, the work function layers of the metal gates of each NMOS are correspondingly arranged, and the second threshold voltage of the first and second selection tubes can be smaller than the first threshold voltage of the first NMOS pull-down tube, namely the standard threshold voltage, by arranging the second work function layers of the first and second selection tubes, thus being beneficial to increasing the gamma ratio and increasing WNM.
By setting the fourth work function layer of the read pull-down tube, the fourth threshold voltage of the read pull-down tube is smaller than the third threshold voltage of the read select tube, so that the beta ratio is favorably increased, and RNM is increased.
By arranging the first work function layer of the first NMOS pull-down tube and the third work function layer of the read selection tube, the first threshold voltage and the third threshold voltage can both keep the standard threshold voltage, and the relatively larger first threshold voltage of the first NMOS pull-down tube is favorable for keeping the alpha ratio to be larger, so that the HNM is favorable for increasing; reading the relatively large third threshold voltage of the select tube then facilitates further increases in beta ratio, thereby further increasing RNM.
Therefore, the invention can increase the alpha ratio, the beta ratio and the gamma ratio simultaneously through the arrangement of the work function layer of the NMOS metal gate in the SRAM, thereby respectively improving HNM, RNM and WNM of the circuit and finally improving NM of the circuit.
According to the invention, the NM of the circuit can be improved only by setting the work function layer of the metal gate of the NMOS, the parameters such as the size and the doping concentration of the active region are not required to be adjusted, an additional photomask is not required to be added, and the work functions of different logic devices can be selected to match, so that the invention can be well applied to the FinFET SRAM, and an auxiliary circuit is not required to be additionally adopted, and the NM performance of the FinFET SRAM can be improved, and the area can be saved.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a circuit diagram of a memory cell of a conventional 6T type SRAM;
FIG. 2 is a circuit diagram of a memory cell of a conventional 8T2P type SRAM;
FIG. 3 is a layout of a dual port SRAM with read-write separation in accordance with an embodiment of the present invention;
fig. 4 is an enlarged layout view of one memory cell in fig. 3.
Detailed Description
The circuit diagram of the read-write separated dual-port SRAM provided by the invention is also shown in reference to FIG. 2, and as shown in FIG. 3, the circuit diagram of the read-write separated dual-port SRAM is a layout of the read-write separated dual-port SRAM in the embodiment of the invention; FIG. 4 is an enlarged layout view of one of the memory cells 201 of FIG. 3; the memory cell 201 of the dual-port SRAM of the embodiment of the present invention includes: a body circuit, a write port circuit and a read port circuit.
The body circuit includes a pair of first and second storage nodes Q and Qb that are mutually inverted and mutually latched.
The main circuit is formed by connecting a first CMOS inverter and a second CMOS inverter, wherein the output end of the first CMOS inverter is connected with the input end of the second CMOS inverter and is used as the second storage node Qb, and the output end of the second CMOS inverter is connected with the input end of the first CMOS inverter and is used as the first storage node Q.
The write port circuit comprises a first selection tube 1 and a second selection tube 2, the first selection tube 1 is further marked with PG1, and the second selection tube 2 is further marked with PG 2.
The read port circuit comprises a read select tube 7 and a read pull-down tube 8, wherein the read select tube 7 is also marked with PRG, and the read pull-down tube 8 is also marked with PRD.
The first CMOS inverter is composed of a first PMOS pull-up tube 3 and a first NMOS pull-down tube 5. The first PMOS pull-up tube 3 is also labeled PU1 and the first NMOS pull-down tube 5 is also labeled PD 1.
The second CMOS inverter is composed of a second PMOS pull-up tube 4 and a second NMOS pull-down tube 6. The second PMOS pull-up tube 4 is also labeled PU2 and the second NMOS pull-down tube 6 is also labeled PD 2.
The first selection tube 1, the second selection tube 2, the read selection tube 7 and the read pull-down tube 8 are NMOS tubes.
The gate structures of the first PMOS pull-up tube 3, the second PMOS pull-up tube 4, the first NMOS pull-down tube 5, the second NMOS pull-down tube 6, the first selection tube 1, the second selection tube 2, the read selection tube 7 and the read pull-down tube 8 all adopt metal gates.
The metal gate of the first PMOS pull-up tube 3 is the same as the metal gate of the second PMOS pull-up tube 4.
The work function layers of the metal gates of the first NMOS pull-down tube 5, the first select tube 1, the read select tube 7, and the read pull-down tube 8 are separately arranged to adjust the γ ratio and the β ratio, where the γ ratio is the ratio of the source-drain current of the first select tube 1 to the source-drain current of the first PMOS pull-up tube 3; the beta ratio is the ratio of the source-drain current of the read pull-down tube 8 to the source-drain current of the read select tube 7.
The work function layers of the metal gates of the first NMOS pull-down tube 5, the first select tube 1, the read select tube 7, and the read pull-down tube 8 are set as follows:
the metal gate of the first NMOS pull-down pipe 5 has a first work function layer, and the metal gate of the second NMOS pull-down pipe 6 is the same as the metal gate of the first NMOS pull-down pipe 5.
The metal gate of the first selection tube 1 has a second work function layer, and the metal gate of the second selection tube 2 is the same as the metal gate of the first selection tube 1.
The metal gate of the read select pipe 7 has a third work function layer.
The metal gate of the read pulldown tube 8 has a fourth work function layer.
The first work function layer makes the threshold voltage of the first NMOS pull-down tube 5 be a first threshold voltage.
The second work function layer makes the threshold voltage of the first selection tube 1 be a second threshold voltage.
The third work function layer makes the threshold voltage of the read select transistor 7 a third threshold voltage.
The fourth work function layer makes the threshold voltage of the read pull-down tube 8 a fourth threshold voltage.
The second threshold voltage is less than the first threshold voltage to increase the gamma ratio and thereby improve the write noise margin.
The fourth threshold voltage is less than the third threshold voltage to increase the beta ratio and thereby improve the read noise margin.
In an embodiment of the present invention, the third threshold voltage is equal to the first threshold voltage.
The second threshold voltage is less than or equal to the fourth threshold voltage.
Taking the first threshold voltage as an NMOS (N-type) standard threshold voltage, namely NSVT (N-type), and taking the third threshold voltage as NSVT; the fourth threshold voltage can be an N-type low threshold voltage, i.e., NLVT, and the second threshold voltage can be an N-type ultra-low threshold voltage, i.e., NULVT.
The gate of the first selection tube 1 and the gate of the second selection tube 2 are both connected to a write word line WWL.
The first source-drain region of the first selection tube 1 is connected with a first write bit line WBL, and the second source-drain region of the first selection tube 1 is connected with the first storage node Q.
The first source-drain region of the second selection tube 2 is connected with a second write bit line WBLB, and the second source-drain region of the first selection tube 1 is connected with the second storage node Qb. In fig. 2, the first write bit line and the second write bit line are denoted by WBL and WBLB, respectively; however, WBL is used in the layout corresponding to fig. 3, and only in the actual use process, WBL and WBLB are signals with opposite phases.
The grid electrode of the read selection tube 7 is connected with a read word line RWL; the first source-drain region of the read selection tube 7 is connected with a read bit line RBL, and the second source-drain region of the read selection tube 7 is connected with the first source-drain region of the read pull-down tube 8.
The second source drain region of the read pull-down transistor 8 is grounded to Vss, and the gate of the read pull-down transistor 8 is connected to one of the first storage node Q and the second storage node Qb. The gate of the read pull-down tube 8 is shown in fig. 2 connected to the second storage node Qb; the layout of fig. 3 shows that the gate of the read pull-down tube 8 is connected to the first storage node Q. That is, in the embodiment of the present invention, only one storage node needs to be connected to achieve reading. The storage nodes are also denoted Node in fig. 3.
The gate structures of the first PMOS pull-up tube 3, the second PMOS pull-up tube 4, the first NMOS pull-down tube 5, the second NMOS pull-down tube 6, the first selection tube 1, the second selection tube 2, the read selection tube 7 and the read pull-down tube 8 have gate dielectric layers with high dielectric constant layers.
The high dielectric constant layer is formed on a semiconductor substrate, and the metal gate is formed on the high dielectric constant layer. The semiconductor substrate includes a silicon substrate.
The gate dielectric layer also has an interfacial layer between the high dielectric constant layer and the semiconductor substrate. The material of the interface layer comprises silicon oxide. The material of the high dielectric constant layer comprises hafnium oxide.
The metal gate includes a corresponding work function layer and a metal conductive material layer 203. The material of the metal conductive material layer 203 includes aluminum.
The first PMOS pull-up tube 3, the second PMOS pull-up tube 4, the first NMOS pull-down tube 5, the second NMOS pull-down tube 6, the first select tube 1, the second select tube 2, the read select tube 7, and the read pull-down tube 8 are all finfets. The embodiment of the invention can realize the improvement of NM without adjusting parameters such as the size and the doping concentration of the active region, so the embodiment of the invention can be well applied to FinFETs.
The FinFET includes a fin 202, and the corresponding gate structure covers the sides and top surfaces of the fin 202. The fins 202 are parallel to each other in layout structure. Since the layout has regions where the gate structure is not required, part of the fin 202 is cut off, and in fig. 3, the mark 202a corresponds to the region cut off by the fin 202.
On the layout structure of the memory cell 201:
the metal conductive material layers 203 of the first PMOS pull-up tube 3 and the first NMOS pull-down tube 5 are connected together.
The metal conductive material layers 203 of the second PMOS pull-up tube 4 and the second NMOS pull-down tube 6 are connected together.
The metal conductive material layer 203 of the read pull-down tube 8 is connected to the metal conductive material layer 203 of one of the first PMOS pull-up tube 3 and the second PMOS pull-up tube 4.
The first PMOS pull-up tube 3 is formed on one of the fins 202, and the second PMOS pull-up tube 4 is formed on one of the fins 202.
The first NMOS pull-down pipes 5 are formed on 2 of the fin bodies 202, and the second NMOS pull-down pipes 6 are formed on 2 of the fin bodies 202.
The first selection tube 1 is formed on 2 fin bodies 202, and the first selection tube 1 is formed on 2 fin bodies 202.
The read pulldown tube 8 is formed on 3 of the fins 202, and the read select tube 7 is formed on 3 of the fins 202.
As can be seen from fig. 4, on the layout structure of the memory cell 201:
the first NMOS pull-down tube 5 and the first select tube 1 are located on the same 2 fins 202.
The second NMOS pull-down tube 6 and the second select tube 2 are located on the same 2 fins 202.
The read pulldown tube 8 and the read select tube 7 are located on the same 3 fins 202.
In fig. 3, 4 memory cells 201 are shown, and as indicated by 4 corresponding dashed boxes, the layout of the 4 memory cells 201 is generally symmetrical, such as centrally symmetrical. In the layout of fig. 3, a total of 4 layers are shown, respectively: the fin corresponding to the mark 202; marking 203 the metal conductive material layer of the corresponding metal gate; the via corresponding to reference 204 is typically the zeroth layer via denoted by M0 PO; the metal layer corresponding to the reference 205, the metal layer 205 is typically the zeroth metal layer, generally denoted by M0D.
In the embodiment of the invention, according to the difference of functions of the NMOS of the read-write separated dual-port SRAM in the read-write process, the work function layers of the metal gates of the NMOS are correspondingly arranged, and the second threshold voltage of the first and second selection tubes 2 can be smaller than the first threshold voltage of the first NMOS pull-down tube 5, namely the standard threshold voltage, by arranging the second work function layers of the first and second selection tubes 2, thus being beneficial to increasing the gamma ratio and WNM.
By setting the fourth work function layer of the read pull-down tube 8, the fourth threshold voltage of the read pull-down tube 8 can be smaller than the third threshold voltage of the read select tube 7, which is beneficial to increasing the beta ratio and increasing the RNM.
By arranging the first work function layer of the first and NMOS pull-down tubes and the third work function layer of the read select tube 7, the first threshold voltage and the third threshold voltage can both keep the standard threshold voltage, and the relatively larger first threshold voltage of the first and NMOS pull-down tubes is beneficial to keeping the alpha ratio to a larger value, so that the HNM is beneficial to increasing; the relatively large third threshold voltage of the sense select tube 7 facilitates further increases in beta ratio, thereby further increasing RNM.
Therefore, the embodiment of the invention can simultaneously increase the alpha ratio, the beta ratio and the gamma ratio by arranging the work function layer of the NMOS metal gate in the SRAM, thereby respectively improving HNM, RNM and WNM of the circuit and finally improving NM of the circuit.
According to the embodiment of the invention, the NM of the circuit can be improved only by setting the work function layer of the metal gate of the NMOS, the parameters such as the size and the doping concentration of the active region are not required to be adjusted, an additional photomask is not required to be added, and the work functions of different logic devices can be selected to match, so that the embodiment of the invention can be well applied to the FinFET SRAM, and an auxiliary circuit is not required to be additionally adopted, and the embodiment of the invention can improve the NM performance of the FinFET SRAM and save the area.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (18)

1. A dual port SRAM with separate read and write, wherein the memory cell comprises: a main body circuit, a write port circuit and a read port circuit;
the main body circuit comprises a pair of first storage nodes and second storage nodes which are mutually opposite and mutually latched;
the main circuit is formed by connecting a first CMOS inverter and a second CMOS inverter, the output end of the first CMOS inverter and the input end of the second CMOS inverter are connected together and serve as the second storage node, and the output end of the second CMOS inverter and the input end of the first CMOS inverter are connected together and serve as the first storage node;
the write port circuit comprises a first selection tube and a second selection tube;
the read port circuit comprises a read selection tube and a read pull-down tube;
the first CMOS inverter consists of a first PMOS pull-up tube and a first NMOS pull-down tube;
the second CMOS inverter consists of a second PMOS pull-up tube and a second NMOS pull-down tube;
the first selection tube, the second selection tube, the reading selection tube and the reading pull-down tube are NMOS tubes;
the gate structures of the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube, the second NMOS pull-down tube, the first selection tube, the second selection tube, the reading selection tube and the reading pull-down tube all adopt metal gates;
the metal gate of the first PMOS pull-up tube is the same as the metal gate of the second PMOS pull-up tube;
the work function layers of the first NMOS pull-down tube, the first selection tube, the read selection tube and the metal gate of the read pull-down tube are arranged separately to adjust the gamma ratio and the beta ratio, wherein the gamma ratio is the ratio of the source leakage current of the first selection tube to the source leakage current of the first PMOS pull-up tube; the beta ratio is the ratio of the source leakage current of the read pull-down tube to the source leakage current of the read select tube;
the work function layers of the metal gates of the first NMOS pull-down tube, the first selection tube, the read selection tube and the read pull-down tube are set as follows:
the metal gate of the first NMOS pull-down tube is provided with a first work function layer, and the metal gate of the second NMOS pull-down tube is the same as the metal gate of the first NMOS pull-down tube;
the metal gate of the first selection tube is provided with a second work function layer, and the metal gate of the second selection tube is the same as the metal gate of the first selection tube;
the metal gate of the read select tube has a third work function layer;
the metal gate of the read pull-down tube has a fourth work function layer;
the first work function layer enables the threshold voltage of the first NMOS pull-down tube to be a first threshold voltage;
the second work function layer enables the threshold voltage of the first selection tube to be a second threshold voltage;
the third work function layer enables the threshold voltage of the reading selection tube to be a third threshold voltage;
the fourth work function layer enables the threshold voltage of the read pull-down tube to be a fourth threshold voltage;
the second threshold voltage is less than the first threshold voltage to increase the gamma ratio and thereby improve the write noise margin;
the fourth threshold voltage is less than the third threshold voltage to increase the beta ratio and thereby improve the read noise margin.
2. The dual port SRAM of claim 1, wherein: the third threshold voltage is equal to the first threshold voltage.
3. The dual port SRAM of claim 2, wherein: the second threshold voltage is less than or equal to the fourth threshold voltage.
4. The dual port SRAM of claim 1, wherein: the grid electrode of the first selection tube and the grid electrode of the second selection tube are connected to a writing line;
a first source drain region of the first selection tube is connected with a first write bit line, and a second source drain region of the first selection tube is connected with the first storage node;
the first source-drain region of the second selection tube is connected with a second write bit line, and the second source-drain region of the first selection tube is connected with the second storage node;
the grid electrode of the reading selection tube is connected with a reading word line; the first source drain region of the read selection tube is connected with a read bit line, and the second source drain region of the read selection tube is connected with the first source drain region of the read pull-down tube;
and a second source drain region of the read pull-down tube is grounded, and a grid electrode of the read pull-down tube is connected with one of the first storage node and the second storage node.
5. The dual port SRAM of claim 4, wherein: the gate structures of the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube, the second NMOS pull-down tube, the first selection tube, the second selection tube, the reading selection tube and the reading pull-down tube are provided with gate dielectric layers with high dielectric constant layers.
6. The dual port SRAM of claim 5, wherein: the high dielectric constant layer is formed on a semiconductor substrate, and the metal gate is formed on the high dielectric constant layer.
7. The dual port SRAM of claim 6, wherein: the gate dielectric layer also has an interfacial layer between the high dielectric constant layer and the semiconductor substrate.
8. The dual port SRAM of claim 6, wherein: the metal gate includes a corresponding work function layer and a metal conductive material layer.
9. The dual port SRAM of claim 8, wherein: the material of the metal conductive material layer comprises aluminum.
10. The method of manufacturing a high dielectric constant metal gate MOS transistor of claim 7 wherein: the semiconductor substrate includes a silicon substrate.
11. The method of manufacturing a high dielectric constant metal gate MOS transistor of claim 10 wherein: the material of the interface layer comprises silicon oxide.
12. The method of manufacturing a high dielectric constant metal gate MOS transistor of claim 5 wherein: the material of the high dielectric constant layer comprises hafnium oxide.
13. The dual port SRAM of claim 8, wherein: the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube, the second NMOS pull-down tube, the first selection tube, the second selection tube, the read selection tube and the read pull-down tube are FinFETs.
14. The dual port SRAM of claim 13, wherein: the FinFET includes a fin body, and the corresponding gate structure covers side and top surfaces of the fin body.
15. The dual port SRAM of claim 14, wherein: and on the layout structure, the fin bodies are parallel to each other.
16. The dual port SRAM of claim 15, wherein the read-write separation is performed by: on the layout structure of the storage unit:
the metal conductive material layers of the first PMOS pull-up tube and the first NMOS pull-down tube are connected together;
the metal conductive material layers of the second PMOS pull-up tube and the second NMOS pull-down tube are connected together;
the metal conductive material layer of the read pull-down tube is connected with the metal conductive material layer of one of the first PMOS pull-up tube and the second PMOS pull-up tube.
17. The dual port SRAM of claim 16, wherein: the first PMOS pull-up tube is formed on one fin body, and the second PMOS pull-up tube is formed on one fin body;
the first NMOS pull-down tube is formed on 2 fin bodies, and the second NMOS pull-down tube is formed on 2 fin bodies;
the first selection pipes are formed on 2 fin bodies, and the first selection pipes are formed on 2 fin bodies;
the read pull-down tube is formed on 3 fin bodies, and the read selection tube is formed on 3 fin bodies.
18. The dual port SRAM of claim 17, wherein the read-write separation is performed by: on the layout structure of the storage unit:
the first NMOS pull-down tube and the first selection tube are positioned on the same 2 fin bodies;
the second NMOS pull-down tube and the second selection tube are positioned on the same 2 fin bodies;
the read pull-down tube and the read select tube are located on the same 3 fin bodies.
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