CN111755335B

CN111755335B - Semiconductor structure and forming method thereof

Info

Publication number: CN111755335B
Application number: CN201910236559.7A
Authority: CN
Inventors: 陈福刚; 唐丽贤
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-03-27
Filing date: 2019-03-27
Publication date: 2023-05-05
Anticipated expiration: 2039-03-27
Also published as: CN111755335A

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein a well region and a drift region are formed in the substrate, a gate structure is formed on the substrate, an active region is formed in the well region on one side of the gate structure, a drain region is formed in the drift region on the other side of the gate structure, and an interlayer dielectric layer is formed on the substrate with the exposed gate structure; etching part of the thickness interlayer dielectric layer above the source region and the drain region to form an initial contact hole; etching the bottom of the initial contact hole and an interlayer dielectric layer on one side of the grid structure, which is close to the drain region, to form a contact hole exposing the source region and the drain region, and a deep groove positioned on one side of the grid structure, wherein the bottom of the deep groove is positioned in the interlayer dielectric layer and the bottom of the deep groove is lower than the top of the grid structure; a contact hole plug in the contact hole and a shield plug in the deep recess are formed. According to the invention, the initial contact hole is formed first, so that the bottom of the deep groove is easy to remain with a part of thickness interlayer dielectric layer, and the bridging probability between the shielding plug and the grid structure or the substrate is reduced.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid growth of the semiconductor industry, PICs (power integrated circuit, power integrated circuits) are being used in a variety of fields, and laterally diffused metal oxide semiconductor transistors (lateral diffusion metal oxide semiconductor, LDMOS) are of great importance in integrated circuit design and fabrication. LDMOS transistors are often required to have a higher breakdown voltage (breakdown voltage, BV) and a lower on-resistance (Ron) in use to improve transistor performance.

In the LDMOS transistor, since the drain terminal is subjected to a large voltage, its local electric field is strong, so hot carriers (hot electrons or hot holes) are easily generated, thereby causing a problem of hot carrier damage (hot carrier damage). The injection of hot electrons can be effectively neutralized by the introduction of H during the subsequent heat treatment. The hot holes are difficult to effectively balance and neutralize charges, so that an electric field in a vertical direction is easy to generate, and BV and Ron of the LDMOS transistor are further affected.

One current approach is to form an electric field shielding structure (field shield structure) on the side of the gate structure near the drain, which is usually at zero potential in the application of the LDMOS transistor, and forms a capacitor with the gate structure, so that a voltage opposite to the gate structure can be induced, thereby adsorbing hot carriers between the drain and the gate structure, and accordingly playing a role in inhibiting hot carrier injection.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of a transistor.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a well region and a drift region are formed in the substrate, a gate structure is formed on the substrate, the gate structure covers part of the well region and part of the drift region, an active region is formed in the well region at one side of the gate structure, a drain region is formed in the drift region at the other side of the gate structure, the drain region and the gate structure are separated by a transverse distance, an interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the interlayer dielectric layer covers the source region, the drain region and the gate structure; etching a part of thickness interlayer dielectric layer above the source region and the drain region, and forming an initial contact hole in the interlayer dielectric layer; etching the bottom of the initial contact hole and an interlayer dielectric layer on one side of the grid structure, which is close to the drain region, to form a contact hole exposing the source region and the drain region, and a deep groove on one side of the grid structure, wherein the bottom of the deep groove is positioned in the interlayer dielectric layer, and the bottom of the deep groove is lower than the top of the grid structure; and filling conductive materials in the contact hole and the deep groove to form a contact hole plug positioned in the contact hole and a shielding plug positioned in the deep groove.

Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: the substrate is internally provided with a well region and a drift region; a gate structure on the substrate, the gate structure covering a portion of the well region and a portion of the drift region; the source region is positioned in the well region at one side of the grid structure; the drain region is positioned in the drift region at the other side of the gate structure and is separated from the gate structure by a transverse distance; the interlayer dielectric layer is positioned on the substrate exposed by the gate structure and covers the gate structure; the contact hole plugs are positioned in the interlayer dielectric layers at two sides of the grid structure and are electrically connected with the source region and the drain region; the shielding plug is positioned in the interlayer dielectric layer and at least positioned on one side of the gate structure close to the drain region, the bottom of the shielding plug is positioned in the interlayer dielectric layer, and the bottom of the shielding plug positioned on one side of the gate structure is lower than the top of the gate structure.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the embodiment of the invention, an interlayer dielectric layer with partial thickness is etched firstly, an initial contact hole is formed in the interlayer dielectric layer above a source region and a drain region, then the interlayer dielectric layer at the bottom of the initial contact hole and at one side of a grid structure close to the drain region is etched, and a contact hole exposing the source region and the drain region and a deep groove positioned at one side of the grid structure are formed; because the initial contact hole is formed firstly, the interlayer dielectric layer in the region corresponding to the deep groove is not etched, before the subsequent etching step is carried out, the thickness of the residual interlayer dielectric layer at the bottom of the initial contact hole is smaller than the initial thickness of the interlayer dielectric layer in the region corresponding to the deep groove, correspondingly, after the contact hole and the deep groove are formed, the interlayer dielectric layer with partial thickness is easy to remain at the bottom of the deep groove, and the possibility of over etching of the interlayer dielectric layers at the bottom and the side wall of the deep groove is lower, so that the bridging probability between a shielding plug and a grid structure or a substrate is reduced, and the performance of a transistor is correspondingly improved; and after etching, the interlayer dielectric layer between the deep groove and the grid structure can be used as a shielding dielectric layer, so that the shielding plug, the grid structure and the interlayer dielectric layer between the deep groove and the grid structure form a capacitor structure, and the shielding plug can play a role in the process.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

FIG. 2 is an electron microscope image corresponding to the semiconductor structure shown in FIG. 1;

fig. 3 to 11 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;

fig. 12 to 14 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

After the electric field shielding structure is introduced into the LDMOS transistor, the performance of the transistor is still to be improved. The reasons for the improvement in performance are now analyzed in connection with a semiconductor structure.

Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.

The semiconductor structure is an LDMOS transistor, comprising: a substrate 10, wherein a well region 20 and a drift region 30 are formed in the substrate 10, the well region 20 has first type doping ions, and the drift region 30 has second type doping ions; a gate structure 40, which is located on the substrate 100 and covers a portion of the well region 20 and a portion of the drift region 30, and includes a gate dielectric layer 41 and a gate layer 42 located on the gate dielectric layer 41; a source region 25 located in the well region 20 at one side of the gate structure 40, wherein the source region 25 has second type doping ions; a drain region 35 located in the drift region 30 on the other side of the gate structure 40 and spaced apart from the gate structure 40 by a lateral distance, the drain region 35 having a second type of dopant ions; a shielding dielectric layer 45 covering a side wall and a part of the top of the side of the gate structure 40 close to the drain region 35; contact hole plugs 51 respectively located on the source region 25 and the drain region 35; a shield plug (shield CT) 52 on the shield dielectric layer 30 on one side of the gate structure 40; and metal layers 53 respectively positioned on the contact hole plugs 51 and the shielding plugs 52.

The shield plug 52, the shield dielectric layer 30 and the gate structure 40 constitute a capacitor, and thus a voltage opposite to the gate structure 40 can be induced, so that hot carriers between the drain region 35 and the gate structure 40 can be absorbed, thereby reducing a spike electric field, improving the voltage resistance of the transistor, improving the resistance to hot carrier injection, and reducing miller capacitance.

An interlayer dielectric layer (not shown) is formed on the substrate 10 exposed by the contact plug 51 and the shield plug 52, the contact plug 51 and the shield plug 52 are usually formed in the same process, and the forming step generally includes: etching the interlayer dielectric layer to form a first contact hole exposing the source region 25 and the drain region 35 and a second contact hole exposing the shielding dielectric layer 45 at one side of the gate structure 40; a contact hole plug 51 in the first contact hole and a shield plug 52 in the second contact hole are formed.

The thickness of the interlayer dielectric layer above the shielding dielectric layer 30 is smaller than the thickness of the interlayer dielectric layer above the source region 25 and the drain region 35, and in the etching process, the shielding dielectric layer 30 is exposed first, but in order to expose the source region 25 and the drain region 35, the interlayer dielectric layer needs to be continuously etched, and in the continuous etching process, the problem that the shielding dielectric layer 30 is easy to be over-etched easily occurs, which easily causes the second contact hole to expose the gate structure 40 or the substrate 10, so that bridging between the shielding plug 52 and the gate structure 40 (as shown by a dotted line circle a1 in fig. 1) and bridging between the shielding plug 52 and the substrate 10 (as shown by a dotted line circle b1 in fig. 2) are caused, thereby reducing the performance of the transistor.

Referring to fig. 2 in combination, the case where the shield plug 52 bridges the gate structure 40 (as indicated by the dashed circle a2 in fig. 2) and the case where the shield plug 52 bridges the substrate 10 (as indicated by the dashed circle b2 in fig. 2) are shown.

In order to solve the technical problems, in the embodiment of the invention, an interlayer dielectric layer with partial thickness is etched firstly, an initial contact hole is formed in the interlayer dielectric layer above a source region and a drain region, then the interlayer dielectric layer at the bottom of the initial contact hole and at one side of a grid structure close to the drain region is etched, and a contact hole exposing the source region and the drain region and a deep groove positioned at one side of the grid structure are formed; because the initial contact hole is formed firstly, the interlayer dielectric layer in the region corresponding to the deep groove is not etched, before the subsequent etching step is carried out, the thickness of the residual interlayer dielectric layer at the bottom of the initial contact hole is smaller than the initial thickness of the interlayer dielectric layer in the region corresponding to the deep groove, correspondingly, after the contact hole and the deep groove are formed, the interlayer dielectric layer with partial thickness is easy to remain at the bottom of the deep groove, and the possibility of over-etching of the interlayer dielectric layers at the bottom and the side wall of the deep groove is lower, so that the bridging probability between a shielding plug and a grid structure or a substrate is reduced, and the performance of a transistor is correspondingly improved; and after etching, the interlayer dielectric layer between the deep groove and the grid structure can be used as a shielding dielectric layer, so that the shielding plug, the grid structure and the shielding dielectric layer between the deep groove and the grid structure form a capacitor structure, and the shielding plug can play a role in the process.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 3 to 11 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 3, a substrate 100 is provided, a well region 110 and a drift region 120 are formed in the substrate 100, a gate structure 200 is formed on the substrate 100, the gate structure 200 covers a portion of the well region 110 and a portion of the drift region 120, an active region 115 is formed in the well region 110 on one side of the gate structure 200, a drain region 125 is formed in the drift region 120 on the other side of the gate structure 200, the drain region 125 and the gate structure 200 are separated by a lateral distance, an interlayer dielectric layer 140 is formed on the substrate 100 exposed by the gate structure 200, and the interlayer dielectric layer 140 covers the source region 115, the drain region 125 and the gate structure 200.

The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures. Specifically, the semiconductor structure is an LDMOS transistor, which may be an N-type transistor or a P-type transistor.

In this embodiment, the base 100 is a silicon substrate. In other embodiments, the material of the base may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the like, and the base 100 may be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.

The well region 110 has first type doping ions, which may be N-type ions or P-type ions. When the LDMOS transistor is an N-type transistor, the first type doped ion is a P-type ion, which may be B, ga or In; when the LDMOS transistor is a P-type transistor, the first type dopant ion is an N-type ion, which may be P, as or Sb.

The drift region 120 is used for bearing larger partial pressure, and the existence of the drift region 120 is beneficial to improving the breakdown voltage between the source region 115 and the drain region 125, reducing the parasitic capacitance between the source region 115 and the drain region 125, and improving the frequency characteristic; and, the drift region 120 serves as a buffer between the channel and drain regions 125, which is beneficial to improve the short channel effect of the LDMOS transistor.

The drift region 120 has second type doping ions, which may be N-type ions or P-type ions, and the second type doping ions are different in type from the first type doping ions. The drift region 120 is a high-resistance layer, so that the concentration of dopant ions in the drift region 120 is small, and the concentration of dopant ions in the drift region 120 is smaller than the concentration of dopant ions in the drain region 125.

Specifically, the substrate 100 in a specific region is doped by using a mask using different ion implantation processes to form the well region 110 and the drift region 120, respectively.

The gate structure 200 includes a gate dielectric layer 210 and a gate layer 220 on the gate dielectric layer 210. In the present embodiment of the present invention,the gate structure 200 is a polysilicon gate structure, the gate dielectric layer 210 is made of silicon oxide, and the gate layer 220 is made of polysilicon. In other embodiments, the gate structure may be a metal gate structure, and the gate dielectric layer may be made of a high-k gate dielectric material, such as HfO ₂ Or Al ₂ O ₃ Etc.; the material of the gate layer 220 is correspondingly metal, and the metal may be copper, aluminum, tungsten, or the like.

In this embodiment, a sidewall 250 is further formed on the sidewall of the gate structure 200. The sidewall 250 protects the sidewall of the gate structure 200 and also serves to define the formation location of the source region 115.

The material of the side wall 250 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride, and the side wall 250 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall 250 has a single-layer structure, and the material is silicon nitride.

The drain region 125 serves as the drain terminal of the LDMOS transistor. In this embodiment, the substrate 100 exposes a top surface of the drain region 125, and the drain region 125 has a second type of dopant ions.

The drain region 125 and the gate structure 200 are spaced apart by a lateral distance to improve the voltage resistance of the LDMOS transistor. Wherein the drain region 125 and the gate structure 200 are separated by a lateral distance means that: the drain region 125 is located at one side of the gate structure 200 and is isolated in a direction perpendicular to the sidewall of the gate structure 200.

The source region 115 serves as the source terminal of the LDMOS transistor. In this embodiment, the substrate 100 exposes the top surface of the source region 115, the doping type of the source region 115 is the same as the doping type of the drain region 125, and the doping ion concentration of the source region 115 is the same as the doping ion concentration of the drain region 125.

Specifically, after the sidewall 250 is formed, the substrate 100 on both sides of the gate structure 200 is doped by using a photomask and an ion implantation process to form the source region 115 and the drain region 125.

In this embodiment, a body contact region 116 is further formed in the well region 110 on the side of the source region 115 away from the gate structure 200, and a sidewall of the body contact region 116 contacts a sidewall of the source region 115. Well region 110 is circumscribed by body contact region 116. The body contact region 116 has a first type of dopant ions, and the body contact region 116 has a dopant ion concentration greater than that of the well region 110, resulting in a lower resistance of the body contact region 116.

Accordingly, the substrate 100 is doped by ion implantation using a photomask to form the body contact region 116. The source region 115 and the drain region 125 may be formed first, followed by forming the body contact region 116, or the body contact region 116 may be formed first, followed by forming the source region 115 and the drain region 125.

The interlayer dielectric layer 140 is used for realizing electrical isolation between adjacent transistors, and the material of the interlayer dielectric layer is an insulating material. In this embodiment, the material of the interlayer dielectric layer 140 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer may be silicon nitride or silicon oxynitride or other dielectric materials.

Before forming the interlayer dielectric layer 140, the method further includes: and forming an etching stop layer 130 covering the substrate 100 and the gate structure 200 in a conformal manner, wherein the etching stop layer 130 is used for defining an etching stop position in a subsequent etching process for forming a contact hole, so that the problem of excessive etching of the substrate 100 is reduced while ensuring that the finally formed contact hole in each region can expose the source region 115 and the drain region 125. Accordingly, the interlayer dielectric layer 140 is formed on the etch stop layer 130.

In this embodiment, the material of the etching stop layer 130 is silicon nitride. The hardness and the compactness are high, and the etching selectivity between the silicon oxide and the silicon nitride is high, so that the etching stop layer 130 can well play a role in defining the etching stop position.

Referring to fig. 4 and 5 in combination, a partial thickness of the interlayer dielectric layer 140 over the source region 115 and the drain region 125 is etched, and an initial contact hole 141 is formed in the interlayer dielectric layer 140 over the source region 115 and the drain region 125.

The initial contact hole 141 is used to provide a process basis for the subsequent formation of contact holes exposing the source region 115 and the drain region 125. The subsequent steps further comprise: the interlayer dielectric layer 140 at the bottom of the initial contact hole 141 and at the side of the gate structure 200 near the drain region 125 is etched to form a contact hole exposing the source region 115 and the drain region 125, and a deep recess at the side of the gate structure 200, the contact hole providing a spatial location for forming a contact hole plug (CT), the deep recess providing a spatial location for forming a shield plug.

Since the initial contact hole 141 is formed first, which is equivalent to that a part of the process of forming the contact hole has already been performed, and at this time, the interlayer dielectric layer 140 in the region corresponding to the deep groove has not been etched yet, therefore, before the subsequent etching step is performed, the thickness of the remaining interlayer dielectric layer 140 at the bottom of the initial contact hole 141 is smaller than the initial thickness of the interlayer dielectric layer 140 in the region corresponding to the deep groove, and accordingly, after the contact hole and the deep groove are finally formed, and under the condition that the depth value of the deep groove meets the process requirement, the interlayer dielectric layer 140 still having a partial thickness at the bottom of the deep groove is liable to remain, and the possibility that the interlayer dielectric layer 140 at the bottom and the side wall of the deep groove is excessively etched is lower, thereby reducing the bridging probability between the shielding plug and the gate structure 200 or the substrate 100 and correspondingly improving the performance of the transistor.

In this embodiment, a dry etching process is used to etch a portion of the interlayer dielectric layer 140 above the source region 115 and the drain region 125. The dry etching process has the characteristic of etching with different etching characteristics, and is favorable for improving the appearance quality of the initial contact hole 141 and easily controlling the etching amount of the interlayer dielectric layer 140 by selecting the dry etching process.

In this embodiment, in the step of etching the interlayer dielectric layer 140 with a partial thickness above the source region 115 and the drain region 125, the interlayer dielectric layer 140 with a partial thickness above the gate structure 200 is also etched, and a shallow recess 142 is formed in the interlayer dielectric layer 140 above the gate structure 200, where a projection of the shallow recess 142 on the gate structure 200 covers a portion of the top and a portion of the substrate 100 on a side of the gate structure 200 near the drain region 125.

The shallow recess 142 is used for communicating with a deep recess formed subsequently, and accordingly, a shielding plug is formed subsequently in the shallow recess 142 and the deep recess, that is, the shielding plug covers a portion of the top and a portion of the sidewall of the gate structure 200 near the side of the drain region 125, and the interlayer dielectric layer 140 is isolated between the shielding plug and the gate structure 200 and between the shielding plug and the substrate 100. By forming the shallow recess 142, the effective area between the shielding plug and the gate structure is increased, and the capacitance density of the capacitor structure is increased under the same condition as the area of the same substrate 100, so as to improve the neutralization effect on hot carriers, and further improve the resistance to hot carrier injection and the voltage-withstanding performance of the transistor.

The projection of the shallow trench 142 on the gate structure 200 covers a portion of the top and a portion of the substrate 100 of the gate structure 200 near the side of the drain region 125, which is advantageous for enabling a deep trench formed later to have a safe distance from the gate structure 200 in a direction perpendicular to the sidewall of the gate structure 200, so as to further reduce the bridging probability between the shielding plug and the gate structure 200.

In this embodiment, the number of the shallow grooves 142 is plural, and the plurality of shallow grooves 142 are arranged along the extending direction of the gate structure 200. By forming a plurality of discrete shallow grooves 142, in the process of etching by adopting a dry etching process, the amount of electric charge generated by etching in each shallow groove 142 can be reduced, so that the problem of electric charge accumulation at the corners of the bottom of each shallow groove 142 is solved, and the possibility of over etching of the interlayer dielectric layer 140 at the bottom and the side wall of each deep groove is further reduced.

Since the shallow recesses 142 serve to increase the effective area between the shield plug and the gate structure 200, even with a solution of forming a plurality of discrete shallow recesses 142, the probability of a total reduction in the effective area is low, which facilitates the capacitance density of the capacitor structure to still meet the performance requirements of the transistor. For example: by reasonably setting the number of the shallow grooves 142, the dimension of each shallow groove 142 along the extending direction of the gate structure 200, the dimension of each shallow groove 142 along the direction perpendicular to the sidewall of the gate structure 200, the depth of the subsequent deep groove, and the like.

In this embodiment, the preset depth H1 of the initial contact hole 141 is determined according to the initial thickness T1 of the interlayer dielectric layer 140 and the total amount of subsequent etching of the interlayer dielectric layer 140. The etching amount of the interlayer dielectric layer 140 at the bottom of the initial contact hole 141 is taken as the etching total amount, and the etching process generally includes a main etching (main etching) step and an over etching (over etching) step, where the etching total amount is the etching amount of the main etching step.

Specifically, the total etching amount is set to be a preset etching amount, and the difference between the initial thickness T1 and the preset depth H1 is greater than the preset etching amount, so as to ensure that the interlayer dielectric layer 140 with a partial thickness remains at the bottom of the deep groove, and reduce the probability of etching damage to the substrate 100 where the source region 115 and the drain region 125 are located.

It should be noted that the preset depth H1 of the initial contact hole 141 is not too small or too large. If the preset depth H1 is too small, after the remaining interlayer dielectric layer 140 at the bottom of the initial contact hole 141 is removed later, the thickness of the remaining interlayer dielectric layer 140 at the bottom of the deep groove is easily too small, so that the possibility of over etching of the interlayer dielectric layer 140 at the bottom and the side wall of the deep groove is increased, and the probability of bridging between the shielding plug and the gate structure 200 or the substrate 100 is increased; if the preset depth H1 is too large, after the remaining interlayer dielectric layer 140 at the bottom of the initial contact hole 141 is removed, the depth of the deep groove may not meet the process requirement, so in order to enable the depth of the deep groove to meet the process requirement, the interlayer dielectric layer 140 needs to be further etched, which correspondingly increases the total time of the etching process, and increases the probability of etching damage to the substrate 100 where the source region 115 and the drain region 125 are located. For this purpose, the predetermined depth H1 of the initial contact hole 141 is

To the point of

It should be further noted that, in the step of forming the initial contact hole 141, the interlayer dielectric layer 140 is further etched to a partial thickness above the gate structure 200, and the preset depth H1 of the initial contact hole 141 is the depth of the shallow trench 142, so that by setting the preset depth H1 of the initial contact hole 141 in the above range, the problem of over etching of the interlayer dielectric layer 140 at the bottom of the shallow trench 142 can be reduced, thereby reducing the probability that the shallow trench 142 exposes the gate structure 200, and further reducing the probability that the subsequently formed shielding plug bridges the gate structure 200.

In addition, the subsequent process further comprises: and forming metal layers respectively positioned on the contact hole plug and the shielding plug. Specifically, the metal layer is a first metal interconnection line (i.e., M1), and the metal layer refers to a layer closest to the contact hole plug in the metal interconnection structure.

In this embodiment, in order to save the mask and reduce the process cost, the same Zhang Guang mask is used to form the initial contact hole 141, the shallow trench 142 and the metal layer. Correspondingly, the metal layer formed later is located on the shielding plug in the corresponding area of the shallow recess 142.

Specifically, the step of forming the initial contact hole 141 and the shallow groove 142 includes: forming a patterned first photoresist layer 300 (shown in fig. 4) on the interlayer dielectric layer 140; etching the interlayer dielectric layer 140 by using the patterned first photoresist layer 300 as a mask; the patterned first photoresist layer 300 is removed.

The patterned first photoresist layer 300 has a first pattern opening 301 formed therein, and the first pattern opening 301 is used to define the formation area of the initial contact hole 141 and the shallow trench 142.

The type of the first photoresist layer 300 may be either positive photoresist or negative photoresist depending on the design of the photomask. The exposed positive photoresist is removed after being developed, and the area corresponding to the first pattern opening 301 in the photomask is a light-transmitting area; the exposed negative photoresist is left after development, and the region of the mask corresponding to the first pattern opening 301 is a light shielding region.

In this embodiment, the subsequent process of forming the metal layer includes a step of patterning the metal material layer by using the patterned second photoresist layer as a mask, where the region corresponding to the first pattern opening 301 is a region to be etched in the interlayer dielectric layer 140, and the region corresponding to the first pattern opening 301 is a region to be reserved in the metal material layer, so that the types of the first photoresist layer 300 and the second photoresist layer are different.

Currently, a positive photoresist is generally used in the semiconductor manufacturing process, i.e., the type of the second photoresist layer is a positive photoresist, and thus, in this embodiment, the type of the first photoresist layer 300 is a negative photoresist.

In other embodiments, when the process of forming the metal layer includes a step of patterning an inter-metal dielectric (inter metal dielectric layer, IMD) layer and a step of forming the metal layer in the patterned IMD layer, the same Zhang Guang mask is used to form the initial contact hole, the shallow recess, and the metal layer, and the types of the first photoresist layer and the second photoresist layer are correspondingly the same.

In other embodiments, the corresponding mask may be manufactured separately for the process of forming the first pattern opening. At this time, when the metal layer is formed on the shielding plug of the shallow trench corresponding region, compared with the scheme using the same photomask, in this embodiment, the patterns of the photomask used for forming the first pattern opening and the photomask used for forming the metal layer are inverted (reverse tone), that is, in the photomask used for forming the first pattern opening, the region corresponding to the first pattern opening is a light-transmitting region, and the region corresponding to the metal layer in the other Zhang Guangzhao is a light-shielding region. However, if the corresponding mask is separately manufactured for the process of forming the first pattern opening, the metal layer is not limited to the mask plug in the corresponding region of the shallow trench.

The post-lithographic pattern dimensions are characterized by post-development inspection (after develop inspection, ADI) critical dimensions (critical dimension, CD), the post-etch pattern dimensions are characterized by post-etch inspection (after etch inspection, AEI) CD, and the photoresist layer is typically depleted during the etching process, and therefore AEICD is typically greater than adid. For this reason, in the present embodiment, in the direction perpendicular to the sidewall of the gate structure 200, the width W (as shown in fig. 5) of the initial contact hole 141 or the shallow trench 142 is smaller than the width of the subsequent metal layer, so as to reduce the possibility that the initial contact hole 141 and the shallow trench 142 have an oversized width, thereby reducing the risk of bridging between the subsequent contact hole plug and the shielding plug.

The difference between the width of the metal layer and the width W of the corresponding initial contact hole 141 or shallow trench 142 is not too small nor too large. If the difference is too small, the effect of reducing the bridging risk is poor; if the difference is too large, not only is the contact area of the contact plug with the substrate 100 in the region where the source region 115 and the body contact region 116 are located too small, resulting in an increase in contact resistance, but also the possibility that the contact plug cannot be electrically connected to the source region 115 and the body contact region 116 at the same time is increased, and in addition, the shallow recess 142 cannot be connected to a deep recess formed later is also easily caused. For this reason, in the present embodiment, the difference between the width of the metal layer and the width W of the corresponding initial contact hole 141 or shallow groove 142 is 10nm to 20nm, i.e., the width W of the initial contact hole 141 or shallow groove 142 is 10nm to 20nm smaller than the width of the corresponding metal layer.

Wherein, by adjusting the parameters of the photolithography process to adjust the width of the first pattern opening 301, the widths W of the initial contact hole 141 and the shallow trench 142 are easily reduced. For example: the exposure energy can be adjusted.

Referring to fig. 6 and 7 in combination, the bottom of the initial contact hole 141 (as shown in fig. 5) and the interlayer dielectric layer 140 of the gate structure 200 near the side of the drain region 125 are etched to form a contact hole 144 (as shown in fig. 7) exposing the source region 115 and the drain region 125, and a deep recess 145 at the side of the gate structure 200, wherein the bottom of the deep recess 145 is located in the interlayer dielectric layer 140, and the bottom of the deep recess 145 is lower than the top of the gate structure 200.

The deep recess 145 is used to provide a spatial location for the subsequent formation of a shield plug. In this embodiment, the bottom of the initial contact hole 141 (as shown in fig. 5) and the interlayer dielectric layer 140 on the side of the gate structure 200 near the drain region 125 are etched in the same step.

As shown in fig. 5, before the etching step, the thickness of the remaining interlayer dielectric layer 140 at the bottom of the initial contact hole 141 is smaller than the initial thickness T1 of the interlayer dielectric layer 140 in the region corresponding to the deep trench 145 (as shown in fig. 5), so that after the contact hole 144 and the deep trench 145 are finally formed, and the depth H2 of the deep trench 145 meets the process requirement, the possibility of over etching the interlayer dielectric layer 140 at the bottom and the sidewall of the deep trench 145 is lower, so that the bridging probability between the subsequent shielding plug and the gate structure 200 or the substrate 100 is reduced, and the performance of the transistor is correspondingly improved.

In addition, the interlayer dielectric layer 140 between the deep recess 145 and the gate structure 200 may be used as a shielding dielectric layer, so that the subsequently formed shielding plug, the gate structure 200 and the interlayer dielectric layer 140 therebetween form a capacitor structure, thereby implementing the field plate effect of the shielding plug, and accordingly omitting the step of forming the shielding dielectric layer, which is beneficial to improving the manufacturing efficiency or reducing the influence on the manufacturing efficiency.

In this embodiment, in the step of forming the deep groove 145, the interlayer dielectric layer 140 on the side of the shallow groove 142 close to the drain region 125 is etched, so as to form the deep groove 145 communicating with the shallow groove 142.

Specifically, the step of forming the contact 144 and the deep recess 145 includes: forming a patterned third photoresist layer 310 (as shown in fig. 6) on the interlayer dielectric layer 140, wherein the third photoresist layer 310 is filled in the shallow trench 142 (as shown in fig. 5), a second pattern opening 312 is formed in the third photoresist layer 310, and the second pattern opening 312 exposes the initial contact hole 141 (as shown in fig. 5) and the interlayer dielectric layer 140 on the side of the shallow trench 142 close to the drain region 125; etching the interlayer dielectric layer and the etching stop layer 130 by using the third photoresist layer 310 as a mask, to form a contact hole 144 penetrating the interlayer dielectric layer 140 and the etching stop layer 130 and exposing the source region 115 and the drain region 125, and a deep groove 145 located in the interlayer dielectric layer 140 and communicating with the shallow groove 142; the third photoresist layer 310 is removed.

The substrate 100 is formed with the etching stop layer 130, so that the remaining interlayer dielectric layer 140 in each region exposes the etching stop layer 130 above the source region 115 and the drain region 125, and after the depth H2 of the deep groove 145 meets the process requirement, the etching stop layer 130 is etched to form the contact hole 144 penetrating the interlayer dielectric layer 140 and the etching stop layer 130 and exposing the source region 115 and the drain region 125.

In this case, the third photoresist layer 310 is generally worn out during the etching process, that is, the second pattern opening 312 is gradually enlarged, so that the deep groove 145 is easily communicated with the shallow groove 142 after the deep groove 145 is formed by etching. In this embodiment, in order to easily enable the deep groove 145 to communicate with the shallow groove 142, the sidewall of the second pattern opening 312 corresponding to the deep groove 145 is flush with the top boundary of the shallow groove 142 on the side close to the drain region 125.

In this embodiment, the dry etching process is used to perform the etching step, so as to improve the morphology quality of the contact hole 144 and the deep groove 145.

In this embodiment, the number of the shallow grooves 142 is plural, and the plurality of shallow grooves 142 are arranged along the extending direction of the gate structure 200, so the number of the deep grooves 145 is also plural, and the deep grooves 145 are in one-to-one correspondence with the shallow grooves 142.

In this embodiment, the sidewalls of the source region 115 and the body contact region 116 are contacted, so that the contact hole 144 on one side of the gate structure 200 exposes both the source region 115 and the body contact region 116, thereby electrically connecting the source region 115 and the body contact region 116 to an external circuit through the same contact hole plug, and reducing the complexity and the process window of the process for forming the contact hole.

Referring to fig. 8 to 9 in combination, the contact hole 144 (shown in fig. 7) and the deep recess 145 (shown in fig. 7) are filled with a conductive material 305 to form a contact hole plug 410 located in the contact hole 144 and a shield plug 420 located in the deep recess 145.

The contact hole plugs 410 are used to electrically connect the source region 115, the body contact region 116, and the drain region 125 to an external circuit.

The shielding plug 420 is an electric field shielding structure, and the shielding plug 420, the gate structure 200 and the interlayer dielectric layer 140 between them form a capacitor structure, which plays roles of inhibiting hot carrier injection and improving the voltage resistance of the transistor.

In this embodiment, the deep recess 145 and the shallow recess 142 (as shown in fig. 7) are connected, so in the step of filling the contact hole 144 and the deep recess 145 with the conductive material 305, the conductive material 305 is further filled in the shallow recess 144 to form a shielding plug 420 located in the shallow recess 142 and the deep recess 145, the shielding plug 420 covers a portion of the top and a portion of the sidewall of the gate structure 200 near the drain region 125, an interlayer dielectric layer 140 is isolated between the shielding plug 420 and the gate structure 200, and an interlayer dielectric layer 140 is isolated between the shielding plug 420 and the substrate 100.

Compared with the scheme of sequentially forming a part of top and side wall of the conformal covering gate structure close to one side of the drain region and a part of shielding dielectric layer (such as a silicon-rich silicon oxide layer) of the substrate and a shielding layer of the conformal covering shielding dielectric layer, the method of etching the interlayer dielectric layer 140 and filling the conductive material 305 is adopted, so that the problem that the shielding plug 420 breaks or forms a cavity at the corner is avoided, the formation quality of the shielding plug 420 is improved, the performance of the shielding plug 420 is guaranteed, and the performance of a device is improved.

Specifically, the step of forming the contact hole plug 410 and the shield plug 420 includes: filling conductive material 305 in the contact hole 144, the shallow groove 142 and the deep groove 145, wherein the conductive material 305 also covers the top of the interlayer dielectric layer 140; and flattening the conductive material 305 to remove the conductive material 305 higher than the top of the interlayer dielectric layer 140, wherein the remaining conductive material 305 in the contact hole 144 is used as the contact hole plug 410, and the remaining conductive material 305 in the shallow groove 142 and the deep groove 145 is used as the shielding plug 420.

In this embodiment, the conductive material 305 is W. In other embodiments, the conductive material may also be Al, cu, ag, or Au.

Before filling the conductive material 305, the method further includes: etching the interlayer dielectric layer 140 on the top of the gate structure 200 to form another contact hole exposing the top of a part of the gate structure 200; accordingly, the conductive material 305 is also filled in the other contact hole on top of the gate structure 200, thereby forming a gate plug electrically connected to the gate structure 200.

Specifically, another contact hole exposing the top of the gate structure 200 is formed by a separately fabricated mask. The forming process is the same as the existing process, and for convenience of illustration, the embodiment will not be repeated.

Referring to fig. 10 and 11 in combination, after forming the contact hole plug 410 and the shielding plug 420, the method further includes: a metal layer 430 is formed on the contact plugs 410 and on the shield plugs 420 in the areas corresponding to the shallow recesses 142 (as shown in fig. 11).

Specifically, the step of forming the metal layer 430 includes: forming a metal material layer 405 (as shown in fig. 10), wherein the metal material layer 405 also covers the top of the interlayer dielectric layer 140; forming a patterned second photoresist layer 320 on the metal material layer 405; etching the metal material layer 405 with the patterned second photoresist layer 320 as a mask, and using the remaining metal material layer 405 protruding from the interlayer dielectric layer 140 as the metal layer 430; the patterned second photoresist layer 320 is removed.

In this embodiment, the same Zhang Guang cap is used to form the initial contact hole 141 (as shown in fig. 5), the shallow trench 142 (as shown in fig. 5), and the metal layer 430, so that the second photoresist layer 320 is different from the first photoresist layer 300 in type. In this embodiment, the second photoresist layer 320 is a positive photoresist.

The metal layer 430 is formed by patterning the metal material layer 405, so the material of the metal material layer 405 is a metal material that is easy to implement patterning. In this embodiment, the material of the metal material layer 405 is Al. In other embodiments, the material of the metal material layer may be W, cu, ag or Au according to the type of the back-end process and the process requirements.

In this embodiment, the metal material layer 405 is formed by a physical vapor deposition process.

The present embodiment is the same as the previous embodiment, and will not be described again here. This embodiment differs from the previous embodiments in that: the contact hole plug 410a, the shield plug 420a, and the metal layer 430a are formed in the same step. By forming the contact hole plug 410a, the shield plug 420a, and the metal layer 430a in the same step, the process steps are simplified and the manufacturing efficiency is improved.

As shown in fig. 12, a contact hole 144a, a shallow recess 142a, and a deep recess 145a are formed in the interlayer dielectric layer 140 a. The steps of forming the contact hole 144a, the shallow groove 142a and the deep groove 145a are the same as those of the previous embodiment, and will not be repeated here.

Referring to fig. 13, a metal material layer 405a is formed in the contact hole 144a, the shallow recess 142a, and the deep recess 145a, and the metal material layer 405a also covers the top of the interlayer dielectric layer 140 a.

The shield plug, the contact hole plug and the metal layer are then formed by patterning the metal material layer 405a. Therefore, the material of the metal material layer 405a is a metal material that is easy to pattern. In this embodiment, the material of the metal material layer 405a is Al.

The metal material layer 405a not only covers the top of the interlayer dielectric layer 140a, but also fills the contact hole 144a and the shallow recess 142a, so that a process mode with better filling performance is adopted to form the metal material layer 405a.

In this embodiment, a thermal physical vapor deposition (thermal physical vapor deposition) process is used to deposit a metal material, so as to form the metal material layer 405a. The thermal physical vapor deposition process has a process temperature greater than that of the conventional physical vapor deposition process and a process temperature greater than 360 ℃, which allows the metal material to have better fluidity, thereby improving the formation quality of the metal material layer 405a.

After forming the metal material layer 405a, the method further includes: a patterned photoresist layer 320a is formed on the metal material layer 405a, the patterned photoresist layer 320a covering the metal material layer 405a over the contact holes 144a and over the shallow recesses 142 a. The patterned photoresist layer 320a is used as a mask for the subsequent patterned metal material layer 405a.

Referring to fig. 14, the patterned photoresist layer 320a is used as a mask, and the top of the interlayer dielectric layer 140a is used as a stop position, the metal material layer 405a is etched, the remaining metal material layer 405a in the contact hole 144a is used as the contact hole plug, the remaining metal material layer 405a in the shallow recess 142a and the deep recess 145a is used as the shielding plug 420a, and the remaining metal material layer 405a protruding from the interlayer dielectric layer 140a is used as the metal layer 430a.

For a specific description of the forming method in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated.

Correspondingly, the embodiment of the invention also provides a semiconductor structure. With continued reference to fig. 11, a schematic structural diagram of one embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100, wherein a well region 110 and a drift region 120 are formed in the substrate 100; a gate structure 200 on the substrate 100, the gate structure 200 covering a portion of the well region 110 and a portion of the drift region 120; a source region 115 located in the well region 110 at one side of the gate structure 200; a drain region 125 located in the drift region 120 at the other side of the gate structure 200 and spaced apart from the gate structure 200 by a lateral distance; an interlayer dielectric layer 140 located on the substrate 100 exposed by the gate structure 200, wherein the interlayer dielectric layer 140 covers the gate structure 200; contact plugs 410 located in the interlayer dielectric layer 140 at both sides of the gate structure 200 and electrically connecting the source region 115 and the drain region 125; and a shielding plug 420 located in the interlayer dielectric layer 140 and at least located at one side of the gate structure 200 near the drain region 125, wherein the bottom of the shielding plug 420 is located in the interlayer dielectric layer 140, and the bottom of the shielding plug 420 located at one side of the gate structure 200 is lower than the top of the gate structure 200.

The process of forming the contact plug 410 and the shield plug 420 includes: etching the interlayer dielectric layer 140 to form contacts exposing the source region 115 and the drain region 125 and deep grooves in the interlayer dielectric layer 140; conductive material is filled in the contact hole and the deep groove to form a contact hole plug 410 and a shield plug 420, respectively. Because the bottom of the shielding plug 420 is located in the interlayer dielectric layer 140, the contact hole and the deep groove are not completely formed in the same etching step, which is easy to enable the bottom of the shielding plug 420 to still have a part of the thickness of the interlayer dielectric layer 140, thereby reducing the bridging probability between the shielding plug 420 and the gate structure 200 or the substrate 100, and correspondingly improving the performance of the transistor; in addition, the interlayer dielectric layer 140 between the shielding plug 420 and the gate structure 200 may be used as a shielding dielectric layer, so that the shielding plug 420, the gate structure 200 and the interlayer dielectric layer 140 therebetween form a capacitor structure, so as to ensure that the shielding plug 420 can play a role in its intended purpose.

The semiconductor structure is an LDMOS transistor, and the LDMOS transistor can be an N-type transistor or a P-type transistor.

The well region 110 has first type doped ions, and when the LDMOS transistor is an N-type transistor, the first type doped ions are P-type ions; when the LDMOS transistor is a P-type transistor, the first type of dopant ions are N-type ions. The drift region 120 has a second type of dopant ions, and the first type of dopant ions and the second type of dopant ions are of different types.

The gate structure 200 includes a gate dielectric layer 210 and a gate layer 220 on the gate dielectric layer 210. In this embodiment, the gate structure 200 is a polysilicon gate structure, the material of the gate dielectric layer 210 is silicon oxide, and the material of the gate layer 220 is polysilicon. In other embodiments, the gate structure may also be a metal gate structure, and the material of the gate dielectric layer may be a high-k gate dielectric material correspondingly; the material of the gate layer is correspondingly metal.

A sidewall 250 is further formed on the sidewall of the gate structure 200, for protecting the sidewall of the gate structure 200, and for defining the positions of the drain region 125 and the source region 115. In this embodiment, the sidewall 250 has a single-layer structure, and the material is silicon nitride.

The drain region 125 is used as a drain terminal of the LDMOS transistor, and the drain region 125 and the gate structure 200 are separated by a lateral distance to improve the voltage resistance of the LDMOS transistor; the source region 115 serves as the source terminal of the LDMOS transistor. In this embodiment, the drain region 125 and the source region 115 each have a second type of dopant ions, and the dopant ion concentration of the source region 115 is the same as the dopant ion concentration of the drain region 125.

In this embodiment, a body contact region 116 is further formed in the well region 110 on the side of the source region 115 away from the gate structure 200, and a sidewall of the body contact region 116 contacts a sidewall of the source region 115. Body contact region 116 has a first type of dopant ions.

The semiconductor structure further includes: an etch stop layer 130 is positioned between the interlayer dielectric layer 140 and the substrate 100, and between the interlayer dielectric layer 140 and the gate structure 200. The process of forming the contact plug 410 includes a step of etching the interlayer dielectric layer 140, and the etch stop layer 130 is used to define a position of an etch stop in the etching process. In this embodiment, the material of the etching stop layer 130 is silicon nitride.

The contact hole plugs 410 are used to electrically connect the source region 115, the body contact region 116, and the drain region 125 to an external circuit. The shield plug 420, the gate structure 200 and the interlayer dielectric layer 140 therebetween form a capacitor structure, which serves to suppress hot carrier injection and to improve the voltage resistance of the transistor.

The material of the contact hole plug 410 may be W, al, cu, ag or Au, and the material of the shield plug 420 may be W, al, cu, ag or Au. In this embodiment, the shielding plug 420 and the contact hole plug 410 are made of the same material, and the shielding plug 420 and the contact hole plug 410 are made of W.

In this embodiment, the shielding plug 420 covers a portion of the top and a portion of the sidewall of the gate structure 200 near the side of the drain region 125, and an interlayer dielectric layer 140 is isolated between the shielding plug 420 and the gate structure 200 and between the shielding plug and the substrate 100. By having the shield plug 420 also located within the interlayer dielectric layer 140 above the gate structure 200, the effective area between the shield plug 420 and the gate structure 200 is increased, and correspondingly the capacitance density of the capacitor structure is increased, thereby further improving the resistance to hot carrier injection and the withstand voltage performance of the transistor.

In this embodiment, the number of the shielding plugs 420 is plural, and the plural shielding plugs 420 are arranged along the extending direction of the gate structure 200. The process of forming the shield plug 420 generally includes a step of etching the interlayer dielectric layer 140 to form a deep recess on one side of the gate structure 200 and a shallow recess on the upper side of the gate structure 200, and in order to improve the quality of the etched profile, a dry etching process is generally selected to etch, so that the number of the shield plugs 420 is increased, which is beneficial to improving the charge accumulation problem at the corners of the bottoms of the shallow recess and the deep recess, thereby reducing the possibility of over-etching of the interlayer dielectric layer 140 at the bottoms or sidewalls of the shallow recess and the deep recess, and further reducing the bridging probability between the shield plug 420 and the gate structure 200.

The semiconductor structure further includes: the metal layer 430 covers the contact plugs 410 and the shield plugs 420 over the gate structure 200, respectively. Specifically, the metal layer 430 is a first metal interconnect line.

As can be seen from the foregoing analysis, the process of forming the shielding plug 420 generally includes the step of etching the interlayer dielectric layer 140 to form a deep recess on one side of the gate structure 200 and a shallow recess on the top of the gate structure 200, and the metal layer 430 covers the shielding plug 420 on the top of the gate structure 200, so that the same Zhang Guangzhao is used for the process of forming the shallow recess and the process of forming the metal layer 430, thereby reducing the process cost.

In this embodiment, the material of the metal layer 430 is Al. In other embodiments, the material of the metal layer may be W, cu, ag or Au according to the type of the back-end process and the process requirements.

In other embodiments, the contact plug, shield plug, and metal layer may also be a unitary structure. For process feasibility, the material of the metal layer is correspondingly a metal material which is easy to pattern. For example: al.

It should be noted that the semiconductor structure further includes: a gate plug (not shown) is located in the interlayer dielectric layer 140 over the top of the portion of the gate structure 200 and electrically connects the gate structure 200. For ease of illustration, the gate plug is not illustrated in this embodiment.

The semiconductor structure of this embodiment may be formed by the forming method described in the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a well region and a drift region are formed in the substrate, a gate structure is formed on the substrate, the gate structure covers part of the well region and part of the drift region, an active region is formed in the well region at one side of the gate structure, a drain region is formed in the drift region at the other side of the gate structure, the drain region and the gate structure are separated by a transverse distance, an interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the interlayer dielectric layer covers the source region, the drain region and the gate structure;

Etching a part of thickness interlayer dielectric layer above the source region and the drain region, and forming an initial contact hole in the interlayer dielectric layer;

etching the bottom of the initial contact hole and an interlayer dielectric layer on one side of the grid structure, which is close to the drain region, to form a contact hole exposing the source region and the drain region, and a deep groove on one side of the grid structure, wherein the bottom of the deep groove is positioned in the interlayer dielectric layer, and the bottom of the deep groove is lower than the top of the grid structure;

and filling conductive materials in the contact hole and the deep groove to form a contact hole plug positioned in the contact hole and a shielding plug positioned in the deep groove.

2. The method of forming a semiconductor structure of claim 1, wherein in the step of etching a portion of the thickness interlayer dielectric layer over the source and drain regions, a portion of the thickness interlayer dielectric layer over the gate structure is also etched, a shallow recess is formed in the interlayer dielectric layer, and a projection of the shallow recess onto the gate structure covers a portion of the top and a portion of the substrate of the gate structure on a side adjacent to the drain region;

the step of forming the deep groove includes: etching an interlayer dielectric layer on one side of the shallow groove close to the drain region to form the deep groove communicated with the shallow groove;

In the step of filling the contact hole and the deep groove with conductive material, the conductive material is also filled in the shallow groove to form the shielding plug in the shallow groove and the deep groove.

3. The method of forming a semiconductor structure of claim 2, wherein the number of shallow recesses is a plurality, and the plurality of shallow recesses are aligned along an extension direction of the gate structure;

in the step of forming the deep grooves, the deep grooves are in one-to-one correspondence with the shallow grooves.

4. The method of forming a semiconductor structure of claim 2, wherein the method of forming further comprises: and forming a metal layer on the contact hole plug and the shielding plug of the area corresponding to the shallow groove, and forming the initial contact hole, the shallow groove and the metal layer by adopting the same Zhang Guang cover.

5. The method of forming a semiconductor structure of claim 4, wherein forming the initial contact hole and shallow trench comprises: forming a patterned first photoresist layer on the interlayer dielectric layer; etching the interlayer dielectric layer by taking the patterned first photoresist layer as a mask; removing the patterned first photoresist layer;

The step of forming the metal layer includes: forming a metal material layer which also covers the top of the interlayer dielectric layer; forming a patterned second photoresist layer on the metal material layer; etching the metal material layer by taking the patterned second photoresist layer as a mask, wherein the residual metal material layer protruding out of the interlayer dielectric layer is used as the metal layer; removing the patterned second photoresist layer;

the type of the first photoresist layer is positive photoresist or negative photoresist, the type of the second photoresist layer is positive photoresist or negative photoresist, and the types of the first photoresist layer and the second photoresist layer are different.

6. The method of forming a semiconductor structure of claim 4, wherein after forming the metal layer, a width of the metal layer is greater than a width of a corresponding initial contact hole or shallow trench in a direction perpendicular to sidewalls of the gate structure.

7. The method of claim 6, wherein the metal layer width is from 10nm to 20nm different from the corresponding initial contact hole or shallow trench width.

8. The method of forming a semiconductor structure of claim 4, wherein the metal layer is formed after the contact plug and shield plug are formed;

Alternatively, the contact hole plug, the shield plug, and the metal layer are formed in the same step.

9. The method of forming a semiconductor structure of claim 4, wherein forming the contact plug, shield plug and metal layer in the same step comprises:

filling a metal material layer in the contact hole, the shallow groove and the deep groove, wherein the metal material layer also covers the top of the interlayer dielectric layer;

and etching the metal material layer by taking the top of the interlayer dielectric layer as a stop position, taking the residual metal material layer in the contact hole as the contact hole plug, taking the residual metal material layers in the shallow groove and the deep groove as the shielding plug, and taking the residual metal material layer protruding out of the interlayer dielectric layer as the metal layer.

10. The method of claim 9, wherein the metal material layer is formed by depositing a metal material using a thermal physical vapor deposition process having a process temperature greater than 360 ℃.

11. The method of forming a semiconductor structure of claim 1, wherein the step of forming the contact plug and shield plug comprises: filling conductive materials in the contact holes and the deep grooves, wherein the conductive materials also cover the top of the interlayer dielectric layer;

And flattening the conductive material, removing the conductive material higher than the top of the interlayer dielectric layer, wherein the residual conductive material in the contact hole is used as the contact hole plug, and the residual conductive material in the deep groove is used as the shielding plug.

12. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the interlayer dielectric layer, the interlayer dielectric layer has an initial thickness;

in the step of forming the initial contact hole, the initial contact hole has a preset depth;

in the step of etching the interlayer dielectric layer at the bottom of the initial contact hole and at one side of the grid structure close to the drain region, the total etching amount of the interlayer dielectric layer is a preset etching amount;

the difference between the initial thickness and the preset depth is larger than the preset etching amount.

13. The method of forming a semiconductor structure according to claim 1, wherein the predetermined depth of the initial contact hole is

To->

14. The method of forming a semiconductor structure of claim 1, wherein a dry etching process is used to etch a portion of the thickness of the interlayer dielectric layer over the source and drain regions.

15. A semiconductor structure, comprising:

the substrate is internally provided with a well region and a drift region;

a gate structure on the substrate, the gate structure covering a portion of the well region and a portion of the drift region;

the source region is positioned in the well region at one side of the grid structure;

the drain region is positioned in the drift region at the other side of the gate structure and is separated from the gate structure by a transverse distance;

the interlayer dielectric layer is positioned on the substrate exposed by the gate structure and covers the gate structure;

the contact hole plugs are positioned in the interlayer dielectric layers at two sides of the grid structure and are electrically connected with the source region and the drain region;

the shielding plug is positioned in the interlayer dielectric layer and at least positioned on one side of the gate structure close to the drain region, the bottom of the shielding plug is positioned in the interlayer dielectric layer, and the bottom of the shielding plug positioned on one side of the gate structure is lower than the top of the gate structure.

16. The semiconductor structure of claim 15, wherein the shield plug covers a portion of the top and a portion of the sidewall of the gate structure adjacent to a side of the drain region, and the shield plug is isolated from the gate structure and the substrate by the interlayer dielectric layer.

17. The semiconductor structure of claim 16, wherein the number of shield plugs is a plurality, and the plurality of shield plugs are aligned along an extension direction of the gate structure.

18. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: and the metal layer is used for respectively covering the contact hole plug and the shielding plug above the grid electrode structure.

19. The semiconductor structure of claim 18, wherein the contact plug, shield plug, and metal layer are a unitary structure.

20. The semiconductor structure of claim 15, wherein a material of the shield plug is Al, W, cu, ag or Au.