Nothing Special   »   [go: up one dir, main page]

CN111696875A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

Info

Publication number
CN111696875A
CN111696875A CN201910568918.9A CN201910568918A CN111696875A CN 111696875 A CN111696875 A CN 111696875A CN 201910568918 A CN201910568918 A CN 201910568918A CN 111696875 A CN111696875 A CN 111696875A
Authority
CN
China
Prior art keywords
carboxylic acid
acid gas
furnace
solder bump
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910568918.9A
Other languages
English (en)
Other versions
CN111696875B (zh
Inventor
宫崎力
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of CN111696875A publication Critical patent/CN111696875A/zh
Application granted granted Critical
Publication of CN111696875B publication Critical patent/CN111696875B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/008—Soldering within a furnace
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
    • B23K1/206—Cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/40—Semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7501—Means for cleaning, e.g. brushes, for hydro blasting, for ultrasonic cleaning, for dry ice blasting, using gas-flow, by etching, by applying flux or plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H01L2224/75101—Chamber
    • H01L2224/75102—Vacuum chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75272—Oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81022—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H01L2224/81065—Composition of the atmosphere being reducing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81091—Under pressure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81095—Temperature settings
    • H01L2224/81096—Transient conditions
    • H01L2224/81097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及半导体装置的制造方法。根据一实施方式，将第1半导体元件的焊料凸块与第2半导体元件的第2凸块电极暂时固定而形成层叠体。其次，一边将炉内设为羧酸的还原温度以上且未达焊料凸块的熔融温度的温度，一边将炉内设为第1羧酸气体浓度。然后，一边将炉内的温度升温至熔融温度为止，一边将炉内设为第2羧酸气体浓度。接着，将炉内的温度维持为熔融温度以上的温度，使焊料凸块熔融。第2羧酸气体浓度是低于第1羧酸气体浓度，且包含能够将焊料凸块的氧化膜还原的最低限度的羧酸气体的浓度。当炉内的温度达到熔融温度时，至少炉内具有第2羧酸气体浓度。

Description

半导体装置的制造方法
相关申请引用
本申请以2019年3月15日先行申请的日本专利申请第2019-048423号的优先权的利益为基础，且要求其利益，通过引用的方式包含该申请的全部内容。
技术领域
此处说明的多种实施方式均涉及半导体装置的制造方法。
背景技术
已知有一种半导体装置，层叠多个半导体芯片，利用凸块将层叠的半导体芯片的凸块电极间电连接。凸块理想为具有稳定的连接形状，且凸块与凸块电极之间的接触界面的氧化膜被除去。
发明内容
本发明的一个实施方式提供一种半导体装置的制造方法，在层叠的半导体元件的凸块电极间具有稳定的连接形状，且能够除去与凸块电极的接触界面的氧化膜。
根据本发明的一个实施方式，半导体装置的制造方法包含层叠体形成工序、排气工序、氧化膜除去工序、还原性气体浓度降低工序、及熔融工序。在所述层叠体形成工序中，将具有第1凸块电极及配置于所述第1凸块电极上的焊料凸块的第1半导体元件、具有第2凸块电极的第2半导体元件，通过暂时固定所述焊料凸块与所述第2凸块电极而层叠，从而形成层叠体。在所述排气工序中，将配置有所述层叠体的炉内排气。在所述氧化膜除去工序中，一边将所述炉内的温度设为显现羧酸还原作用的还原温度以上且未达所述焊料凸块熔融的熔融温度的温度，一边以所述炉内变成第1羧酸气体浓度的方式，向所述炉内导入包含羧酸气体与惰性气体的还原性气体，将所述焊料凸块表面的氧化膜除去。在所述还原性气体浓度降低工序中，一边将所述炉内的温度升温至所述熔融温度为止，一边将所述炉内的羧酸气体的浓度降低至第2羧酸气体浓度为止。在所述熔融工序中，将所述炉内的温度维持为所述熔融温度以上的温度，使所述焊料凸块熔融，从而将所述焊料凸块与所述第2凸块电极连接。所述第2羧酸气体浓度是低于所述第1羧酸气体浓度，且包含能够使咬入所述焊料凸块与所述第2凸块电极之间的所述焊料凸块的氧化膜还原的最低限度的羧酸气体的浓度。在所述熔融工序的开始时间点，至少所述炉内具有所述第2羧酸气体浓度。
根据所述构成，可提供一种半导体装置的制造方法，在层叠的半导体元件的凸块电极间具有稳定的连接形状，且能够将与凸块电极的接触界面的氧化膜除去。
附图说明
图1(a)～(c)是示意性表示第1实施方式的半导体装置的制造方法的顺序的一例的剖视图。
图2(a)～(c)是示意性表示第1实施方式的半导体装置的制造方法中的焊料凸块附近的状况的剖视图。
图3是示意性表示焊料凸块连接时的状况的图。
图4是示意性表示还原回流焊处理装置的构成的一例的图。
图5是表示第1实施方式的还原回流焊处理的条件的一例的图。
图6是表示第2实施方式的还原回流焊处理的条件的一例的图。
具体实施方式
以下参照附图详细地说明实施方式的半导体装置的制造方法。另外，本发明并非由这些实施方式限定。在附图中，相同符号表示相同或相似部分。此外，以下实施方式中使用的半导体装置的剖视图是示意图，层的厚度与宽度的关系、各层的厚度的比率等有时候与实物并不相同。
(第1实施方式)图1是表示第1实施方式的半导体装置的制造方法的顺序的一例的剖视图。图2是示意性表示第1实施方式的半导体装置的制造方法的焊料凸块附近的状况的剖视图。图3是示意性表示焊料凸块连接时的状况的图。图2及图3中，表示将半导体芯片10与半导体芯片20-1之间的凸块电极11、21间放大后的图。
如图1(a)所示，在半导体装置的制造中，要准备多个半导体元件即半导体芯片10、20-1～20-N(N为任意的自然数)。于此，准备半导体芯片10、及多个半导体芯片20-1～20-N(另外，以下不需要区分各个半导体芯片20-1～20-N时，表述为半导体芯片20)。半导体芯片10在作为其中一面的上表面具有凸块电极11。半导体芯片20在作为其中一面的下表面具有凸块电极21、及连接于凸块电极21上的焊料凸块22，在作为另一面的上表面具有凸块电极23。
各凸块电极11、21、23是成为将2个半导体芯片10、20间电连接及机械连接的连接部的电极。凸块电极11在半导体芯片10的上表面的特定区域内排列成例如矩阵状。凸块电极21、23分别在半导体芯片20的下表面及上表面的特定区域内排列成例如矩阵状。本例中，各凸块电极11、21、23具有平坦的焊垫形状。各凸块电极包含使用Cu、Au、Ni、Pd等金属单体的金属膜或将这些金属层叠多层而成的复合膜、或者这些金属的合金膜。
如图2(a)所示，在各凸块电极11、21、23的侧面，存在凸块电极11、21、23的表面被氧化的氧化膜31。凸块电极11、21的侧面存在的氧化膜31具有如下功能：在焊料凸块22的熔融时，使熔融的焊料不向凸块电极11、21的侧面润湿扩散。若凸块电极11、21、23的侧面不存在氧化膜31，则如图3所示，在焊料凸块22熔融时，熔融的焊料会向凸块电极11、21的侧面润湿扩散。即，焊料向凸块电极11、21的侧面流回，结果得到的焊料凸块22具有在高度方向的中央附近凹陷的形状。此外，像这样向凸块电极11、21的侧面流回的焊料21a有可能与在平行于凸块电极11、21的配置面的方向邻接的凸块电极11、21或焊料凸块22短路。因此，熔融焊料凸块22时，需要使凸块电极11、21、23的侧面的氧化膜31不被除去。
焊料凸块22在半导体芯片20的下表面的凸块电极21上与凸块电极21同样地配置成例如矩阵状。焊料凸块22例如以镀覆法形成、或者使用由焊料合金形成的微小球形成。焊料凸块22包含例如Sn、Ag、Cu、Au、Bi、Zn、In等单体金属或这些金属的复合物、或者这些金属的合金。刚形成于凸块电极21上之后的焊料凸块22的表面并不存在氧化膜，但随着时间经过，如图2(a)所示，焊料凸块22的表面氧化，形成氧化膜32。形成于焊料凸块22的表面的氧化膜32在连接焊料凸块22与凸块电极11、23时成为焊料凸块22与凸块电极11、23之间的电阻增大、或者焊料凸块22与凸块电极11、23之间发生连接不良的主要原因。因此，要求在熔融焊料凸块22之前，尽可能地除去焊料凸块22的表面的氧化膜32。
半导体芯片10及半导体芯片20例如是硅(Si)芯片等，但也可以至少一方为Si插入式衬底。即，第1半导体元件与第2半导体元件的组合并无特别限定，除了半导体芯片10与半导体芯片20的组合以外，还有Si插入式衬底与半导体芯片10、20的组合、半导体芯片10、20与Si插入式衬底的组合等。
其次，如图1(b)所示，在支持衬底40上搭载半导体芯片10。然后，以半导体芯片10的凸块电极11与半导体芯片20-1的焊料凸块22重叠的方式进行对准后，在半导体芯片10上层叠半导体芯片20。此时，将凸块电极11与焊料凸块22暂时固定。暂时固定只要能获得在下一工序中实施氧化膜除去时上下半导体芯片10、20-1不脱离的强度即可。凸块电极11与焊料凸块22的暂时固定有以下等方法：一边使用脉冲加热器加热型接合机加热至未达焊料凸块22的融点一边施加荷重而进行固定；或者并用感光性粘结剂或非导电性粘结剂作为未图示的固定材料。另外，支持衬底40例如是引线框架或玻璃环氧衬底。
然后，将半导体芯片20-2的焊料凸块22、与和半导体芯片10暂时固定的半导体芯片20的凸块电极23以相同方法暂时固定。直至半导体芯片20-N暂时固定为止反复进行该动作。由此，获得暂时固定有半导体芯片10～20-N的层叠体50。
其次，对图1(b)中暂时固定的层叠体50进行还原回流焊处理，将焊料凸块22与凸块电极11、23正式接合。上下邻接的半导体芯片10、20的凸块电极11、23与焊料凸块22之间的暂时固定是在焊料凸块22的表面存在氧化膜32的状态下实施的，因此凸块电极11、23与焊料凸块22的接触界面处于咬入有氧化膜32的状态。但，如图2(b)所示，凸块电极11与焊料凸块22为暂时固定的状态，因此凸块电极11与焊料凸块22的接触界面存在间隙G。因此，使羧酸气体接触焊料凸块22的表面存在的氧化膜32而将其除去后，熔融焊料凸块22，本实施方式中进行还原回流焊处理，在存在羧酸气体的气氛下进行该熔融，熔融焊料凸块22时将咬入接触界面的氧化膜32除去。以下，说明该还原回流焊处理。
图4是示意性表示还原回流焊处理装置的构成的一例的图。还原回流焊处理装置100具有加热炉110、排气处理部130、气体导入部150。加热炉110具有可密闭的结构。加热炉110在内部具有保持加工对象且具有加热机构的载物台111。载物台111上可载置例如配置有多个暂时固定的层叠体50的搬送板60。
排气处理部130具备：真空泵132，经由配管131而与加热炉110连接，向外部排出加热炉110内的气体；排气阀133，切换真空泵132的排气接通与断开；及除外装置134，经由配管131而与真空泵132连接，使通过真空泵132排气的气体无害化。
气体导入部150具备：惰性气体贮存部152，经由配管151而与加热炉110连接，贮存惰性气体；及阀153，切换惰性气体向加热炉110的供给的接通与断开。惰性气体贮存部152中贮存氮气等惰性气体。通过该配管151连接的路径用于大气开放的情况，即，使处于内部被排气的状态的加热炉110恢复成大气压。
此外，气体导入部150具备惰性气体贮存部155、还原气体生成部156。惰性气体贮存部155中作为产生羧酸气体时使用的载气使用、且作为调整羧酸气体的浓度的稀释气体使用的惰性气体。作为惰性气体可使用氮气、He气体、Ne气体、Ar气体、Kr气体、Xe气体等惰性气体。图中，分开地设置有惰性气体贮存部152及惰性气体贮存部155，但用于大气开放的惰性气体、与用于还原性气体生成的惰性气体使用相同气体的情况下，也可以将惰性气体贮存部共通化。
连接于惰性气体贮存部155的配管161在中途被分支为稀释气体配管162与载气配管163。稀释气体配管162连接于加热炉110。稀释气体配管162中设置有气体流量控制器157，该气体流量控制器157控制作为导入加热炉110内的稀释气体的惰性气体的流量。载气配管163设置有气体流量控制器158，该气体流量控制器158控制作为导入还原气体生成部156的载气的惰性气体的流量。作为气体流量控制器157、158可使用质量流量控制器等。载气配管163连接于还原气体生成部156。此外，配管161中设置有切换惰性气体的供给的接通与断开的阀165。
还原气体生成部156是收容有羧酸液体1562的密闭容器1561。密闭容器1561连接有载气配管163、以及将包含密闭容器1561内生成的羧酸蒸汽与载气的混合气体导入加热炉110内的混合气体配管164。载气配管163的前端配置在羧酸液体1562中。此外，混合气体配管164的一端以不接触羧酸液体1562的方式设置于密闭容器1561，另一端连接稀释气体配管162。羧酸液体1562在羧酸自身为液体时可以是液体，也可以是按特定浓度含有羧酸的羧酸水溶液。还原气体生成部156具有加热羧酸液体1562的加热部1563。加热部1563例如加热密闭容器1561。通过加热密闭容器1561，在密闭容器1561内产生羧酸蒸汽。混合气体配管164中的混合气体与稀释气体配管162中的稀释气体混合，变成含有特定浓度的羧酸气体的还原性气体，并被供给至加热炉110内。
羧酸气体用于将焊料凸块22的表面存在的氧化膜32还原而除去。作为氧化膜32的还原剂使用的羧酸并无特别限定，例如列举甲酸、乙酸、丙烯酸、丙酸、草酸、琥珀酸、丙二酸等脂肪族的一元或二元的低级羧酸。这些之中，优选使用甲酸，其自身成本及用于气体化的成本低，且氧化膜32的还原作用优异。另外，以下以使用甲酸作为羧酸的代表例的情况为中心进行说明，但作为氧化膜32的还原剂的羧酸并不限定于此。此外，还原气体生成部156的构成是使用起泡方式时的一例，只要能够将羧酸蒸汽供给至加热炉110内，则也可以使用烘烤方式、直接气化方式等其他构成。
于此，对图4所示的还原回流焊处理装置100的第1实施方式的还原回流焊处理进行说明。图5是表示第1实施方式的还原回流焊处理的条件的一例的图。该图中横轴表示时间，左侧的纵轴表示温度，右侧的纵轴表示加热炉110内的压力及羧酸气体的浓度(体积％)。
首先，将搭载于支持衬底40的多个暂时固定的层叠体50配置于搬送板60，并载置于加热炉110(回流焊炉)内的载物台111上。然后，为了使加热炉110内变成减压气氛，实施利用真空泵132将加热炉110内排气的排气处理(步骤S11)。加热时残留于加热炉110内的氧使焊料凸块22氧化，因此优选在从大气压状态(1.01×105Pa)起1×103Pa以下、更理想为5Pa左右的减压状态下将加热炉110内排气。
进行还原处理，向这种减压气氛的加热炉110内导入作为还原性气体的羧酸气体，使焊料凸块22的氧化膜还原(步骤S12)。该还原处理中，以加热炉110内的温度为显现羧酸气体的还原作用的还原温度T1以上、且未达焊料凸块22的融点T2的温度范围的方式，利用载物台111的加热机构进行加热。此外，加热炉110内的压力被维持为特定值，羧酸浓度也被维持为特定值C1。以下，具体地说明该还原处理。
如图4所示，利用加热部1563加热还原气体生成部156的密闭容器1561收容的羧酸水溶液，使密闭容器1561内产生羧酸蒸汽。通过从载气配管163向该状态的密闭容器1561内流入载气，而从混合气体配管164送出由载气与羧酸蒸汽混合而成的混合气体。作为载气使用氮气、He气体、Ne气体、Ar气体、Kr气体、Xe气体等。
由于混合气体配管164连接稀释气体配管162，因此混合气体与稀释气体合流。在稀释气体配管162内流动的惰性气体、混合气体混合而生成羧酸气体浓度得到调整的还原性气体，还原性气体被导入加热炉110内。稀释气体是用于调整羧酸气体的浓度的气体。稀释气体配管162中，为了变成还原加热炉110内的焊料凸块22上存在的氧化膜所需的羧酸的浓度，利用气体流量控制器157调整稀释气体的流量，利用气体流量控制器158构成载气的流量。与载气同样地，稀释气体使用惰性气体。作为稀释气体可使用氮气等，但也可以使用与载气相同的气体。
另外，预先通过实验求出加热炉110内具有特定压力时的加热炉110内的羧酸气体的浓度、气体流量控制器157、158的惰性气体的流量、排气阀133的开度之间的关联信息。然后，向加热炉110内导入还原性气体时，按照该关联信息进行气体流量控制器157、158的惰性气体的流量控制，且利用排气阀133的动作调整加热炉110内的压力，由此控制加热炉110内的羧酸气体的浓度。
即，一直向加热炉110内供给新的还原性气体。此外，加热炉110的气氛压优选设定为比大气压低的状态、例如维持在1.3～8×104Pa的范围内。若加热炉110内的压力过低则有可能因真空隔热引起的加热不足导致焊料凸块22未熔融，处于大气压附近时会导致包含羧酸气体的外部气体被卷入焊料而引起空隙不良。由此，利用还原性气体还原氧化膜32时产生的气体不会滞留，可以向周围释放，从而抑制还原时产生的气体进入焊料凸块22与凸块电极11、23的接合体(连接体)25内的情况。具体的气氛压依赖于羧酸气体的导入量，但理想的是例如2.7×104Pa以下。
在1.3×104Pa以上且8×104Pa以下的减压气氛下，若存在特定存在量(浓度)的羧酸气体，就能将焊料凸块22的表面的氧化膜32还原除去。例如，当加热炉110内的压力为2.7×104Pa的情况下，优选以羧酸气体浓度为0.6体积％～9.2体积％的范围的方式导入还原性气体。若将该羧酸气体浓度换算为例如甲酸的摩尔浓度则为3.19×10-6mol/L～2.87×10-3mol/L的范围。
若还原处理工序中加热炉110内的羧酸气体的浓度过高，则多余的羧酸气体有可能会进入熔融的焊料凸块22内成为空隙。另一方面，若羧酸气体的浓度过低，则无法充分获得利用羧酸气体的氧化膜32的还原作用，有可能导致焊料凸块22的连接不良及电阻值增大等。因此，理想的是所述羧酸气体浓度的范围。
在所述环境下向加热炉110内导入还原性气体后，或者在导入还原性气体的大致同时，利用载物台111的加热机构以特定升温速度(例如20～50℃/分)使加热炉110内升温。此时，将加热炉110内的温度控制为显现羧酸的还原作用的还原温度T1以上、且未达焊料凸块22的融点T2的温度。
使用甲酸作为羧酸的情况下，在150℃以上的温度显现氧化膜32的还原作用。即，甲酸对氧化膜32的还原温度T1约为150℃，若变成150℃以上的温度则氧化膜32还原而被除去。像这样的氧化膜32的还原温度T1以上的温度区域，将焊料凸块22在甲酸气体中暴露例如数分钟，由此可将焊料凸块22的表面存在的氧化膜还原而除去。
但，构成暂时固定的层叠体50的各半导体芯片20上配置的焊料凸块22的数量伴随着凸块尺寸微小化或凸块间距微细化等而超过1000个。还原回流焊处理的对象是这样的具有多个焊料凸块22的半导体芯片20层叠而成的层叠体50，且加热炉110内成批地对多个层叠体50进行还原回流焊处理，因此焊料凸块22的数量有时候超过800,000个。还原开始前这些焊料凸块22的氧化膜32的状态并不相同，因此要将所有焊料凸块22的氧化膜同样地除去，需要足够长的还原处理的时间。
另一方面，若凸块连接所需的焊料凸块22的接合体25以外的凸块电极11、21、23的侧面的氧化膜31被还原，则如图3所示焊料凸块22的焊料向凸块电极11、21、23的侧面润湿扩散，导致接合体25的连接所需的焊料的体积减少。此外，减少还原力而以一定的浓度抑制向凸块电极11、21、23的侧面润湿扩散的方法，使焊料凸块22的还原时间变长，预计会因热历程引起焊料凸块22的连接弊端。该方法中例如以低温进行金属的固相扩散，先形成高熔点的金属化合物，会阻碍焊料凸块22在熔点T2的熔融。
因此，第1实施方式中，对还原处理后的处理进行了研究，以便在还原处理后，能够不使凸块电极11、21、23的侧面的氧化膜31还原地，将焊料凸块22与凸块电极11、23之间未还原而残留的氧化膜32除去。即，在还原处理后的焊料凸块22的熔融处理时，也以加热炉110内存在还原性气体的方式控制加热炉110内的气氛。
在步骤S12的还原处理工序后，实施升温处理，使加热炉110的温度升温至焊料凸块22的熔点(熔融温度)T2以上(步骤S13)。在升温处理中，在羧酸气体的氧化膜的还原温度T1以上且未达焊料凸块22的熔点T2的温度区域，降低羧酸气体的浓度。即，利用气体流量控制器157、158进行控制，增加稀释气体配管162内流动的惰性气体相对于混合气体的流量比率。由此，可降低加热炉110内的羧酸气体浓度。如上所述，并非将加热炉110内的羧酸气体浓度变成0，而是降低至特定值C2。特定值C2是在升温工序结束时间点(下一熔融工序开始时间点)能够将焊料凸块22与凸块电极11、23之间咬入的氧化膜32还原的最低限度的羧酸气体浓度。另外，以加热炉110的气氛压固定、例如为2.7×104Pa的状态的方式控制排气阀17。
在使用甲酸作为羧酸的情况下，例如以15L/分的比率流通例如以还原温度T1以上时甲酸气体浓度为2.8体积％的方式控制含有甲酸气体的混合气体与稀释气体的流量比的还原性气体。然后，当加热炉110的温度达到焊料凸块22的熔点T2时，例如以30L/分的比率流通以甲酸气体浓度为0.6体积％以上的方式控制含有甲酸气体的混合气体与稀释气体的流量比的还原性气体。另外，甲酸气体浓度为一例，还原温度T1以上时理想的是2.8体积％～9.2体积％，且当达到焊料凸块22的熔点T2时理想的是0.6体积％～2.8体积％。由此，阶段性地降低加热炉110内的甲酸气体浓度。该设定中，甲酸气体浓度以-0.7体积％/分减少。但，加热炉110内的整体压力控制为不变化。
然后，将加热炉110的温度维持为焊料凸块22的熔点T2以上，实施熔融焊料凸块22的熔融处理(步骤S14)。在熔融处理的开始时间点，如上所述加热炉110内为能够将焊料凸块22与凸块电极11、23之间咬入的氧化膜32还原的最低限度的羧酸气体浓度。在熔融处理期间，加热炉110内的整体压力也控制为不变化。
根据相对于温度绘制氧化反应的标准反应吉布斯能比的埃林厄姆图，例如使用Sn、Ag、Cu、Au、Bi、Zn、In等或其复合膜、合金等的焊料凸块22是以不易被还原的Sn为主成分的金属。但，依据该方法，通过使用在还原温度T1以上具有还原作用的羧酸气体，而在未达焊料凸块22的熔点T2的低温区域除去氧化膜。另一方面，例如使用Cu、Au、Ni、Pd等单体、复合膜、合金等的凸块电极11、21、23在高温下容易被还原。因此，通过还原处理将焊料凸块22的表面的氧化膜32大致除去后，以降低加热炉110内的羧酸气体浓度的状态，设为焊料凸块22的熔点T2，从而可抑制凸块电极11、21、23的氧化膜31的还原。
此外，根据作为层叠体50暂时固定的图2(b)的状态，未达熔点T2时可能出现羧酸气体渗入凸块电极11与焊料凸块22的接触界面27的间隙G的状态的情况。总之，变成焊料凸块22变形而覆盖凸块电极11、23的状态。焊料凸块22在熔点T2以上熔融而焊料形状变化，羧酸气体能够渗入，因此可继续除去焊料凸块22的氧化膜32。所以，加热炉110内至少在熔融处理的开始时间点为暂时具有还原性的状态。即，加热炉110内的温度达到熔点T2时的羧酸气体的浓度被控制为具有能够除去凸块电极11、23与焊料凸块22之间的氧化膜32的最低限度的浓度，且小于还原温度T1下的羧酸气体的浓度。
另外，在熔融处理的结束时间点，可以具有能够除去氧化膜32的最低限度的羧酸气体的浓度，也可以具有未达最低限度的羧酸气体的浓度。在使用甲酸作为羧酸的情况下，例如达到熔点T2时的羧酸气体浓度只要为0.6体积％以上即可。
通过在这样的加热炉110内的气氛下将温度设为熔点T2以上，凸块电极11、23与焊料凸块22一体化而形成接合体25。此时，在残留凸块电极11、23的氧化膜31的状态下熔融焊料凸块22，因此熔融的焊料不会向凸块电极11、23的侧面润湿扩散，形成能比稳定的焊料凸块22的连接形状。焊料凸块22的稳定的连接形状例如为球形状。其结果，如图2(c)所示，可获得由实现电及机械特性优异的半导体芯片10、20间的连接的层叠体50形成的半导体装置。
然后，实施排气处理(步骤S15)。在排气处理中，停止载物台111的加热机构的加热，且停止还原性气体向加热炉110内的供给，利用真空泵132将加热炉110内排气。
使加热炉110内的温度降温至容易取出层叠体50的温度、例如50℃左右的温度后，实施大气开放处理(步骤S16)。在大气开放处理中，经由配管151从惰性气体贮存部152向加热炉110内导入氮气等惰性气体而使其变成大气压。然后，从加热炉110中取出配置有多个层叠体50的搬送板60。这样，加热炉110内恢复成大气压，可以在降温至容易取出层叠体50的温度后实施，也可以在还原处理结束后，在加热炉110内的温度处于焊料凸块22的熔点T2以上的温度区域的状态下，向加热炉110内一次性导入氮气等惰性气体而恢复成大气压。
将从加热炉110取出的层叠体50与通常的半导体装置同样地送往装配工序。装配工序根据半导体装置而选择，并无特别限定。若叙述其一例，例如在未图示的配线衬底上利用热硬化性树脂粘结层叠体50，将其固化处理而硬化后，利用引线接合等将层叠体50与未图示的衬底之间连接。将这样的结构体树脂模塑后，配置外球而形成半导体装置(半导体封装)的外部连接端子。
在第1实施方式中，在对暂时固定有半导体芯片10、20的凸块电极11、23、与另一半导体芯片20的焊料凸块22的层叠体50进行还原回流焊处理时，以羧酸气体的还原温度T1以上且未达焊料凸块22的熔点T2的温度向加热炉110内导入羧酸气体。然后，在加热炉110内的温度达到焊料凸块22的T2的时间点，变成能够将夹在焊料凸块22与凸块电极11、23之间的焊料凸块22的氧化膜32还原的最低限度的羧酸气体的浓度。由此，在焊料凸块22熔融时，一边抑制凸块电极11、23的侧面存在的氧化膜31的还原，一边进行焊料凸块22上残留的氧化膜32的还原。其结果，凸块电极11、23与凸块电极21之间连接所需的焊料体积不会减少，可形成具有稳定连接形状的焊料凸块22。此外，可对连接面的焊料充分赋予合金层生长所需的加热时间，从而可增加焊料凸块22的连接强度。
(第2实施方式)图6是表示第2实施方式的还原回流焊处理的条件的一例的图。该图中横轴表示时间，左侧的纵轴表示温度，右侧的纵轴表示加热炉110内的甲酸的浓度(体积％)。另外，以下仅说明与第1实施方式的图5不同的部分。
第2实施方式中，将图5的步骤S12的还原处理与步骤S13的升温处理组合而变成1个还原处理(步骤S21)。该还原处理中，以在羧酸气体的还原温度T1以上且未达焊料凸块22的熔点T2的温度，使羧酸气体浓度阶段状降低的方式变更还原性气体浓度。例如，如图6所示，在时刻T11～T12，以羧酸气体浓度变成C1的方式导入第1还原性气体，在时刻T12～T13以羧酸气体浓度变成C3的方式导入第2还原性气体，在时刻T13～T14以羧酸气体浓度变成C2的方式导入第3还原性气体。其中，羧酸气体浓度的大小为C1＞C3＞C2。浓度不同的还原性气体导入的切換时间、及导入的还原性气体的羧酸气体浓度的设定可根据凸块电极11、23及焊料凸块22的形态而任意地设定，其次数及浓度并无限制。即，当加热炉110内的温度达到熔点T2时，只要以羧酸气体浓度具有能够将夹在焊料凸块22与凸块电极11、23之间的焊料凸块22的氧化膜32还原的最低限度的羧酸气体的浓度的方式，使羧酸气体浓度以m(m为2以上的自然数)阶段状降低即可。
根据第2实施方式，也能获得与第1实施方式相同的效果。
另外，所述说明中，如图1及图2所示，表示了在其中一半导体芯片20的凸块电极21上配置焊料凸块22的情况，但也可以在两个半导体芯片10、20的凸块电极11、21、23上配置焊料凸块22。此外，对于具备凸块电极11、21、23的玻璃环氧衬底与配置有焊料凸块22的半导体芯片20、或者具备焊料凸块22的玻璃环氧衬底与半导体芯片的凸块电极11、21、23的接合也是一样的。这些情况下，也通过相同的方法进行还原回流焊处理，可以形成利用2个焊料凸块22具有稳定连接形状的接合体。
虽然对本发明的若干实施方式进行了说明，但这些实施方式是作为示例而提出的，并不意图限定发明的范围。这些新颖的实施方式能以其他各种形态实施，且在不脱离发明主旨的范围内可进行各种省略、置换、变更。这些实施方式及其变化包含于发明的范围及主旨，且包含于权利要求记载的发明及其均等范围内。

Claims (11)

1.一种半导体装置的制造方法，包括：层叠体形成工序，将具有第1凸块电极及配置于所述第1凸块电极上的焊料凸块的第1半导体元件、具有第2凸块电极的第2半导体元件，通过暂时固定所述焊料凸块与所述第2凸块电极而层叠，从而形成层叠体；排气工序，将配置有所述层叠体的炉内排气；氧化膜除去工序，一边将所述炉内的温度设为显现羧酸的还原作用的还原温度以上且未达所述焊料凸块熔融的熔融温度的温度，一边以所述炉内变成第1羧酸气体浓度的方式，向所述炉内导入包含羧酸气体与惰性气体的还原性气体，将所述焊料凸块的表面的氧化膜除去；还原性气体浓度降低工序，一边将那个所述炉内的温度升温至所述熔融温度为止，一边将所述炉内的羧酸气体的浓度降低至第2羧酸气体浓度为止；以及熔融工序，将所述炉内的温度维持为所述熔融温度以上的温度，使所述焊料凸块熔融，从而将所述焊料凸块与所述第2凸块电极连接；且所述第2羧酸气体浓度是低于所述第1羧酸气体浓度，且包含能使咬入所述焊料凸块与所述第2凸块电极之间的所述焊料凸块的氧化膜还原的最低限度的羧酸气体的浓度，在所述熔融工序的开始时间点，至少所述炉内具有所述第2羧酸气体浓度。
2.一种半导体装置的制造方法，包括：层叠体形成工序，将具有第1凸块电极及配置于所述第1凸块电极上的焊料凸块的第1半导体元件、具有第2凸块电极的第2半导体元件，通过暂时固定所述焊料凸块与所述第2凸块电极而层叠，从而形成层叠体；排气工序，将配置有所述层叠体的炉内排气；氧化膜除去工序，一边将所述炉内的温度升温至所述焊料凸块熔融的熔融温度为止，一边向所述炉内导入羧酸气体与惰性气体，从而将所述焊料凸块的表面的氧化膜除去；熔融工序，将所述炉内的温度维持为所述熔融温度以上的温度，使所述焊料凸块熔融，而将所述焊料凸块与所述第2凸块电极连接；以及第2排气工序，降低所述炉内的温度，并将所述炉内排气；且在所述氧化膜除去工序中，在所述排气工序之后向所述炉内以变成第1羧酸气体浓度的方式导入所述羧酸气体与所述惰性气体后，在所述熔融工序的开始时间点以变成低于所述第1羧酸气体浓度的第2羧酸气体浓度的方式，阶段性地降低所述羧酸气体的浓度，以此方式控制所述羧酸气体与所述惰性气体的导入量，所述第2羧酸气体浓度是低于所述第1羧酸气体浓度，且包含能够将咬入所述焊料凸块与所述第2凸块电极之间的所述焊料凸块的氧化膜还原的最低限度的羧酸气体的浓度。
3.根据权利要求1或2所述的半导体装置的制造方法，其中，直至所述熔融工序结束为止，将所述炉内维持为所述第2羧酸气体浓度。
4.根据权利要求1或2所述的半导体装置的制造方法，其中，在所述熔融工序的结束时间点，所述炉内未达所述第2羧酸气体浓度。
5.根据权利要求1所述的半导体装置的制造方法，其中，在所述氧化膜除去工序至所述熔融工序期间，将所述炉内的压力维持为比大气压低的特定压力。
6.根据权利要求5所述的半导体装置的制造方法，其中，所述压力为1.3×104Pa以上8×104Pa以下的范围。
7.根据权利要求1所述的半导体装置的制造方法，其中，所述第1羧酸气体浓度为大于0.6体积％且9.2体积％以下。
8.根据权利要求7所述的半导体装置的制造方法，其中，所述第1羧酸气体浓度为2.8～9.2体积％，所述第2羧酸气体浓度为0.6～2.8体积％。
9.根据权利要求1所述的半导体装置的制造方法，其中，所述第1凸块电极及所述第2凸块电极由选自Ni、Cu、Au及Pd的群的1种金属、或选自Ni、Cu、Au及Pd的群的2种以上的金属层叠多层而成的复合膜形成，所述焊料凸块由Sn或包含Sn的合金形成。
10.根据权利要求1所述的半导体装置的制造方法，其中，所述羧酸气体中包含的羧酸为脂肪族一元或二元的低级羧酸。
11.根据权利要求10所述的半导体装置的制造方法，其中，所述低级羧酸包含选自甲酸、乙酸、丙烯酸、丙酸、草酸、琥珀酸及丙二酸的群的至少1种。
CN201910568918.9A 2019-03-15 2019-06-27 半导体装置的制造方法 Active CN111696875B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-048423 2019-03-15
JP2019048423A JP2020150202A (ja) 2019-03-15 2019-03-15 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN111696875A true CN111696875A (zh) 2020-09-22
CN111696875B CN111696875B (zh) 2023-12-05

Family

ID=72424758

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910568918.9A Active CN111696875B (zh) 2019-03-15 2019-06-27 半导体装置的制造方法

Country Status (4)

Country Link
US (1) US11476229B2 (zh)
JP (1) JP2020150202A (zh)
CN (1) CN111696875B (zh)
TW (1) TWI723424B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3092959B1 (fr) * 2019-02-20 2021-10-29 Commissariat Energie Atomique Procédé d’assemblage de composants mettant en œuvre un prétraitement des bossages de brasure permettant un assemblage par brasage sans flux et sans résidu
JP7485972B2 (ja) 2022-04-26 2024-05-17 日亜化学工業株式会社 半導体装置の製造方法
JP2024022998A (ja) 2022-08-08 2024-02-21 日東電工株式会社 ワーク保持部材及び積層体

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5249733A (en) * 1992-07-16 1993-10-05 At&T Bell Laboratories Solder self-alignment methods
US8191758B2 (en) * 2009-06-19 2012-06-05 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04127649A (ja) 1990-09-18 1992-04-28 Fujitsu Ltd 多機能電話機における登録内容表示方式
US6207551B1 (en) * 1999-08-24 2001-03-27 Conexant Systems, Inc. Method and apparatus using formic acid vapor as reducing agent for copper wirebonding
JP3378852B2 (ja) 1999-12-20 2003-02-17 富士通株式会社 加熱溶融処理装置
JP3397313B2 (ja) 1999-12-20 2003-04-14 富士通株式会社 半導体装置の製造方法及び電子部品の実装方法
TW570856B (en) * 2001-01-18 2004-01-11 Fujitsu Ltd Solder jointing system, solder jointing method, semiconductor device manufacturing method, and semiconductor device manufacturing system
KR101030764B1 (ko) * 2006-09-29 2011-04-27 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치의 제조 방법 및 제조 장치
JP4901933B2 (ja) 2009-09-29 2012-03-21 株式会社東芝 半導体装置の製造方法
JP5885135B2 (ja) 2010-07-23 2016-03-15 アユミ工業株式会社 加熱溶融処理方法および加熱溶融処理装置
TWI440110B (zh) * 2010-12-17 2014-06-01 Toshiba Kk 半導體裝置之製造方法
JP2013065761A (ja) 2011-09-20 2013-04-11 Toshiba Corp 半導体装置の製造方法および半導体装置の製造装置
JP5661957B1 (ja) * 2014-01-22 2015-01-28 オリジン電気株式会社 カルボン酸ガス濃度の推定方法及び半田付け装置
WO2016093114A1 (ja) * 2014-12-08 2016-06-16 東レ株式会社 接着剤組成物、その硬化物を含む半導体装置およびそれを用いた半導体装置の製造方法
US10610981B2 (en) * 2015-09-30 2020-04-07 Origin Company, Limited Solder paste for reduction gas, and method for producing soldered product
CN108538726B (zh) * 2017-03-03 2022-08-26 Tdk株式会社 半导体芯片的制造方法
WO2018235854A1 (ja) * 2017-06-21 2018-12-27 日立化成株式会社 半導体用接着剤、半導体装置の製造方法及び半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5249733A (en) * 1992-07-16 1993-10-05 At&T Bell Laboratories Solder self-alignment methods
US8191758B2 (en) * 2009-06-19 2012-06-05 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
TWI723424B (zh) 2021-04-01
TW202036822A (zh) 2020-10-01
US11476229B2 (en) 2022-10-18
CN111696875B (zh) 2023-12-05
US20200294960A1 (en) 2020-09-17
JP2020150202A (ja) 2020-09-17

Similar Documents

Publication Publication Date Title
JP5378078B2 (ja) 半導体装置の製造方法
US9331042B2 (en) Semiconductor device manufacturing method and semiconductor device
TW592871B (en) Solder foil and semiconductor device and electronic device
US8409919B2 (en) Method for manufacturing semiconductor device
KR101233282B1 (ko) 접합 방법 및 접합 장치
CN102760664B (zh) 半导体装置和制造半导体装置的方法
US8012866B2 (en) Method of bonding semiconductor devices utilizing solder balls
CN111696875B (zh) 半导体装置的制造方法
KR102121176B1 (ko) 반도체 패키지의 제조 방법
JP2012033518A (ja) 接合構造体製造方法および加熱溶融処理方法ならびにこれらのシステム
JP5035134B2 (ja) 電子部品実装装置及びその製造方法
JP6197619B2 (ja) 電子装置及び電子装置の製造方法
JP5885135B2 (ja) 加熱溶融処理方法および加熱溶融処理装置
JP4175858B2 (ja) はんだ被覆ボールの製造方法
JP4175857B2 (ja) はんだ被覆ボールの製造方法
CN108538824B (zh) 半导体芯片的制造方法
JP4590783B2 (ja) はんだボールの形成方法
JP2006054227A (ja) 半導体パワーモジュール及び半導体装置
JP2012129482A (ja) 半導体装置の製造方法
US20080079128A1 (en) Lead frame type stack package and method o fabricating the same
KR101214683B1 (ko) 반도체 장치의 제조 방법
JP5401996B2 (ja) 半導体装置の製造方法
KR101192925B1 (ko) 반도체 장치의 제조 방법
US20100148364A1 (en) Semiconductor device and method for producing semiconductor device
TW202123352A (zh) 半導體裝置之製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Tokyo

Applicant after: Kaixia Co.,Ltd.

Address before: Tokyo

Applicant before: TOSHIBA MEMORY Corp.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant