Nothing Special   »   [go: up one dir, main page]

CN111354814B - Double-junction laminated solar cell and preparation method thereof - Google Patents

Double-junction laminated solar cell and preparation method thereof Download PDF

Info

Publication number
CN111354814B
CN111354814B CN201811573631.7A CN201811573631A CN111354814B CN 111354814 B CN111354814 B CN 111354814B CN 201811573631 A CN201811573631 A CN 201811573631A CN 111354814 B CN111354814 B CN 111354814B
Authority
CN
China
Prior art keywords
layer
buffer layer
thickness
cell
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811573631.7A
Other languages
Chinese (zh)
Other versions
CN111354814A (en
Inventor
许吉林
乔秀梅
刘琦
梁鹏
王权
辛智渊
童翔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zishi Energy Co ltd
Original Assignee
Zishi Energy Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zishi Energy Co ltd filed Critical Zishi Energy Co ltd
Priority to CN201811573631.7A priority Critical patent/CN111354814B/en
Publication of CN111354814A publication Critical patent/CN111354814A/en
Application granted granted Critical
Publication of CN111354814B publication Critical patent/CN111354814B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/074—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a heterojunction with an element of Group IV of the Periodic Table, e.g. ITO/Si, GaAs/Si or CdTe/Si solar cells
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/0623—Sulfides, selenides or tellurides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C23C14/083—Oxides of refractory metals or yttrium
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/24—Vacuum evaporation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58—After-treatment
    • C23C14/5806—Thermal treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24—Deposition of silicon only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/403—Oxides of aluminium, magnesium or beryllium
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/407—Oxides of zinc, germanium, cadmium, indium, tin, thallium or bismuth
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0328—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032
    • H01L31/0336—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032 in different semiconductor regions, e.g. Cu2X/CdX hetero- junctions, X being an element of Group VI of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thermal Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The invention relates to a double-junction laminated solar cell and a preparation method thereof, wherein the cell comprises a crystal silicon cell and an antimony selenide sulfide cell which are arranged in a laminated manner, wherein the antimony selenide sulfide cell is provided with an antimony selenide sulfide light absorption layer and a buffer layer; sb used for preparing the antimony selenide sulfide light-absorbing layer 2 (Se x S 1–x ) 3 In the formula, x is more than or equal to 0 and less than or equal to 0.5; the buffer layer is made of Zn (O, S, OH) X One or more of CdS, ZnO or (Zn, Mg) O. The laminated cell can improve the efficient and sufficient absorption of solar spectrum and realize Sb 2 (Se x S 1‑x ) 3 The thin film absorbs light with the wavelength of 300-700nm, and the crystalline silicon absorbs light with the wavelength of 700-1200nm, so that the laminated cell has a wider spectral response value.

Description

Double-junction laminated solar cell and preparation method thereof
Technical Field
The invention relates to the field of solar cells, in particular to a novel double-junction laminated cell and a preparation method thereof.
Background
The crystalline silicon solar cell technology is the most mature photovoltaic power generation technology at present, and due to the advantages of the crystalline silicon solar cell technology in the aspects of comprehensive cost and conversion efficiency, other types of solar cells such as CIGS, OPV, gallium arsenide and other thin film cells are difficult to replace crystalline silicon cells in a short time, the performance of the crystalline silicon cells is continuously improved, and the technology is continuously optimized, so that the method has important significance in reducing the cost. However, the conventional crystalline silicon cell has some limitations in material and process, and the forbidden band width of crystalline silicon is 1.12eV and is an indirect band gap; in addition, the conventional crystalline silicon battery needs high temperature in the diffusion and sintering process, minority carrier recombination is aggravated in the high temperature processes, and the influence of auger recombination is more obvious in the thermal diffusion process, so that the open-circuit voltage limit value of the crystalline silicon battery is about 750mV, the theoretical limit efficiency of the crystalline silicon battery is about 29%, and the efficiency of the crystalline silicon battery is difficult to greatly improve. Therefore, a new heterojunction cell with upper and lower double absorption layers formed by materials with excellent optical and electrical properties and silicon is found, and the heterojunction cell has important significance for improving the spectral absorption rate and further improving the efficiency of the solar cell.
Antimony selenide sulfide Sb 2 (Se x S 1-x ) 3 The material is a V-VI family direct band gap semiconductor material with stable properties, and the earth crust is rich in content, safe and nontoxic. And has high light absorption coefficient, moderate band gap width and easy regulation (1.1-1.8eV), so the material is regarded as one of the most promising solar cell materials. The forbidden band widths of antimony selenide sulfide and crystalline silicon can be well complemented, the absorption spectrum of the solar cell is widened, and the double-junction laminated cell is very suitable for being manufactured; however, no research report about antimony selenide sulfide and a crystalline silicon tandem cell exists at present, and the research on the specific structure and the preparation method of the double-junction tandem cell is very little.
Disclosure of Invention
The invention aims to provide a double-junction laminated solar cell, which comprises a crystalline silicon cell and an antimony selenide sulfide cell which are arranged in a laminated manner, wherein the antimony selenide sulfide cell is internally provided with an antimony selenide sulfide light absorption layer and a buffer layer;
preparation of said Sb 2 (Se x S 1–x ) 3 Material Sb of light-absorbing layer 2 (Se x S 1–x ) 3 In the formula, x is more than or equal to 0 and less than or equal to 0.5;
the buffer layer is made of Zn (O, S, OH) X One or more of CdS, ZnO or (Zn, Mg) O.
For Sb 2 (Se x S 1–x ) 3 And in addition, when x is more than or equal to 0 and less than or equal to 0.5, and the buffer layer prepared by the material is arranged on the surface of the light absorption layer, the antimony selenide sulfide and the crystalline silicon battery can play a better matching role, and the overall efficiency of the battery is improved.
In the invention, (Zn, Mg) O is magnesium-doped zinc oxide, and in the preparation process, Zn and Mg are jointly used as film coating materials to carry out film coating by adopting a conventional process. The relative amounts of Zn and Mg used herein are not particularly limited as long as a (Zn, Mg) O film usable in the art can be formed.
Zn(O,S,OH) X The zinc oxide is hydrogen and sulfur doped zinc oxide, and Zn, S and H are jointly used as film coating materials to carry out film coating by adopting a conventional process in the preparation process. Here, the relative amounts of Zn, S and H are not particularly limited as long as Zn (O, S, OH) usable in the art can be formed X And (5) film forming.
Preferably, the buffer layer includes a first buffer layer and a second buffer layer;
the first buffer layer is attached to the surface of the antimony selenide sulfide light absorption layer, and the second buffer layer is attached to the first buffer layer far away from Sb 2 (Se x S 1–x )3 surface of light absorbing layer. Compared with a single-layer buffer layer, the double-buffer layer is arranged, so that the transmission and collection efficiency of carriers can be effectively improved.
Further preferably, the first buffer layer material is Zn (O, S, OH) X Or CdS, and the material of the second buffer layer is ZnO or (Zn, Mg) O. Zn (O, S, OH) X Or the band gap of CdS is lower than that of ZnO or (Zn, Mg) O, so that the CdS is more suitable for being used as the first buffer layer.
Preferably, the material of the first buffer layer is Zn (O, S, OH) X The material of the second buffer layer is (Zn, Mg) O; or the first buffer layer is CdS, and the second buffer layer is ZnO. The prepared battery has better performance by adopting the matching as the first buffer layer or the second buffer layer.
As a further preferable mode, the light absorption layer material is Sb 2 (Se 0.1 S 0.9 ) 3 The first buffer layer is CdS; the second buffer layer is ZnO.
Or the light absorption layer is made of Sb 2 (Se 0.25 S 0.75 ) 3 The first buffer layer is Zn (O, S, OH) X (ii) a The second buffer layer is (Zn, Mg) O.
Preferably, said Sb is 2 (Se x S 1–x ) 3 The thickness of the light absorption layer is 200-1000 nm;
preferably, the thickness of the first buffer layer is 10-80 nm;
preferably, the thickness of the second buffer layer is 50 to 100 nm.
Preferably, the antimony selenide sulfide light absorption layer is located between the crystalline silicon battery and the first buffer layer, and the antimony selenide sulfide light absorption layer is attached to the surface of the crystalline silicon battery.
Preferably, the antimony selenide sulfide cell further comprises a TCO transparent conducting layer and an antireflection layer; the first surface of the TCO transparent conducting layer is attached to the surface, far away from the first buffer layer, of the second buffer layer, and the antireflection layer is attached to the second surface of the TCO transparent conducting layer.
Preferably, the material of the TCO transparent conductive layer is one of ITO, FTO, IZO, AZO, GZO, or graphene thin film.
Preferably, the antireflection film is MgF 2 Or Si 3 N 4 。
Preferably, the thickness of the TCO transparent conductive layer is 50-200 nm.
Preferably, the thickness of the antireflection film is 50 to 100 nm.
As a preferred scheme, the antimony selenide sulfide battery comprises an antimony selenide sulfide light absorption layer, a first buffer layer, a second buffer layer, a TCO layer and an antireflection film;
the first buffer layer is attached to the first surface of the antimony sulfide light absorption layer, and the second buffer layer is attached to the first buffer layer far away from Sb 2 (Se x S 1–x )3, the first surface of the TCO transparent conductive layer is attached to the surface, away from the first buffer layer, of the second buffer layer, the antireflection layer is attached to the second surface of the TCO transparent conductive layer, and the first surface and the second surface of the TCO transparent conductive layer are oppositely arranged;
the Sb 2 (Se x S 1–x ) 3 The thickness of the light absorption layer is 200-1000nm, the thickness of the first buffer layer is 10-80nm, the thickness of the second buffer layer is 50-100nm, the thickness of the TCO transparent conductive layer is 50-200nm, and the thickness of the antireflection film is 50-100 nm; the thickness of the second buffer layer is 25-40 nm greater than that of the first buffer layer.
The Sb is 2 (Se x S 1–x ) 3 X is more than or equal to 0 and less than or equal to 0.5 in the light absorption layer material, and the first buffer layer material is Zn (O, S, OH) X Or CdS, the second buffer layer is made of ZnO or (Zn, Mg) O, the TCO transparent conductive layer is made of one of ITO, FTO, IZO, AZO, GZO or graphene films, and the antireflection film is MgF 2 Or Si 3 N 4 。
The antimony selenide sulfur battery with the structure is compounded with the crystalline silicon battery, so that the conversion efficiency of the battery can be effectively improved.
Preferably, the crystalline silicon cell comprises Si arranged in a stacked manner in sequence 3 N 4 Passivation layer, Al 2 O 3 Passivation layer, p/n type crystalline silicon substrate and SiO 2 Layer n + poly-Si layer, ITO layer and MoO x A layer; the MoO x The layer is attached to the surface of the antimony selenide sulfur light absorption layer far away from the first buffer layer.
Preferably, the ITO layer is made of Sn-doped In 2 O 3 ；
Preferably, the MoO x X in the layer is 3;
preferably, said Si is 3 N 4 The thickness of the passivation layer is 20-100 nm;
preferably, the Al is 2 O 3 The thickness of the passivation layer is 20-100 nm;
preferably, the thickness of the p/n type crystalline silicon substrate is 150-;
preferably, the SiO 2 The thickness of the layer is 1.0-2.0 nm;
preferably, said n + The deposition thickness of the poly-Si layer is 100-300 nm;
preferably, the thickness of the ITO layer is 20-100 nm;
preferably, the MoO x The thickness of the layer is 50-300 nm.
The laminated layer of the invention also comprises Si 3 N 4 A back electrode of a passivation layer and a positive electrode at the anti-reflection film.
Another object of the invention is to protect the process for the preparation of the material according to the invention, comprising the following steps:
by double source vacuum co-evaporation with Sb 2 S 3 Powder and Sb 2 Se 3 Forming the Sb on the surface of a substrate as a raw material 2 (Se x S 1–x ) 3 A light absorbing layer;
chemical water bath deposition method is adopted to deposit on the Sb 2 (Se x S 1–x ) 3 Forming the first buffer layer on the light absorption layer;
and forming the second buffer layer on the first buffer layer by adopting an atomic layer deposition method.
Preferably, the Sb is formed by adopting a double-source vacuum co-evaporation method 2 (Se x S 1–x ) 3 In the process of the light absorption layer, the vacuum degree is set to 10 -3 -10 -6 Pa, the evaporation temperature is 300-700 ℃, and the substrate surface temperature is 200-400 ℃.
Preference is given toOf (1) forming said Sb 2 (Se x S 1–x ) 3 Annealing the light absorbing layer at the temperature of 300-500 ℃ for 0.5-2.0 h;
and/or, after the second buffer layer is formed, annealing is carried out for 0.5-2.0h under the condition of the temperature of 100-300 ℃.
Preferably, a TCO transparent conductive layer is prepared on the surface of the second buffer layer by a magnetron sputtering method, and an antireflection layer is prepared on the surface of the TCO transparent conductive layer by a thermal evaporation method.
Preferably, the preparation method further comprises the preparation of the crystalline silicon battery, and comprises the following steps:
1) preparing SiO on the front side of a silicon wafer by adopting a high-temperature thermal oxidation method 2 A layer; then adopting Low Pressure Chemical Vapor Deposition (LPCVD) to form SiO 2 Surface deposition of a layer n + A poly-Si layer, performing high temperature annealing;
2) at said n + performing magnetron sputtering on the surface of the poly-Si layer to form an ITO transparent conductive film; sequentially preparing Al on the back of the silicon wafer by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method 2 O 3 And Si 3 N 4 A passivation layer;
3) preparing MoO on the surface of the ITO by adopting a thermal evaporation method x A layer.
Preferably, the temperature of the high-temperature thermal oxygen oxidation in the step 1) is 200-500 ℃.
Preferably, the annealing temperature in the step 1) is 800-1150 ℃.
As a preferred scheme, the preparation method of the invention comprises the following steps:
1) preparing SiO on the front side of a silicon wafer by adopting a high-temperature thermal oxidation method 2 A layer; then adopting Low Pressure Chemical Vapor Deposition (LPCVD) to form SiO 2 Surface deposition of a layer n + A poly-Si layer, performing high-temperature annealing;
2) at said n + performing magnetron sputtering on the surface of the poly-Si layer to form an ITO transparent conductive film; sequentially preparing Al on the back of the silicon wafer by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) method 2 O 3 And Si 3 N 4 A passivation layer;
3) MoO is prepared on the ITO layer on the front side of the silicon wafer by adopting a thermal evaporation method x A layer.
4) Vacuum degree 10 of vacuum thermal evaporation equipment -3 -10 -6 Pa, selecting Sb 2 S 3 Powder and Sb 2 Se 3 Powder is used as an evaporation source, the evaporation temperature is 300-700 ℃, the substrate surface temperature is 200-400 ℃, and the MoO is subjected to a codeposition method x Surface preparation of Sb 2 (Se x S 1–x ) 3 A light absorbing layer; after the deposition is finished, annealing;
5) by chemical water bath deposition method, the Sb is treated 2 (Se x S 1–x ) 3 Preparing a first buffer layer on the surface of the light absorption layer;
6) and preparing a second buffer layer on the surface of the first buffer layer by adopting an atomic layer deposition method, and annealing to obtain the buffer layer.
The invention has the following beneficial effects:
1) the laminated cell can improve the efficient and sufficient absorption of the solar spectrum, and realizes that the antimony selenide sulfide film absorbs light with the wavelength of 300-700nm, and the crystalline silicon absorbs light with the wavelength of 700-1200nm, so that the laminated cell has a wider spectral response value;
2) the preparation process of the laminated cell can fully utilize the mature process and equipment of the existing crystalline silicon and thin film cell, does not need to replace or increase production equipment, reduces the capital investment of products, and has rich raw materials of antimony sulfide and antimony selenide and lower cell production cost.
Drawings
Fig. 1 is a schematic view of the structure of the laminated cell of the present invention.
In the figure: 1. p/n type crystal silicon base, 2, SiO 2 Layer, 3, n + poly-Si layer, 4, Al 2 O 3 Passivation layer, 5, Si 3 N 4 A passivation layer; 6. back electrode, 7, ITO layer, 8, MoO x Layer, 9, Sb 2 (Se x S 1–x ) 3 A light absorption layer 10, a first buffer layer 11, a second buffer layer 12, and a TCO transparent conductive layer; 13. an anti-reflective layer; 14. and a positive electrode.
Detailed Description
The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Example 1
The embodiment relates to Sb 2 (Se 0.1 S 0.9 ) 3 The structure of the/Si double-junction laminated cell comprises from bottom to top: ag electrode, Si 3 N 4 Passivation layer, Al 2 O 3 Passivation layer, p-type crystalline silicon substrate and SiO 2 Layer n + poly-Si layer, ITO layer, MoO x Layer, Sb 2 (Se 0.1 S 0.9 ) 3 Light absorption layer, first buffer layer CdS, second buffer layer ZnO, transparent conducting layer AZO and antireflection layer MgF 2 And an Au electrode;
said Si 3 N 4 And Al 2 O 3 The thickness of the passivation layer is 50 nm; the thickness of the p-type crystalline silicon substrate is 180 mu m, and the SiO is 2 The layer thickness was 1.5 nm; n is + The deposition thickness of the poly-Si layer is 150nm, and the thickness of the ITO layer is 20 nm; the MoO x Layer thickness of 150nm, said Sb 2 (Se 0.1 S 0.9 ) 3 The band gap of the light absorption layer material is 1.72eV, and the thickness of the light absorption layer material is 500 nm; the thickness of the first buffer layer CdS is 20 nm; the thickness of the second buffer layer ZnO is 50 nm; the thickness of the AZO layer is 100 nm; the antireflection layer is MgF 2 Is 50 nm; the thickness of the Ag electrode is 800nm, and the thickness of the Au electrode is 300 nm. The structure schematic diagram is shown in figure 1;
the embodiment also relates to a preparation method of the battery, which comprises the following steps:
1) cleaning p-type silicon wafer, and preparing SiO by thermal oxidation of the front surface of the silicon wafer at 500 DEG C 2 A layer; then adopting a low-pressure chemical vapor deposition method to continuously deposit n + Annealing the poly-Si layer at 900 ℃ for half an hour; at said n + performing magnetron sputtering on the surface of the poly-Si layer to form a layer of ITO transparent conductive film;
2) sequentially preparing Al on the back of the silicon wafer by adopting a PECVD method 2 O 3 And Si 3 N 4 A passivation layer;
3) MoO is prepared on the surface of ITO by adopting a thermal evaporation method x A layer;
4) in the MoO x Preparing Sb on the surface of the layer by adopting a double-source vacuum co-evaporation method 2 (Se x S 1–x ) 3 The light absorption layer comprises the following specific steps: vacuum degree of 1 × 10 by using vacuum thermal evaporation equipment -6 Pa, the evaporation source is Sb 2 S 3 Powder and Sb 2 Se 3 Powder, wherein the evaporation temperature is 500 ℃, and the substrate surface temperature during deposition is 300 ℃; after the deposition is finished, continuously annealing for 2.0h at 300 ℃ to improve the performance of the film;
5) in Sb 2 (Se x S 1–x ) 3 Preparing a first buffer layer CdS on the light absorption layer by adopting a chemical water bath deposition method, preparing a second buffer layer ZnO by adopting an atomic layer deposition method, and annealing at 200 ℃ for 1.0 h;
6) preparing an AZO transparent conductive layer on the surface of the second buffer layer ZnO by adopting a magnetron sputtering method, and sequentially preparing an antireflection layer MgF by adopting a thermal evaporation method 2 A front electrode Au and a back electrode Ag.
Example 2
The embodiment relates to Sb 2 (Se 0.25 S 0.75 ) 3 The structure of the/Si double-junction laminated cell comprises from bottom to top: al electrode, Si 3 N 4 Passivation layer, Al 2 O 3 Passivation layer, n-type crystalline silicon substrate and SiO 2 Layer n + poly-Si layer, ITO layer, MoO x Layer, Sb 2 (Se 0.25 S 0.75 ) 3 Light absorbing layer, first buffer layer Zn (O, S, OH) X A second buffer layer (Zn, Mg) O, a transparent conductive layer FTO and an antireflection layer Si 3 N 4 And Ag/Cu electrodes.
Said Si 3 N 4 And Al 2 O 3 The thickness of the passivation layer is 20nm, the thickness of the n-type crystalline silicon substrate is 160 mu m, and the SiO is 2 The layer thickness is 1.7nm, n + The deposition thickness of the poly-Si layer is 200nm, the thickness of the ITO layer is 35nm, and the MoO is x Layer thickness 200nm, said Sb 2 (Se 0.25 S 0.75 ) 3 Light absorbing layer materialThe band gap is 1.65eV, and the thickness is 350 nm; the first buffer layer Zn (O, S, OH) X Is 45 nm; the thickness of the second buffer layer (Zn, Mg) O is 75 nm; the thickness of the FTO layer is 85 nm; the antireflection film is Si 3 N 4 Is 80 nm; the thickness of the Al electrode is 1000nm, and the thickness of the Ag/Cu electrode is 500 nm.
The embodiment also relates to a preparation method of the battery, which comprises the following steps:
1) firstly, cleaning an n-type silicon wafer, and preparing SiO by thermally oxidizing the front surface of the silicon wafer at 300 DEG C 2 A layer; then adopting a low-pressure chemical vapor deposition method to deposit n on the front surface + Annealing the poly-Si layer for 1 hour at 850 ℃; on the front side of the silicon wafer (n) + poly-Si layer) magnetron sputtering a layer of ITO transparent conductive film;
2) preparing Al on the back of the silicon wafer by adopting a PECVD method 2 O 3 And Si 3 N 4 A passivation layer;
3) MoO is prepared on the ITO layer on the front side of the silicon wafer by adopting a thermal evaporation method x A layer;
4) sb preparation by double-source vacuum co-evaporation method 2 (Se 0.25 S 0.75 ) 3 The light absorption layer is specifically as follows: vacuum degree of 2X 10 is set by adopting vacuum thermal evaporation equipment -3 Pa, the evaporation source is Sb 2 S 3 Powder and Sb 2 Se 3 Powder, wherein the evaporation temperature is 650 ℃, and the substrate surface temperature during deposition is 250 ℃; after the deposition is finished, continuously annealing for 2.0h at 350 ℃ to improve the performance of the film;
5) in Sb 2 (Se 0.25 S 0.75 ) 3 Preparing a first buffer layer Zn (O, S, OH) on the light absorption layer by adopting a chemical water bath deposition method in sequence X Preparing a second buffer layer (Zn, Mg) O by adopting an atomic layer deposition method, and annealing at the annealing temperature of 150 ℃ for 1.5 h;
6) finally, preparing a FTO transparent conductive layer by adopting a magnetron sputtering method, and sequentially preparing an antireflection layer Si by adopting a thermal evaporation method 3 N 4 The front electrode is made of Ag/Cu alloy, and the back electrode is made of Al.
Example 3
The present example differs from example 1 in that:
the light absorption layer is made of Sb 2 (Se 0.5 S 0.5 ) 3 The band gap is 1.42eV, and the thickness is 750 nm;
the first buffer layer Zn (O, S, OH) X Is 75 nm;
the thickness of the second buffer layer (Zn, Mg) O is 100 nm;
in the preparation process, the vacuum degree is set to be 1 multiplied by 10 in the step 4) -5 Setting the evaporation temperature to 650 ℃, setting the substrate surface temperature to 400 ℃ during deposition, and annealing for 1.0h at 450 ℃;
step 5) the first buffer layer is Zn (O, S, OH) X The second buffer layer is (Zn, Mg) O, the annealing temperature is 300 ℃, and the annealing time is 0.5 h.
Example 4
This example differs from example 1 in that:
the light absorption layer is made of Sb 2 S 3 The band gap is 1.8eV, and the thickness is 1000 nm;
step 4) setting the vacuum degree to 10 -4 The evaporation temperature is set to 350 ℃, the substrate surface temperature during deposition is 280 ℃, and annealing is carried out for 1.0h at 350 ℃.
Example 5
The difference from embodiment 1 is that the first buffer layer is CdS and the second buffer layer is (Zn, Mg) O.
Example 6
The difference compared to example 1 is that the first buffer layer is Zn (O, S, OH) X The second buffer layer is ZnO
Example 7
This example differs from example 1 in that: the antimony selenide sulfur battery is only provided with one buffer layer which is CdS.
Comparative example 1
Compared with the embodiment 1, the difference is that the antimony selenide sulfide light-absorbing layer material is Sb 2 (Se 0.8 S 0.2 ) 3 A band gap of 1.3eV
Comparative example 2
The embodiment relates to a crystalThe silicon cell had the same structure as the crystalline silicon cell in example 1, and was composed of an Ag back electrode and an Si back electrode in this order from bottom to top 3 N 4 Passivation layer, Al 2 O 3 Passivation layer, p-type crystalline silicon substrate and SiO 2 Layer n + poly-Si layer, Ag front electrode
Examples of the experiments
At room temperature, AM1.5G, 100 mW. cm -2 The examples were tested under conditions, with the main test equipment: the efficiency of the cell was measured using a solar simulator, standard silicon detector, Keithley 2400 source meter, IV tester, etc. The specific test results are shown in table 1:
TABLE 1
Battery with a battery cell Distribution of forbidden band width of battery Conversion efficiency
Example 1 1.72eV/1.12eV 28.5％
Example 2 1.65eV/1.12eV 30.8％
Example 3 1.42eV/1.12eV 27.2％
Example 4 1.8eV/1.12eV 26.7％
Example 5 1.72eV/1.12eV 25.8％
Example 6 1.65eV/1.12eV 25.2％
Example 7 1.72eV/1.12eV 25.0％
Comparative example 1 1.3eV/1.12eV 21.5％
Comparative example 2 1.12eV 24.5％
As can be seen from the data in the above table, Sb in examples 1, 2, 3 and 4 2 (Se x S 1-x ) 3 The photoelectric conversion efficiency of the/Si double-junction laminated cell is greatly improved compared with that of the existing monocrystalline silicon cell, and the photoelectric conversion efficiency of the/Si double-junction laminated cell is also improved to a certain extent in the embodiments 5-7. The reason is that the forbidden bandwidth distribution of the antimony selenide sulfide cell and the crystalline silicon cell keeps better matching with the solar cell spectrum, and the solar spectrum can be better utilized compared with the monocrystalline silicon cell.
Although the invention has been described in detail hereinabove by way of general description, specific embodiments and experiments, it will be apparent to those skilled in the art that many modifications and improvements can be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims (4)

1. A double-junction tandem solar cell, characterized in that its structure comprises from bottom to top: ag electrode, Si 3 N 4 Passivation layer, Al 2 O 3 Passivation layer, p-type crystalline silicon substrate and SiO 2 Layer n + poly-Si layer, ITO layer, MoO x Layer, Sb 2 (Se 0.1 S 0.9 ) 3 Light absorption layer, CdS first buffer layer, ZnO second buffer layer, AZO transparent conductive layer and MgF antireflection layer 2 And an Au electrode; wherein Sb 2 (Se 0.1 S 0.9 ) 3 The thickness of the light absorption layer is 500nm, the thickness of the CdS first buffer layer is 20nm, and the thickness of the ZnO second buffer layer is 50 nm;
or the structure comprises from bottom to top: al electrode, Si 3 N 4 Passivation layer, Al 2 O 3 Passivation layer, n-type crystalline silicon substrate and SiO 2 Layer n + poly-Si layer, ITO layer, MoO x Layer, Sb 2 (Se 0.25 S 0.75 ) 3 Light absorbing layer, first buffer layer Zn (O, S, OH) X A second buffer layer (Zn, Mg) O, a transparent conductive layer FTO and an antireflection layer Si 3 N 4 And Ag/Cu electrodes; wherein Sb 2 (Se 0.25 S 0.75 ) 3 The thickness of the light absorption layer is 350 nm; first buffer layer Zn (O, S, OH) X Is 45 nm; the thickness of the second buffer layer (Zn, Mg) O was 75 nm.
2. The method of fabricating a dual junction tandem solar cell of claim 1, comprising:
by double source vacuum co-evaporation with Sb 2 S 3 Powder and Sb 2 Se 3 Forming Sb on the surface of a substrate as a raw material 2 (Se x S 1–x ) 3 X =0.1 or 0.25 light absorbing layer;
and preparing a buffer layer.
3. The method of fabricating a dual junction tandem solar cell according to claim 2, comprising:
chemical water bath deposition method is adopted to deposit on the Sb 2 (Se x S 1–x ) 3 X =0.1 or 0.25 light absorbing layer on which the first buffer layer is formed;
and forming the second buffer layer on the first buffer layer by adopting an atomic layer deposition method.
4. The method according to claim 2, wherein said Sb is formed by a double source vacuum co-evaporation method 2 (Se x S 1–x ) 3 In the process of x =0.1 or 0.25 light absorbing layer, when x =0.1, the degree of vacuum is set to 1 × 10 -6 Pa, the evaporation temperature is 500 ℃, the surface temperature of the substrate is 300 ℃, and annealing is continued for 2.0h at 300 ℃ after deposition is finished; when x =0.25, the vacuum degree was set to 2 × 10 -3 Pa, the evaporation temperature is 650 ℃, the substrate surface temperature is 250 ℃, and after the deposition is finished, the annealing is continued for 2.0 hours at 350 ℃;
after the second buffer layer is formed, annealing is carried out for 0.5-2.0h under the condition of the temperature of 100-300 ℃.
CN201811573631.7A 2018-12-21 2018-12-21 Double-junction laminated solar cell and preparation method thereof Active CN111354814B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811573631.7A CN111354814B (en) 2018-12-21 2018-12-21 Double-junction laminated solar cell and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811573631.7A CN111354814B (en) 2018-12-21 2018-12-21 Double-junction laminated solar cell and preparation method thereof

Publications (2)

Publication Number Publication Date
CN111354814A CN111354814A (en) 2020-06-30
CN111354814B true CN111354814B (en) 2022-09-09

Family

ID=71197869

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811573631.7A Active CN111354814B (en) 2018-12-21 2018-12-21 Double-junction laminated solar cell and preparation method thereof

Country Status (1)

Country Link
CN (1) CN111354814B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115896820A (en) * 2022-11-29 2023-04-04 电子科技大学长三角研究院(湖州) Three-electrode type photoelectrochemical cell for photolysis of water to produce hydrogen

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0297644A2 (en) * 1987-07-01 1989-01-04 ENIRICERCHE S.p.A. Process for preparing thin films of crystalline metals or semiconductors on amorphous substrates, and thin-film electroluminescent device obtainable by means of such a process
US4818357A (en) * 1987-05-06 1989-04-04 Brown University Research Foundation Method and apparatus for sputter deposition of a semiconductor homojunction and semiconductor homojunction products created by same
WO2012001689A1 (en) * 2010-06-29 2012-01-05 Yeda Research And Development Co. Ltd. Photovoltaic cell and method of its manufacture
WO2013106836A1 (en) * 2012-01-13 2013-07-18 The Regents Of The University Of California Metal-chalcogenide photovoltaic device with metal-oxide nanoparticle window layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2243166A1 (en) * 2007-12-31 2010-10-27 Rafael Nathan Kleiman High efficiency silicon-based solar cells
US8969719B2 (en) * 2008-12-19 2015-03-03 Zetta Research and Development LLC—AQT Series Chalcogenide-based photovoltaic devices and methods of manufacturing the same
US10062800B2 (en) * 2013-06-07 2018-08-28 First Solar, Inc. Photovoltaic devices and method of making
CN105810772B (en) * 2016-05-30 2017-07-14 中南大学 A kind of antimony trisulfide/silicon stacked solar cell, cascade solar cell and preparation method thereof
CN106898662B (en) * 2017-03-10 2018-06-29 河北大学 A kind of p-i-n types antimony selenide solar cell

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818357A (en) * 1987-05-06 1989-04-04 Brown University Research Foundation Method and apparatus for sputter deposition of a semiconductor homojunction and semiconductor homojunction products created by same
EP0297644A2 (en) * 1987-07-01 1989-01-04 ENIRICERCHE S.p.A. Process for preparing thin films of crystalline metals or semiconductors on amorphous substrates, and thin-film electroluminescent device obtainable by means of such a process
WO2012001689A1 (en) * 2010-06-29 2012-01-05 Yeda Research And Development Co. Ltd. Photovoltaic cell and method of its manufacture
WO2013106836A1 (en) * 2012-01-13 2013-07-18 The Regents Of The University Of California Metal-chalcogenide photovoltaic device with metal-oxide nanoparticle window layer

Also Published As

Publication number Publication date
CN111354814A (en) 2020-06-30

Similar Documents

Publication Publication Date Title
Sun et al. Toward efficiency limits of crystalline silicon solar cells: recent progress in high‐efficiency silicon heterojunction solar cells
CN109004053B (en) Crystalline silicon/thin film silicon heterojunction solar cell with double-sided light receiving function and manufacturing method thereof
CN112086535B (en) Laminated battery
US8658889B2 (en) Quantum dot thin film solar cell
CN207320169U (en) A kind of perovskite battery of graded bandgap
US8679892B2 (en) Method for manufacturing silicon thin-film solar cells
CN110970562A (en) Perovskite/crystalline silicon laminated solar cell and preparation method thereof
US20100200059A1 (en) Dual-side light-absorbing thin film solar cell
KR102350885B1 (en) Solar cell
CN116669439B (en) Solar cell, preparation method thereof, photovoltaic module and photovoltaic device
Boccard et al. Passivation and carrier selectivity of TiO 2 contacts combined with different passivation layers and electrodes for silicon solar cells
WO2023115870A1 (en) Pn heterojunction antimony selenide/perovskite solar cell, and preparation method therefor
CN101510568A (en) Amorphous silicon/dye-sensitized laminated thin film solar cell and preparation method thereof
CN209087911U (en) A kind of perovskite/crystal silicon lamination solar cell
CN101393942B (en) Polycrystalline-silicon carbide lamination thin-film solar cell
US12100562B2 (en) Solar cell with alumina coated porous silicon layer
CN111354814B (en) Double-junction laminated solar cell and preparation method thereof
CN105355699A (en) Multi-junction multi-lamination cadmium telluride thin film solar cell and preparation method thereof
CN218160390U (en) HJT battery structure with passivation medium oxide film
CN204668332U (en) There is the cadmium telluride diaphragm solar battery of gradient-structure
Petti et al. Thin Films in Photovoltaics
Terukov et al. Investigation of the characteristics of heterojunction solar cells based on thin single-crystal silicon wafers
CN205194721U (en) Many stromatolites of multijunction cadmium telluride thin -film solar cell
CN113035968A (en) Perovskite/crystalline silicon tandem solar cell based on double-tunneling compound
CN219679160U (en) Photovoltaic cell

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
TA01 Transfer of patent application right

Effective date of registration: 20210120

Address after: Unit 611, unit 3, 6 / F, building 1, yard 30, Yuzhi East Road, Changping District, Beijing 102208

Applicant after: Zishi Energy Co.,Ltd.

Address before: Room a129-1, No. 10, Zhongxing Road, science and Technology Park, Changping District, Beijing

Applicant before: DONGTAI HI-TECH EQUIPMENT TECHNOLOGY Co.,Ltd.

TA01 Transfer of patent application right
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant