CN110556891A - Charging circuit of double-charger - Google Patents
Charging circuit of double-charger Download PDFInfo
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- CN110556891A CN110556891A CN201910755634.0A CN201910755634A CN110556891A CN 110556891 A CN110556891 A CN 110556891A CN 201910755634 A CN201910755634 A CN 201910755634A CN 110556891 A CN110556891 A CN 110556891A
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- 239000003990 capacitor Substances 0.000 claims description 20
- 230000009977 dual effect Effects 0.000 claims description 18
- 238000001514 detection method Methods 0.000 claims description 16
- 238000005070 sampling Methods 0.000 description 20
- 101100102627 Oscarella pearsei VIN1 gene Proteins 0.000 description 17
- 238000010586 diagram Methods 0.000 description 4
- 101100191136 Arabidopsis thaliana PCMP-A2 gene Proteins 0.000 description 3
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 description 3
- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
- H02H11/002—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/0036—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using connection detecting circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0042—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries characterised by the mechanical construction
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The invention provides a charging circuit of a double charger, which comprises a first OVP chip and a second OVP chip, wherein the first OVP chip is connected with the second OVP chip through a power supply; the first OVP chip comprises a first voltage input pin and a first voltage output pin; the second OVP chip comprises a second voltage input pin and a second voltage output pin; the first voltage input pin is used for connecting a first charger, and the first voltage output pin is used for connecting equipment to be charged; the second voltage input pin is used for connecting a second charger, and the second voltage output pin is used for connecting equipment to be charged. According to the charging circuit of the double chargers, when the two chargers charge the equipment to be charged at the same time, the charger with higher power is preferentially used for charging the equipment to be charged, and the charging efficiency is improved; and if the voltages of the two chargers are equal, the two electrical appliances charge the equipment to be charged at the same time, so that the power of the input power supply is further improved, the function of quick charging can be realized, and the cost of the charging circuit is lower.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of electronic equipment charging, in particular to a charging circuit of a double-charger.
[ background of the invention ]
At present, electronic equipment such as a notebook computer generally has only one charging port, and if rapid charging is to be realized, the charging can be realized only by increasing the power of a charger, so that the cost for increasing the power of the charger is increased, and the power consumption of the whole charging circuit is larger and the cost is higher.
In view of the above, it is desirable to provide a novel charging circuit for a dual charger to overcome the above-mentioned drawbacks.
[ summary of the invention ]
the invention aims to provide a charging circuit of double chargers, when two chargers charge equipment to be charged simultaneously, a charger with higher power is preferentially used for charging the equipment to be charged, so that the charging efficiency is improved, and when the voltages of the two chargers are equal, the two chargers charge the equipment to be charged simultaneously, so that the power of an input power supply is further improved, the function of quick charging can be realized, and the cost of the charging circuit is lower.
In order to achieve the above object, the present invention provides a charging circuit of a dual charger, including a first OVP chip and a second OVP chip; the first OVP chip comprises a first voltage input pin and a first voltage output pin; the second OVP chip comprises a second voltage input pin and a second voltage output pin; the first voltage input pin is used for connecting a first charger, and the first voltage output pin is used for connecting equipment to be charged; the second voltage input pin is used for connecting a second charger, and the second voltage output pin is used for connecting the equipment to be charged; when the voltage of the first charger is greater than that of the second charger, a first voltage input pin and a first voltage output pin of the first OVP chip are communicated, a second voltage input pin and a second voltage output pin of the second OVP chip are disconnected, and the first charger charges the equipment to be charged through the first OVP chip; when the voltage of the first charger is equal to the voltage of the second charger, a first voltage input pin and a first voltage output pin of the first OVP chip are communicated, a second voltage input pin and a second voltage output pin of the second OVP chip are communicated, and the first charger charges the equipment to be charged through the first OVP chip and the second charger through the second OVP chip; when the voltage of the first charger is smaller than the voltage of the second charger, the first voltage input pin and the first voltage output pin of the first OVP chip are disconnected, the second voltage input pin and the second voltage output pin of the second OVP chip are communicated, and the second charger charges the equipment to be charged through the second OVP chip.
In a preferred embodiment, a first reverse current protection module is connected between the first voltage input pin and the first voltage output pin; when the voltage of the first voltage input pin is smaller than the voltage of the first voltage output pin, the first reverse current protection module is turned off, and the first voltage input pin and the first voltage output pin are disconnected; when the voltage of the first voltage input pin is greater than or equal to the voltage of the first voltage output pin, the first reverse current protection module is conducted, and the first voltage input pin and the first voltage output pin are communicated.
In a preferred embodiment, a second reverse current protection module is connected between the second voltage input pin and the second voltage output pin; when the voltage of the second voltage input pin is smaller than the voltage of the second voltage output pin, the second reverse current protection module is turned off, and the second voltage input pin and the second voltage output pin are disconnected; when the voltage of the second voltage input pin is greater than or equal to the voltage of the second voltage output pin, the second reverse current protection module is conducted, and the second voltage input pin and the second voltage output pin are communicated.
In a preferred embodiment, the first OVP chip further includes a first overcurrent protection setting pin, the first overcurrent protection setting pin is connected to a first overcurrent protection module, and the first overcurrent protection module is configured to set a current threshold of the first OVP chip.
In a preferred embodiment, the first overcurrent protection module includes a first resistor, a second resistor, and a first MOS transistor; one end of the first resistor is used for connecting a mainboard, the other end of the first resistor is connected with the first overcurrent protection setting pin, one end of the second resistor is connected with the first overcurrent protection setting pin, the other end of the second resistor is connected with the D pole of the first MOS tube, the S pole of the first MOS tube is grounded, and the G pole of the first MOS tube is used for connecting an EC chip.
In a preferred embodiment, the second OVP chip further includes a second over-current protection setting pin, the second over-current protection setting pin is connected to a second over-current protection module, and the second over-current protection module is configured to set a current threshold of the second OVP chip.
In a preferred embodiment, the second overcurrent protection module includes a third resistor, a fourth resistor, and a second MOS transistor; one end of the third resistor is used for being connected with the mainboard, the other end of the third resistor is connected with the second overcurrent protection setting pin, one end of the fourth resistor is connected with the second overcurrent protection setting pin, the other end of the fourth resistor is connected with the D pole of the second MOS tube, the S pole of the second MOS tube is grounded, and the G pole of the second MOS tube is used for being connected with the EC chip.
in a preferred embodiment, the first OVP chip further comprises a first enable pin, and the first enable pin is used for connecting a first control pin of a PD controller; the second OVP chip further comprises a second enable pin, and the second enable pin is used for connecting a second control pin of the PD controller.
In a preferred embodiment, the first OVP chip further includes a first voltage detection pin for detecting a voltage of the first voltage input pin; the second OVP chip further includes a second voltage detection pin, and the second voltage detection pin is used for detecting a voltage of the second voltage input pin.
In a preferred embodiment, the first voltage input pin is further connected to a first capacitor, and the first voltage output pin is further connected to a second capacitor; the second voltage input pin is further connected with a third capacitor, and the second voltage output pin is further connected with a fourth capacitor.
Compared with the prior art, according to the charging circuit of the double-charger, when two charging ports of equipment to be charged are respectively connected with the first charger and the second charger, if the voltage of the first charger is greater than that of the second charger, the first OVP chip is connected, the second OVP chip is disconnected, and the equipment to be charged is charged by the first charger through the first OVP chip; if the voltage of the first charger is smaller than that of the second charger, the first OVP chip is disconnected, the second OVP chip is communicated, and the second charger charges the equipment to be charged through the second OVP chip; therefore, when the first charger and the second charger charge the equipment to be charged at the same time, the charger with higher power is preferentially used for charging the equipment to be charged, and the charging efficiency is improved. And if the voltage of the first charger is equal to the voltage of the second charger, the first OVP chip and the second OVP chip are communicated, and the first charger charges the equipment to be charged through the first OVP chip and the second charger through the second OVP chip simultaneously, so that the power of an input power supply is further improved, the function of quick charging can be realized, and the cost of the charging circuit is lower.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic block diagram of a charging circuit of a dual charger provided by the present invention;
Fig. 2 is a circuit diagram of a charging circuit of the dual charger shown in fig. 1.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 and fig. 2 together, fig. 1 is a schematic block diagram of a charging circuit 100 of a dual charger according to the present invention, and fig. 2 is a circuit diagram of the charging circuit 100 of the dual charger shown in fig. 1. The charging circuit 100 of the dual charger provided by the invention comprises a first OVP (overvoltage protection) chip U1 and a second OVP chip U2.
The first OVP chip U1 includes a first voltage input pin VIN1 and a first voltage output pin VDRP 1; the second OVP chip U2 includes a second voltage input pin VIN2 and a second voltage output pin VDRP 2; the first voltage input pin VIN1 is used for connecting the first charger 10, and the first voltage output pin VDRP1 is used for connecting the device to be charged 20; the second voltage input pin VIN2 is used for connecting the second charger 30, and the second voltage output pin VDRP2 is used for connecting the device to be charged 20.
When the voltage of the first charger 10 is greater than the voltage of the second charger 30, the first voltage input pin VIN1 and the first voltage output pin VDRP1 of the first OVP chip U1 are connected, the second voltage input pin VIN2 and the second voltage output pin VDRP2 of the second OVP chip U2 are disconnected, and the first charger 10 charges the device to be charged 20 through the first OVP chip U1; when the voltage of the first charger 10 is equal to the voltage of the second charger 30, the first voltage input pin VIN1 and the first voltage output pin VDRP1 of the first OVP chip U1 are communicated, the second voltage input pin VIN2 and the second voltage output pin VDRP2 of the second OVP chip U2 are communicated, and the device 20 to be charged is charged by the first charger 10 through the first OVP chip U1 and the second charger 20 through the second OVP chip U2 at the same time; when the voltage of the first charger 10 is lower than the voltage of the second charger 30, the first voltage input pin VIN1 and the first voltage output pin VDRP1 of the first OVP chip U1 are disconnected, the second voltage input pin VIN2 and the second voltage output pin VDRP2 of the second OVP chip U2 are connected, and the second charger 30 charges the device to be charged 20 through the second OVP chip U2.
According to the charging circuit 100 of the dual-charger, when two charging ports of the device 20 to be charged are respectively connected with the first charger 10 and the second charger 30, if the voltage of the first charger 10 is greater than that of the second charger 30, the first OVP chip is connected, the second OVP chip U2 is disconnected, and the first charger 10 charges the device 20 to be charged through the first OVP chip U1; if the voltage of the first charger 10 is less than the voltage of the second charger 30, the first OVP chip U1 is disconnected, the second OVP chip U2 is connected, and the second charger 30 charges the device 20 to be charged through the second OVP chip U2; therefore, when the first charger 10 and the second charger 30 simultaneously charge the device to be charged, it is realized that the device to be charged 20 is charged by preferentially using the charger with a larger power, and the charging efficiency is improved. Moreover, if the voltage of the first charger 10 is equal to the voltage of the second charger 30, the first OVP chip and the second OVP chip U2 are both connected, and the first charger 10 charges the device 20 to be charged through the first OVP chip U1 and the second charger 20 through the second OVP chip U2, so that the power of the input power supply is further improved, the function of quick charging can be realized, and the cost of the charging circuit is low.
Further, a first reverse current protection module 40 is connected between the first voltage input pin VIN1 and the first voltage output pin VDRP 1; when the voltage of the first voltage input pin VIN1 is less than the voltage of the first voltage output pin VDRP1, the first reverse current protection module 40 is turned off and the first voltage input pin VIN1 and the first voltage output pin VDRP1 are disconnected; when the voltage of the first voltage input pin VIN1 is greater than or equal to the voltage of the first voltage output pin VDRP1, the first reverse current protection module 40 is turned on and the first voltage input pin VIN1 and the first voltage output pin VDRP1 are connected.
further, a second reverse current protection module 50 is connected between the second voltage input pin VIN2 and the second voltage output pin VDRP 2; when the voltage of the second voltage input pin VIN2 is less than the voltage of the second voltage output pin VDRP2, the second reverse current protection module 50 is turned off and the second voltage input pin VIN2 and the second voltage output pin VDRP2 are turned off; when the voltage of the second voltage input pin VIN2 is greater than or equal to the voltage of the second voltage output pin VDRP2, the second reverse current protection module 50 is turned on and the second voltage input pin VIN2 and the second voltage output pin VDRP2 are connected.
It can be understood that the first reverse current protection module 40 implements a function of turning off the first OVP chip when the input voltage of the first OVP chip U1 is less than the output voltage, and specifically, the first reverse current protection module 40 may be a MOS transistor disposed inside the first OVP chip U1 and connected to the first voltage input pin VIN1 and the first voltage output pin VDRP 1. The second reverse current protection module 50 implements a function of turning off the second OVP chip when the input voltage of the second OVP chip U2 is less than the output voltage, and specifically, the second reverse current protection module 50 may be a MOS transistor disposed inside the second OVP chip U2 and connected to the second voltage input pin VIN2 and the second voltage output pin VDRP 2.
Further, the first OVP chip U1 further includes a first over-current protection setting pin ALSET1, the first over-current protection setting pin ALSET1 is connected to the first over-current protection module 60, and the first over-current protection module 60 is configured to set a current threshold of the first OVP chip U1.
Specifically, the first overcurrent protection module 60 includes a first resistor R1, a second resistor R2, and a first MOS transistor Q1; one end of the first resistor R1 is used for connecting a motherboard, and the motherboard is used for providing a voltage VREF for the first overcurrent protection module 60 to set a threshold current value; the other end of the first resistor R1 is connected to a first overcurrent protection setting pin ALSET1, one end of the second resistor R2 is connected to the first overcurrent protection setting pin ALSET1, the other end of the second resistor R2 is connected to the D pole of the first MOS transistor Q1, the S pole of the first MOS transistor Q1 is grounded, and the G pole of the first MOS transistor Q1 is used for connecting an EC (embedded Controller) chip.
It can be understood that when the first charger 10 and the second charger 30 are simultaneously connected and the voltages are the same, the current limit of the device to be charged 20 is the sum of the current limits of the two OVP chips, so that the overcurrent of any one OVP chip can be avoided. The EC chip sends out a control signal 0.5A _ SEL1, when the current limiting condition of the circuit is met, the control signal 0.5A _ SEL1 is high, and the first MOS transistor Q1 is conducted; otherwise, the control signal 0.5A _ SEL1 is low, and the first MOS transistor Q1 is turned off, specifically, the first MOS transistor Q1 is an N-type MOS transistor. The first resistor R1 and the second resistor R2 are used for voltage division, specifically, the first resistor R1 is 100k Ω, and the second resistor R2 is 47k Ω.
Further, the second OVP chip U2 further includes a second over-current protection setting pin ALSET2, the second over-current protection setting pin ALSET2 is connected to the second over-current protection module 70, and the second over-current protection module 70 is configured to set a current threshold of the second OVP chip U2.
Specifically, the second overcurrent protection module 70 includes a third resistor R3, a fourth resistor R4, and a second MOS transistor Q2; one end of the third resistor R3 is used for connecting the motherboard, and the motherboard is used for providing a voltage VREF for the second overcurrent protection module 70 to set a threshold current value; the other end of the third resistor R3 is connected with a second overcurrent protection setting pin ALSET2, one end of the fourth resistor R4 is connected with a second overcurrent protection setting pin ALSET2, the other end of the fourth resistor R4 is connected with the D pole of the second MOS transistor Q2, the S pole of the second MOS transistor Q2 is grounded, and the G pole of the second MOS transistor Q2 is used for being connected with the EC chip.
It can be understood that the second overcurrent protection module 70 has the same principle as the first overcurrent protection module 60, and when the first charger 10 and the second charger 30 are connected at the same time and the voltages are the same, the current limit of the device to be charged 20 is the sum of the current limits of the two OVP chips, so that the overcurrent of any one OVP chip can be avoided. The EC chip sends out a control signal 0.5A _ SEL2, when the current limiting condition of the circuit is met, the control signal 0.5A _ SEL2 is high, and the second MOS transistor Q2 is conducted; otherwise, the control signal 0.5A _ SEL2 is low, and the second MOS transistor Q2 is turned off, specifically, the second MOS transistor Q2 is an N-type MOS transistor. The third resistor R3 and the fourth resistor R4 are used for voltage division, and specifically, the size of the third resistor R3 is 100k Ω, and the size of the fourth resistor R4 is 47k Ω.
In this embodiment, the first over-current protection setting pin ALSET1 is further connected to a fifth resistor R5, the second over-current protection setting pin ALSET2 is further connected to a sixth resistor R6, and the magnitudes of the fifth resistor R5 and the sixth resistor R6 are 100k Ω.
Further, the first OVP chip U1 further includes a first enable pin DRPEN1, the first enable pin DRPEN1 is used for connecting a first control pin SINK1_ CTRL of the PD controller; the second OVP chip U2 further includes a second enable pin DRPEN2, the second enable pin DRPEN2 is used for connecting a second control pin SINK2_ CTRL of the PD controller. It is understood that PD, Power delivery, is a fast charging protocol specification based on type-c port, and the PD controller enables the input Power VBUS (including VBUS1 and VBUS2) to input the SINK _ CTRL (including SINK1_ CTRL and SINK2_ CTRL) output control pins SINK _ CTRL according to the protocol specification. Specifically, when the VBUS1 has a voltage, the first control pin SINK1_ CTRL is high, and the first OVP chip U1 is enabled to operate; when VBUS2 has voltage, the SINK2_ CTRL is high, and the second OVP chip U2 is enabled. In this embodiment, the first enable pin DRPEN1 is further connected to a seventh resistor R7, the second enable pin DRPEN2 is further connected to an eighth resistor R8, and the size of the seventh resistor R7 and the eighth resistor R8 is 100K Ω.
Further, the first OVP chip U1 further includes a first voltage detection pin OVSET1, the first voltage detection pin OVSET1 is configured to detect a voltage of the first voltage input pin VIN1, and when the voltage of the first voltage detection pin OVSET1 exceeds 1v, the first OVP chip U1 stops operating. The second OVP chip U2 further includes a second voltage detection pin OVSET2, the second voltage detection pin OVSET2 is configured to detect a voltage of the second voltage input pin VIN2, and when the voltage of the second voltage detection pin OVSET2 exceeds 1v, the second OVP chip U2 stops operating.
In this embodiment, a ninth resistor R9 is further connected between the first voltage detection pin OVSET1 and the first voltage input pin VIN1, a tenth resistor R10 is further connected between the first voltage detection pin OVSET1 and the ground terminal, the ninth resistor R9 is 200k Ω, and the tenth resistor R10 is 100k Ω. An eleventh resistor R11 is further connected between the second voltage detection pin OVSET2 and the second voltage input pin VIN2, a twelfth resistor R12 is further connected between the second voltage detection pin OVSET2 and the ground terminal, the size of the eleventh resistor R11 is 200k Ω, and the size of the twelfth resistor R12 is 100k Ω.
Further, the first voltage input pin VIN1 is further connected to a first capacitor C1, the first voltage output pin VDRP1 is further connected to a second capacitor C2, the first capacitor C1 and the second capacitor C2 are respectively used for stabilizing voltages of the first voltage input pin VIN1 and the first voltage output pin VDRP1, the size of the first capacitor C1 is 4.7 μ F, and the size of the second capacitor C2 is 10 μ F; the second voltage input pin VIN2 is further connected to a third capacitor C3, the second voltage output pin VDRP2 is further connected to a fourth capacitor C4, the third capacitor C3 and the fourth capacitor C4 are respectively used for stabilizing the voltages of the second voltage input pin VIN2 and the second voltage output pin VDRP2, the size of the third capacitor C3 is 4.7 μ F, and the size of the fourth capacitor C4 is 10 μ F.
In this embodiment, the first OVP chip U1 further includes a first current sampling anode pin ISENP1 and a first current sampling cathode pin ISENN1, the first current sampling anode pin ISENP1 and the first current sampling cathode pin ISENN1 are both connected to the first voltage input terminal VIN1, a thirteenth resistor R13 is connected between the first current sampling anode pin ISENP1 and the first current sampling cathode pin ISENN1, and the size of the thirteenth resistor R13 is 0.01 Ω; the first current sampling anode pin ISENP1 and the first current sampling cathode pin ISENN1 are used for detecting actual output current, and specifically, the first OVP chip U1 acquires current information through a voltage difference between the first current sampling anode pin ISENP1 and the first current sampling cathode pin ISENN 1. The second OVP chip U2 further includes a second current sampling anode pin ISENP2 and a second current sampling cathode pin ISENN2, the second current sampling anode pin ISENP2 and the second current sampling cathode pin ISENN2 are both connected to the second voltage input terminal VIN2, a fourteenth resistor R14 is connected between the second current sampling anode pin ISENP2 and the second current sampling cathode pin ISENN2, and the size of the fourteenth resistor R14 is 0.01 Ω; the second current sampling anode pin ISENP2 and the second current sampling cathode pin ISENN2 are used for detecting actual output current, and specifically, the second OVP chip U2 obtains current information through a voltage difference between the second current sampling anode pin ISENP2 and the second current sampling cathode pin ISENN 2.
When the charging circuit 100 of the dual charger provided by the invention is applied to a notebook computer, for example, when two charging ports of the notebook computer are respectively connected to the first charger 10 and the second charger 30, if the voltage of the first charger 10 is 20V, the first control pin SINK1_ CTRL is high, the first OVP chip U1 is enabled to work, the first voltage INPUT pin VIN1 and the first voltage output pin VDRP1 are communicated through the first reverse current protection module 40, and the output voltage CHG _ INPUT1 of the first OVP chip U1 is equal to the INPUT voltage VBUS 1; assuming that the voltage of the second charger 30 is 15v or 12v or 9v or 5v, the second control pin SINK2_ CTRL is high, the second OVP chip U2 is enabled, however, the output voltage CHG _ INPUT2 of the second OVP chip U2 is greater than the INPUT voltage VBUS2, at this time, the second reverse current protection module 50 is turned off (in practical applications, it may be set that the second reverse current protection module 50 is turned off when the output voltage — the INPUT voltage >20 mV), and then the second OVP chip U2 is turned off, so that the first charger 10 charges the device 20 to be charged through the first OVP chip U1. Only when the voltage of the input voltage VBUS2 of the second charger 30 reaches 20v, and the first OVP chip U1 operates in a current-limiting state to cause a drop in the output voltage, that is, the voltage of the second voltage input pin VIN2 is greater than or equal to the voltage of the second voltage output pin VDRP2, the second reverse current protection module 50 is turned on and the second voltage input pin VIN2 and the second voltage output pin VDRP2 are connected, that is, the two OVP chips (U1 and U2) are turned on simultaneously to charge the notebook computer, specifically, the first voltage output pin VDRP1 and the second voltage output pin VDRP2 are both connected to an input terminal of a charging IC of the notebook computer to supply power to the charging IC.
The charging circuit 100 of the dual charger provided by the invention realizes that when the first charger 10 and the second charger 30 simultaneously charge the equipment to be charged, the charger with higher power is preferentially used for charging the equipment to be charged 20, thereby improving the charging efficiency. Moreover, if the voltage of the first charger 10 is equal to the voltage of the second charger 30, the first charger 10 charges the device 20 to be charged through the first OVP chip U1 and the second charger 20 charges the device 20 to be charged through the second OVP chip U2, so that the power of the input power is further increased, the function of quick charging can be realized, and the cost of the charging circuit is low.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A charging circuit of a double charger is characterized by comprising a first OVP chip and a second OVP chip; the first OVP chip comprises a first voltage input pin and a first voltage output pin; the second OVP chip comprises a second voltage input pin and a second voltage output pin; the first voltage input pin is used for connecting a first charger, and the first voltage output pin is used for connecting equipment to be charged; the second voltage input pin is used for connecting a second charger, and the second voltage output pin is used for connecting the equipment to be charged;
when the voltage of the first charger is greater than that of the second charger, a first voltage input pin and a first voltage output pin of the first OVP chip are communicated, a second voltage input pin and a second voltage output pin of the second OVP chip are disconnected, and the first charger charges the equipment to be charged through the first OVP chip;
When the voltage of the first charger is equal to the voltage of the second charger, a first voltage input pin and a first voltage output pin of the first OVP chip are communicated, a second voltage input pin and a second voltage output pin of the second OVP chip are communicated, and the first charger charges the equipment to be charged through the first OVP chip and the second charger through the second OVP chip;
When the voltage of the first charger is smaller than the voltage of the second charger, the first voltage input pin and the first voltage output pin of the first OVP chip are disconnected, the second voltage input pin and the second voltage output pin of the second OVP chip are communicated, and the second charger charges the equipment to be charged through the second OVP chip.
2. The charging circuit of a dual charger of claim 1, wherein a first reverse current protection module is connected between the first voltage input pin and the first voltage output pin; when the voltage of the first voltage input pin is smaller than the voltage of the first voltage output pin, the first reverse current protection module is turned off, and the first voltage input pin and the first voltage output pin are disconnected; when the voltage of the first voltage input pin is greater than or equal to the voltage of the first voltage output pin, the first reverse current protection module is conducted, and the first voltage input pin and the first voltage output pin are communicated.
3. The charging circuit of a dual charger of claim 2, wherein a second reverse current protection module is connected between the second voltage input pin and the second voltage output pin; when the voltage of the second voltage input pin is smaller than the voltage of the second voltage output pin, the second reverse current protection module is turned off, and the second voltage input pin and the second voltage output pin are disconnected; when the voltage of the second voltage input pin is greater than or equal to the voltage of the second voltage output pin, the second reverse current protection module is conducted, and the second voltage input pin and the second voltage output pin are communicated.
4. The charging circuit of dual charger of claim 3, wherein said first OVP chip further comprises a first over-current protection setting pin, said first over-current protection setting pin is connected to a first over-current protection module, said first over-current protection module is used for setting a current threshold of said first OVP chip.
5. The charging circuit of a dual charger of claim 4, wherein the first over-current protection module comprises a first resistor, a second resistor and a first MOS transistor; one end of the first resistor is used for connecting a mainboard, the other end of the first resistor is connected with the first overcurrent protection setting pin, one end of the second resistor is connected with the first overcurrent protection setting pin, the other end of the second resistor is connected with the D pole of the first MOS tube, the S pole of the first MOS tube is grounded, and the G pole of the first MOS tube is used for connecting an EC chip.
6. The charging circuit of dual charger of claim 5, wherein said second OVP chip further comprises a second over-current protection setting pin, said second over-current protection setting pin is connected to a second over-current protection module, said second over-current protection module is configured to set a current threshold of said second OVP chip.
7. The charging circuit of a dual charger of claim 6, wherein the second over-current protection module comprises a third resistor, a fourth resistor and a second MOS transistor; one end of the third resistor is used for being connected with the mainboard, the other end of the third resistor is connected with the second overcurrent protection setting pin, one end of the fourth resistor is connected with the second overcurrent protection setting pin, the other end of the fourth resistor is connected with the D pole of the second MOS tube, the S pole of the second MOS tube is grounded, and the G pole of the second MOS tube is used for being connected with the EC chip.
8. The charging circuit of dual charger of claim 7 wherein said first OVP chip further comprises a first enable pin for connecting to a first control pin of a PD controller; the second OVP chip further comprises a second enable pin, and the second enable pin is used for connecting a second control pin of the PD controller.
9. The charging circuit of a dual charger of claim 8, wherein the first OVP chip further comprises a first voltage detection pin for detecting a voltage of the first voltage input pin; the second OVP chip further includes a second voltage detection pin, and the second voltage detection pin is used for detecting a voltage of the second voltage input pin.
10. The charging circuit of a dual charger of claim 9, wherein said first voltage input pin is further connected to a first capacitor, and said first voltage output pin is further connected to a second capacitor; the second voltage input pin is further connected with a third capacitor, and the second voltage output pin is further connected with a fourth capacitor.
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